DS28E07P+

DS28E07 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 23

Technical content

The DS28E07 is a 1024-bit, 1-Wire® EEPROM chip orga- nized as four memory pages of 256 bits each. Data is written to an 8-byte scratchpad, verified, and then copied to the EEPROM memory. As a special feature, the four user memory pages can individually be write protected or put in EPROM-emulation mode, where bits can only be changed from a 1 to a 0 state. Each device has its own guaranteed unique 64-bit ROM identification number (ROM ID) that is factory programmed into the chip. The communication follows the 1-Wire protocol with the ROM ID acting as node address in the case of a multiple-device 1-Wire network.

Applications

• Accessory/PCB Identification
• Medical Sensor Calibration Data Storage
• Analog Sensor Calibration Including IEEE P1451.4 Smart Sensors
• Ink and Toner Print Cartridge Identification
• After-Market Management of Consumables Benefits and Features
• Partitioning of Memory Provides Greater Flexibility in Programming User Data
• 1024 Bits of EEPROM Memory Organized as Four Pages of 256 Bits
• Individual Memory Pages Can Be Permanently Write Protected or Put in EPROM-Emulation Mode rite to 0)
• Advanced 1-Wire Protocol Minimizes Interface to Just Single IO Reducing Required Pin Count and Enhancing Reliability
• Unique Factory-Programmed, Unalterable 64-Bit Identification Number Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise Communicates to Host with a Single Digital Signal at 15.4kbps or 125kbps Using 1-Wire Protocol Reads and W rites over a Wide Voltage Range from 3.0V to 5.25V from -40°C to +85°C
• ±8kV HBM ESD Protection (typ) for IO Pin Ordering Information appears at end of data sheet. 1-Wire is a registered trademark of Maxim Integrated Products, Inc. 19-7674; Rev 7; 4/22 Typical Application Circuit µC PIOX PIOY 100 kΩ DS28E07 RPUP *BSS84 IO *NOTE: OPTIONAL LOW-IMPEDANCE BYPASS OR EQUALLY DRIVE LOGIC ‘1’ WITH PIOY BIDIRECTIONAL GND V CC GND OPEN DRAIN PORT 1kΩ VCC 1024-Bit, 1-Wire EEPROM DS28E07 Evaluation Kit Available Design Resources Support © 2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Click here to ask an associate for production status of specific part numbers.

(Note 1) (TA = -40°C to +85°C, unless otherwise noted.) (Note 2) Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: GENERAL DATA 1-Wire Pullup Voltage VPUP (Note 3) 3.0 5.25 V 1-Wire Pullup Resistance RPUP (Note 3, 4) 300 2200 Ω Input Capacitance CIO (Notes 4, 5) 1000 pF Input Load Current IL IO pin at VPUP 0.05 1.75 6.7 µA High-to-Low Switching Threshold VTL (Notes 6, 7, 8) 0.65 x VPUP V Input Low Voltage VIL (Notes 3, 9) 0.5 V Low-to-High Switching Threshold VTH (Notes 6, 7, 10) 0.75 x VPUP V Switching Hysteresis VHY (Notes 6, 7, 11) 0.3 V Output Low Voltage VOL IOL = 4mA 0.4 V IOL = 10mA, 4.75V ≤ VPUP ≤ 5.25V 0.5 Recovery Time (Notes 3, 13) tREC Standard speed, RPUP = 2200Ω 5 µsOverdrive speed, RPUP = 2200Ω 3 Overdrive speed, directly prior to reset pulse, RPUP = 2200Ω 5 Rising-Edge Hold-off Time (Notes 6, 14) tREH Standard speed 1.3 µs Overdrive speed N/A (0) Time Slot Duration (Notes 3, 15) tSLOT Standard speed 65 µs Overdrive speed 9 www.analog.com Analog Devices │ 2 DS28E07 1024-Bit, 1-Wire EEPROM Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics

Electrical Characteristics

(TA = -40°C to +85°C, unless otherwise noted.) (Note 2) Note 2: Limits are 100% production tested at T A = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Typical values are at T A = +25°C. Note 3: System requirement. Note 4: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. Note 5: Maximum value represents the internal parasite capacitance when V PUP is first applied. Once the parasite capacitance is charged, it does not affect normal communication. Note 6: Guaranteed by design and/or characterization only. Not production tested. Note 7: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of V PUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower V PUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Note 8: Voltage below which, during a falling edge on IO, a logic-zero is detected. Note 9: The voltage on IO must be less than or equal to V ILMAX at all times the master is driving IO to a logic-zero level. Note 10: Voltage above which, during a rising edge on IO, a logic-one is detected. Note 11: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least V HY to be detected as logic-zero. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: 1-Wire RESET, PRESENSE-DETECT CYCLE Reset Low Time (Note 3) tRSTL Standard speed 480 640 µs Overdrive speed 48 80 Presence Detect High Time tPDH Standard speed 15 60 µs Overdrive speed 2 6 Presence Detect Low Time tPDL Standard speed 60 240 µs Overdrive speed 8 24 Presence-Detect Sample Time (Notes 3, 16) tMSP Standard speed 60 75 µs Overdrive speed 6 10 IO PIN: 1-Wire WRITE Write-Zero Low Time (Notes 3, 17) tW0L Standard speed 60 120 µs Overdrive speed 6 15.5 Write-One Low Time (Notes 3, 17) tW1L Standard speed 1 15 µs Overdrive speed 0.25 2 IO PIN: 1-Wire READ Read Low Time (Notes 3, 18) tRL Standard speed 5 15 - δ µs Overdrive speed 0.25 2 - δ Read Sample Time (Notes 3, 18) tMSR Standard speed tRL + δ 15 µs Overdrive speed tRL + δ 2 EEPROM Programming Current IPROG (Notes 6, 19) 1.2 mA Programming Time tPROG (Note 20) 12 ms Write/Erase Cycles (Endurance) NCY TA = +25°C (Notes 21, 22) , TA = +85°C (Notes 21, 22) 10000 — Data Retention tDR TA = +85°C (Notes 23, 24, 25) 10 Years www.analog.com Analog Devices │ 3 DS28E07 1024-Bit, 1-Wire EEPROM Electrical Characteristics (continued)

Note 13: Applies to a single device attached to a 1-Wire line. Note 14: The earliest recognition of a negative edge is possible at t REH after VTH has been previously reached. Note 15: Defines maximum possible bit rate. Equal to 1/(t W0LMIN + tRECMIN). Note 16: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS28E07 present. The power-up pres- ence detect pulse could be outside this interval but will be complete within 2ms after power-up. Note 17: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V IL to VTH. The actual maximum duration for the master to pull the line low is t W1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. Note 18: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V IL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is t RLMAX + tF. Note 19: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval should be such that the voltage at IO is greater than or equal to V PUPMIN. If VPUP in the system is close to V PUPMIN, a low impedance bypass of RPUP, which can be activated during programming, may need to be added. Note 20: Interval begins tREHMAX after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from I PROG to IL. Note 21: Write-cycle endurance is tested in compliance with JESD47G. Note 22: Not 100% production tested; guaranteed by reliability monitor sampling. Note 23: Data retention is tested in compliance with JESD47G. Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. Note 25: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem- peratures is not recommended. www.analog.com Analog Devices │ 4 DS28E07 1024-Bit, 1-Wire EEPROM

N.C. IO GND TO-92 TOP VIEW N.C. IO GND N.C. N.C. N.C. TSOC DS28E07 FRONT VIEW (T&R VERSION) FRONT VIEWSIDE VIEW 1 6N.C. N.C. 2 5IO N.C. 3 4GND N.C. TDFN (3mm x 3mm) TOP VIEW 2807 ymrrF *EP *EXPOSED PAD NOTE:THE S FN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL CONTACT APPLICATIONS ONLY, NOT FOR SOLDE RING. FOR MORE INFORMATION, REFER TO APPLICATION NOTE 4132: ATTA CHMENT METHODS FOR THE ELE CTRO-MECHANICAL 1-WIRE CONTACT PACK AGE. BOTTOM VIEW DS28E07G SFN (6mm x 6mm x 0.9mm) 1 2 IO GND BOTTOM VIEW DS28E07GA SFN (3.5mm x 6.5mm x 0.75mm) IO GND BOTTOM VIEW DS28E07GB SFN (3.5mm x 5mm x 0.35mm)

12 IOGND

www.analog.com Analog Devices │ 5 DS28E07 1024-Bit, 1-Wire EEPROM Pin Configurations

be write protected or put in EPROM emulation mode. Write protection prevents changes to the memory data. after-market management of consumables. 64 bit of administrative data memory, and a 64-bit ROM ID. 2 2 2 1 IO 1-Wire Bus Interface. Open-drain signal requires an external pullup resistor. Introduction for additional information. Figure 1. Block Diagram

4 PAGES OF

256 BITS EACH

64 BITS

memory is unprotected and its contents are undefined. revision in hexadecimal notation, e.g., A1h. Table 1. Memory Resources Figure 5. Memory Map the address nor activate any function.

000b, and 8 full bytes must be written into the scratchpad. user memory page open for unrestricted write access. affected memory page must first be programmed to FFh. with the current data) in the device. protected user memory pages (i.e., refresh) are blocked. address. Writing data to the scratchpad clears this flag. Figure 6. Address Registers

To write data to the DS28E07, the scratchpad must be used as intermediate storage. First, the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratch - pad. Note that Copy Scratchpad commands must be per - formed on 8-byte boundaries, i.e., the three LSBs of the target address (T2, T1, T0) must be equal to 000b. If T[2:0] are sent with nonzero values, the copy function is blocked. Under certain conditions (see the Write Scratchpad [0Fh] section) the master receives an inverted CRC-16 of the command, address (actual address sent), and data at the end of the Write Scratchpad command sequence. Knowing this CRC value, the master can compare it to the value it has calculated to decide if the communication was suc - cessful and proceed to the Copy Scratchpad command. If the master could not receive the CRC-16, it should send the Read Scratchpad command to verify data integrity. As a preamble to the scratchpad data, the DS28E07 repeats the target address TA1 and TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the scratchpad, or there was a loss of power since data was last written to the scratchpad. The master does not need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag together with a cleared PF flag indicates that the device did not recognize the Write command. If everything went correctly, both flags are cleared. Now the master can continue reading and verifying every data byte. After the master has verified the data, it can send the Copy Scratchpad command, for example. This command must be followed exactly by the data of the three address registers, TA1, TA2, and E/S. The master should obtain the contents of these registers by reading the scratchpad. As well, a strong pullup (i.e., low impedance bypass) turns on after the Copy Scratchpad sequence for the duration of tPROG to enhance power delivery. The strong pullup can comprise an external FET circuitry or by driving logic 1 on the PIO of a host system with a good low-impedance drive strength. If neither option is available then the designer can size R PUP accordingly for proper power delivery as to not violate VPUP minimum. Memory Function Commands Figure 7 describes the protocols necessary for accessing the memory of the DS28E07. An example on how to use these functions to write to and read from the device is in the Memory Function Example section. The communica - tion between the master and the DS28E07 takes place either at standard speed (default, OD = 0) or at overdrive speed (OD = 1). If not explicitly set into overdrive mode, the DS28E07 assumes standard speed. Write Scratchpad [0Fh] The Write Scratchpad command applies to the user memory and the writable addresses of the administra - tive data. For the scratchpad data to be valid for copying to the array, the user must perform a Write Scratchpad command of 8 bytes starting at a valid row boundary. The Write Scratchpad command accepts invalid addresses and partial rows, but subsequent Copy Scratchpad com- mands are blocked. After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data is writ- ten to the scratchpad starting at the byte offset of T[2:0]. The E/S bits E[2:0] are loaded with the starting byte offset and increment with each subsequent byte. Effectively, E[2:0] is the byte offset of the last full byte written to the scratchpad. Only full data bytes are accepted. When executing the Write Scratchpad command, the CRC generator inside the DS28E07 (Figure 13) calcu- lates a CRC of the entire data stream, starting at the com- mand code and ending at the last data byte as sent by the master. This CRC is generated using the CRC-16 polyno- mial by first clearing the CRC generator and then shifting in the command code (0Fh) of the Write Scratchpad com- mand, the target addresses (TA1 and TA2), and all the data bytes. Note that the CRC-16 calculation is performed with the actual TA1 and TA2 and data sent by the master. The master can end the Write Scratchpad command at any time. However, if the end of the scratchpad is reached (E[2:0] = 111b), the master can send 16 read time slots and receive the CRC generated by the DS28E07. If a Write Scratchpad command is attempted to a write- protected location, the scratchpad is loaded with the data already existing in memory rather than the data transmit- ted. Similarly, if the target address page is in EPROM mode, the scratchpad is loaded with the bitwise logical AND of the transmitted data and data already existing in memory. www.analog.com Analog Devices │ 10 DS28E07 1024-Bit, 1-Wire EEPROM

Figure 7a. Memory Function Flowchart BUS MASTER Tx MEMORY FUNCTION COMMAND BUS MASTER Tx BUS MASTER Rx AND E/S BYTE BUS MASTER Rx DATA BYTE FROM SCRATCHPAD MASTER Tx DATA BYTE TO SCRATCHPAD APPLIES ONLY IF THE MEMORY AREA IS NOT PROTECTED. IF WRITE PROTECTED, THE DS28E07 COPIES THE DATE BYTE FROM THE TARGET ADDRESS INTO THE SCRATCHPAD. IF IN EPROM MODE, THE DS28E07 LOADS THE BITWISE LOGICAL AND OF THE TRANSMITTED BYTE AND THE DATA BYTE FROM THE TARGETED ADDRESS INTO THE SCRATCHPAD. BUS MASTER Rx "1"s DS28E07 INCREMENTS E[2:0] PF = 0 DS28E07 SETS PF = 1 CLEARS AA = 0 SETS E[2:0] = T[2:0] 0Fh WRITE SCRATCHPAD? N Y N Y N Y Y Y N N MASTER Tx RESET? E[2:0] = 7? T[2:0] = 0? MASTER Tx RESET? DS28E07 SETS SCRATCHPAD BYTE COUNTER = T[2:0] AAh READ SCRATCHPAD? N Y DS28E07 Tx CRC-16 OF COMMAND, ADDRESS, AND DATA BYTES AS THEY WERE SENT BY THE BUS MASTER BUS MASTER Rx "1"s Y N MASTER Tx RESET? BUS MASTER Rx CRC-16 OF COMMAND, ADDRESS, E/S BYTE, AND DATA BYTES AS SENT BY THE DS28E07 Y N MASTER Tx RESET? Y BYTE COUNTER = E[2:0]? FROM ROM FUNCTIONS FLOWCHART (FIGURE 9) TO ROM FUNCTIONS FLOWCHART (FIGURE 9) DS28E07 INCREMENTS BYTE COUNTER N TO FIGURE 7b FROM FIGURE 7b www.analog.com Analog Devices │ 11 DS28E07 1024-Bit, 1-Wire EEPROM

Figure 7b. Memory Function Flowchart (continued) BUS MASTER Tx APPLICABLE TO ALL R/W MEMORY LOCATIONS. DURATION: tPROG * * 1-Wire IDLE HIGH FOR POWER. DS28E07 COPIES SCRATCHPAD DATA TO ADDRESS BUS MASTER Rx "1"s AA = 1 BUS MASTER Rx "1"s MASTER Tx RESET? N Y N N MASTER Tx RESET? Y MASTER Tx RESET? BUS MASTER Tx AND E/S BYTE 55h COPY SCRATCHPAD? N Y Y Y N DS28E07 Tx "0" DS28E07 Tx "1" F0h READ MEMORY? N Y Y N AUTH. CODE MATCH? Y N Y N N T[15:0] < 0090h? PF = 0? ADDRESS < 90h? Y COPY PROTECTED? BUS MASTER Rx "1"s MASTER Tx RESET?N Y DS28E07 SETS MEMORY ADDRESS = (T[15:0]) BUS MASTER Rx DATA BYTE FROM MEMORY ADDRESS Y N N MASTER Tx RESET? ADDRESS < 8Fh? N Y MASTER Tx RESET? DS28E07 INCREMENTS ADDRESS COUNTER Y TO FIGURE 7a FROM FIGURE 7a www.analog.com Analog Devices │ 12 DS28E07 1024-Bit, 1-Wire EEPROM

A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS28E07 supports both a standard and overdrive communication speed of 15.4kbps (max) and 125kbps (max), respectively. The value of the pullup resistor primarily depends on the network size and load conditions. The DS28E07 requires a pullup resistor of 2.2kΩ (max) at any speed. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 15.5μs (overdrive speed) or more than 120μs (standard speed), one or more devices on the bus could be reset. Transaction Sequence The protocol for accessing the DS28E07 through the 1-Wire port is as follows:

• Initialization
• ROM function command
• Memory function command
• Transaction/data Initialization All transactions on the 1-Wire bus begin with an initializa- tion sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The pres- ence pulse lets the bus master know that the DS28E07 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. 1-Wire ROM Function Commands Once the bus master has detected a presence, it can issue one of the seven ROM function commands that the DS28E07 supports. All ROM function commands are 8 bits long. A list of these commands follows. See Figure 9. Read ROM [33h] The Read ROM command allows the bus master to read the DS28E07’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC. Match ROM [55h] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS28E07 on a multidrop bus. Only the DS28E07 that exactly matches the 64-bit ROM sequence responds to the subsequent memory function command. All other slaves wait for a reset pulse. This command can be used with a single device or multiple devices on the bus. Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their ROM ID numbers. By taking advantage of the wired-AND property of the bus, the master can use a pro- cess of elimination to identify the ID of all slave devices. For each bit in the ID number, starting with the least sig- nificant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its ID number bit. On the second slot, each slave device participating in the search outputs the complemented value of its ID number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choos- ing which state to write, the bus master branches in the search tree. After one complete pass, the bus master knows the ROM ID number of a single device. Additional passes identify the ID numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. Skip ROM [CCh] This command can save time in a single-drop bus sys- tem by allowing the bus master to access the memory functions without providing the 64-bit ROM ID. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM com- mand, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). www.analog.com Analog Devices │ 14 DS28E07 1024-Bit, 1-Wire EEPROM

Figure 9a. ROM Functions Flow Chart DS28E07 Tx PRESENCE PULSE BUS MASTER Tx RESET PULSE BUS MASTER Tx ROM FUNCTION COMMAND DS28E07 Tx CRC BYTE DS28E07 Tx FAMILY CODE (1 BYTE) DS28E07 Tx SERIAL NUMBER (6 BYTES) RC = 0 MASTER Tx BIT 0 RC = 0 RC = 0 RC = 0 OD = 0 YY Y Y Y Y Y Y 33h READ ROM COMMAND? N 55h MATCH ROM COMMAND? BIT 0 MATCH? BIT 0 MATCH? N N N N N N N F0h SEARCH ROM COMMAND? OD RESET PULSE? N N CCh SKIP ROM COMMAND? N RC = 1 MASTER Tx BIT 1 MASTER Tx BIT 63 BIT 1 MATCH? BIT 63 MATCH? Y Y RC = 1 FROM MEMORY FUNCTIONS FLOWCHART (FIGURE 7) TO MEMORY FUNCTIONS FLOWCHART (FIGURE 7) DS28E07 Tx BIT 0 DS28E07 Tx BIT 0 MASTER Tx BIT 0 BIT 1 MATCH? BIT 63 MATCH? DS28E07 Tx BIT 1 DS28E07 Tx BIT 1 MASTER Tx BIT 1 DS28E07 Tx BIT 63 DS28E07 Tx BIT 63 MASTER Tx BIT 63 Y TO FIGURE 9b TO FIGURE 9b FROM FIGURE 9b FROM FIGURE 9b www.analog.com Analog Devices │ 15 DS28E07 1024-Bit, 1-Wire EEPROM

Figure 9b. ROM Functions Flow Chart (continued) RC = 0; OD = 1 RC = 0; OD = 1 N BIT 0 MATCH? YN RC = 1? Y A5h RESUME COMMAND? N Y 3Ch OVERDRIVE- SKIP ROM? N Y 69h OVERDRIVE- MATCH ROM? FROM FIGURE 9a FROM FIGURE 9a TO FIGURE 9a TO FIGURE 9a N Y Y N MASTER Tx RESET? YMASTER Tx RESET? N BIT 1 MATCH? MASTER Tx BIT 0 MASTER Tx BIT 1 OD = 0 N OD = 0 N OD = 0 Y RC = 1 BIT 63 MATCH? MASTER Tx BIT 63 Y www.analog.com Analog Devices │ 16 DS28E07 1024-Bit, 1-Wire EEPROM

drain pulldowns produce a wired-AND result). drop bus and to simultaneously set it in overdrive mode. presence pulse, the bus master initiates all falling edges. logical level, not triggering any events. Figure 10. Initialization Procedure: Reset and Presence Pulse

Figure 10 shows the initialization sequence required to begin any communication with the DS28E07. A reset pulse followed by a presence pulse indicates that the DS28E07 is ready to receive data, given the correct ROM and memory function command. If the bus master uses slew- rate control on the falling edge, it must pull down the line for tRSTL + tF to compensate for the edge. A t RSTL dura- tion of 480μs or longer exits the overdrive mode, returning the device to standard speed. If the DS28E07 is in over - drive mode and t RSTL is no longer than 80μs, the device remains in overdrive mode. If the device is in overdrive mode and t RSTL is between 80μs and 480μs, the device resets, but the communication speed is undetermined. After the bus master has released the line it goes into receive mode. Now the 1-Wire bus is pulled to V PUP through the pullup resistor or, in the case of a special driver chip, through the active circuitry. When the thresh- old VTH is crossed, the DS28E07 waits for tPDH and then transmits a presence pulse by pulling the line low for tPDL. To detect a presence pulse, the master must test the logi- cal state of the 1-Wire line at t MSP. The t RSTH window must be at least the sum of t PDH- MAX, tPDLMAX, and tRECMIN. Immediately after t RSTH is expired, the DS28E07 is ready for data communication. In a mixed population network, tRSTH should be extended to minimum 480μs at standard speed and 48μs at overdrive speed to accommodate other 1-Wire devices. Read/Write Time Slots Data communication with the DS28E07 takes place in time slots that carry a single bit each. Write time slots transport data from bus master to slave. Read time slots transfer data from slave to master. Figure 11 illustrates the definitions of the write and read time slots. All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the threshold V TL, the DS28E07 starts its internal timing generator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot. Master-to-Slave For a write-one time slot, the voltage on the data line must have crossed the V TH threshold before the write- one low time t W1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the VTH threshold until the write-zero low time tW0LMIN is expired. For the most reliable communication, the voltage on the data line should not exceed V ILMAX during the entire tW0L or t W1L window. After the V TH threshold has been crossed, the DS28E07 needs a recovery time tREC before it is ready for the next time slot. Slave-to-Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below V TL until the read low time t RL is expired. During the t RL window, when responding with a 0, the DS28E07 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS28E07 does not hold the data line low at all, and the voltage starts rising as soon as tRL is over. The sum of tRL + δ (rise time) on one side and the internal timing generator of the DS28E07 on the other side define the master sampling window (t MSRMIN to t MSRMAX), in which the master must perform a read from the data line. For the most reliable communication, t RL should be as short as permissible, and the master should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until t SLOT is expired. This guarantees sufficient recovery time tREC for the DS28E07 to get ready for the next time slot. Note that t REC speci- fied herein applies only to a single DS28E07 attached to a 1-Wire line. For multidevice configurations, t REC must be extended to accommodate the additional 1-Wire device input capacitance. Alternatively, an interface that performs active pullup during the 1-Wire recovery time such as the special 1-Wire line drivers can be used. www.analog.com Analog Devices │ 18 DS28E07 1024-Bit, 1-Wire EEPROM

Figure 11. Read/Write Timing Diagrams

end that is less sensitive to noise. a new time slot (Figure 12, Case C, tGL ≥ tREH). determine if the ROM data has been received error-free. CRC, as shown in the command flowchart (Figure 7). portion of the data with the CRC error. and all the data bytes as they were sent by the bus master. The DS28E07 transmits this CRC only if E[2:0] = 111b. the reading continues through the end of the scratchpad. Figure 12. Noise Suppression Scheme

RST 1-Wire Reset Pulse generated by master. PD 1-Wire Presence Pulse generated by slave. Select Command and data to satisfy the ROM function protocol (e.g. Skip ROM [CCh], etc…). WS Command “Write Scratchpad [0Fh]”. RS Command “Read Scratchpad [AAh]”. CPS Command “Copy Scratchpad [55h]”. RM Command “Read Memory [F0h]”. TA-E/S Target Address TA1, TA2 with E/S byte. <8 – T2:T0 bytes> Transfer of as many bytes as needed to reach the end of the scratchpad for a given target address. <data to EOM> Transfer of as many data bytes as are needed to reach the end of the memory. CRC16 Transfer of an inverted CRC16. FF loop Indefinite loop where the master reads FF bytes. AA loop Indefinite loop where the master reads AA bytes. Programming Data transfer to EEPROM; no activity on the 1-Wire bus permitted during this time. Figure 13. CRC-16 Hardware Description and Polynomial

+Denotes a lead-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. PART TEMP RANGE PIN-PACKAGE DS28E07+ -40°C to +85°C 3 TO-92 DS28E07+T -40°C to +85°C 3 TO-92 (2k pcs) DS28E07P+ -40°C to +85°C 6 TSOC DS28E07P+T -40°C to +85°C 6 TSOC (4k pcs) DS28E07Q+T -40°C to +85°C 6 TDFN-EP* (2.5k pcs) DS28E07G+T -40°C to +85°C 2 SFN (6mm x 6mm) (2.5k pcs) DS28E07GA+T -40°C to +85°C 2 SFN (3.5mm x 6.5mm) (2.5k pcs) DS28E07GB+T -40°C to +85°C 2 SFN (3.5mm x 5mm) (2.5k pcs) PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

3 TO-92

(Bulk) Q3+1 21-0248 —

6 TSOC D6+1 21-0382 90-0321

6 TDFN-EP T633+2 21-0137 90-0058

2 SFN

(6mm x 6mm) G266N+1 21-0390 — (3.5mm x 6.5mm) T23A6N+1 21-0575 90-0431 (3.5mm x 5mm) S23A5N+1 21-0661 90-0398 Write Scratchpad (CANNOT FAIL) RST PD Select WS TA <8 – T2:T0 bytes> CRC16 FF loop Read Scratchpad (CANNOT FAIL) RST PD Select RS TA-E/S <8 – T2:T0 bytes> CRC16 FF loop Copy Scratchpad (success) RST PD Select CPS TA-E/S Programming AA loop Copy Scratchpad (invalid ADDRESS or PF = 1 or COPY protected) RST PD Select CPS TA-E/S FF loop Read Memory (success) RST PD Select RM TA <data to EOM> FF loop Read Memory (invalid address) RST PD Select RM TA FF loop www.analog.com Analog Devices │ 22 DS28E07 1024-Bit, 1-Wire EEPROM 1-Wire Communication Examples Chip Information PROCESS: CMOS Ordering Information Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

0 9/15 Initial release — 1 5/16 Removed future product references 22 2 1/17 Added row to Output Low Voltage parameter and removed Note 12 (remaining Notes were not renumbered per request) 2, 4 3 7/21 Updated Electrical Characteristics table 3 4 9/21 Updated Pin Configurations, Pin Description table, Ordering Information table, and Package Information table 5, 6, 22 5 12/21 Updated Ordering Information table 22 6 1/22 Updated Electrical Characteristics table 3 7 4/22 Updated Ordering Information table 22 DS28E07 1024-Bit, 1-Wire EEPROM

Revision History

www.analog.com Analog Devices │ 23 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.