DS28E05

DS28E05 MAXIM | Alldatasheet

Document overview

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Technical content

Features

• Single-Contact 1-Wire Interface
• 112 Bytes User EEPROM with 1K Write Cycles
• Programmable Write Protection and OTP EPROM Emulation Modes for User Memory
• Unique Factory-Programmed 64-Bit ROM ID Number
• Communicates with Host at Up to 76.9kbps (Overdrive Only)
• Operating Range: 3.3V ±10%, -40°C to +85°C
• ±8kV HBM ESD Protection (typ) on IO Pin
• 3-Pin SOT23 and 6-Pin TSOC Packages 19-6568; Rev 0; 12/12 Ordering Information appears at end of data sheet. For related parts and recommended products to use with this part, refer to www.maximintegrated.com/DS28E05.related. Typical Application Circuit 1-Wire is a registered trademark of Maxim Integrated Products, Inc. IO RPUP VCC µC GND DS28E05

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Electrical Characteristics

(TA = -40°C to +85°C, unless otherwise noted.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: GENERAL DATA 1-Wire Pullup Voltage VPUP (Note 2) 2.97 3.63 V 1-Wire Pullup Resistance RPUP VPUP = 3.3V ±10% (Note 3) 300 1500 Ω Input Capacitance CIO (Notes 4, 5) 1500 pF Input Load Current IL IO pin at VPUP 5 20 µA High-to-Low Switching Threshold VTL (Notes 6, 7) 0.65 x VPUP V Input Low Voltage VIL (Notes 2, 8) 0.3 V Low-to-High Switching Threshold VTH (Notes 6, 9) 0.75 x VPUP V Switching Hysteresis VHY (Notes 6, 10) 0.3 V Output Low Voltage VOL IOL = 4mA (Note 11) 0.4 V Recovery Time tREC RPUP = 1500Ω (Notes 2, 12) 5 µs Time Slot Duration tSLOT (Notes 2, 13) 13 µs IO PIN: 1-Wire RESET, PRESENCE DETECT CYCLE Reset Low Time tRSTL (Note 2) 48 80 µs Reset High Time tRSTH (Note 14) 48 µs Presence Detect Sample Time tMSP (Notes 2, 15) 8 10 µs IO PIN: 1-Wire WRITE Write-Zero Low Time tW0L (Notes 2, 16) 8 16 µs Write-One Low Time tW1L (Notes 2, 16) 1 2 µs IO PIN: 1-Wire READ Read Low Time tRL (Notes 2, 17) 1 2 - δ µs Read Sample Time tMSR (Notes 2, 17) tRL + δ 2 µs EEPROM Programming Current IPROG VPUP = 3.63V (Notes 5, 18) 400 µA Programming Time for a 16-Bit Segment tPROG (Note 19) 16 ms Write/Erase Cycling Endurance NCY TA = +85°C (Notes 20, 21) 1000 — Data Retention tDR TA = +85°C (Notes 22, 23, 24) 10 Years

www.maximintegrated.com Maxim Integrated │ 3 Electrical Characteristics (continued) (TA = -40°C to +85°C, unless otherwise noted.) (Note 1) Note 1: Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and rel- evant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed. Note 2: System requirement. Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. Note 4: Typical value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is charged, it does not affect normal communication. Note 5: Guaranteed by design and/or characterization only. Not production tested. Note 6: V TL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected. Note 8: The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic 0 level. Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected. Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0. Note 11: The I-V characteristic is linear for voltages less than 1V. Note 12: Applies to a single device attached to a 1-Wire line. Note 13: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN). Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired. Note 15: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS28E05 present. The power-up pres - ence detect pulse could be outside this interval but will be complete within 2ms after power-up. Note 16: ε in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum duration for the master to pull the line low is t W1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. Note 17: δ in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is t RLMAX + tF. Note 18: Current drawn from IO during the EEPROM programming interval, during which the voltage at IO must not drop below 1.8V. This condition is met with R PUPMAX over the entire VPUP range. Note 19: The tPROG interval begins immediately after the trailing rising edge on IO for the last time slot of the Release byte for a valid Write Memory sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from I PROG to IL. Note 20: Write-cycle endurance is tested in compliance with JESD47G. Note 21: Not 100% production tested; guaranteed by reliability monitor sampling. Note 22: Data retention is tested in compliance with JESD47G. Note 23: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. Note 24: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem - peratures is not recommended.

Figure 1. Block Diagram Figure 2. Hierarchical Structure for 1-Wire Protocol Figure 3. 64-Bit ROM ID Redundancy Checks with Maxim iButton® Products . CRC returns the shift register to all 0s.

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Table 1. Memory Resources Table 2. Address to Segment Mapping restrictions, such as write protection or read protection. shows how the segments relate to a memory address. factory to set up and register a custom manufacturer ID. Figure 4. 1-Wire CRC Generator Legend: (5Fh) → designates memory location 5Fh. Text without brackets refers to the register name.

Figure 5. User Memory Map Function Commands section for command flow details. memory is written in segments of 2 bytes. C3A9h: addresses 0074h to 0075h are user bytes. *ONCE A NIBBLE IS PROGRAMMED TO ANYTHING OTHER THAN 0h, THE NIBBLE CANNOT BE CHANGED.

Figure 6. Memory Functions Flowchart

2 DATA BYTES AND VERIFIES

*1-Wire IDLE HIGH FOR POWER.

segments within a page. To safeguard against transmission errors, the DS28E05 supports read-after-write verification. new data provided with the command. page numbers are 000b (page 0) to 111b (page 7). memory page). Valid segment numbers for page 7 are 000b, 001b, and 010b. Table 3. Parameter Byte Bitmap Note: The bits marked as 0 must be transmitted as 0 for the parameter byte to be valid. Parameter Byte Target page selection, starting segment number (Table 3). Restrictions The memory page must not be write protected. Protocol Variations Writing within a page. Writing through the end of the page. Error conditions Invalid parameter byte. The memory page is write protected. 33h = The command failed because the page is write protected.

0 PAGE # SEG # 0

is FFh. The master can end the Read Memory command at any time by issuing a reset pulse. Table 4. Parameter Byte Bitmap Note: The bit marked as 0 must be transmitted as 0 for the parameter byte to be valid. Figure 7. Hardware Configuration Parameter Byte Starting memory address (Table 4). Restrictions None. This command can be issued at any time. Error conditions Invalid parameter byte.

0 TA1

www.maximintegrated.com Maxim Integrated │ 11 A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS28E05 supports overdrive speed of 76.9kbps (max) only and cannot be used together with standard speed or dual-speed 1-Wire slaves on the bus. The value of the pullup resistor primarily depends on the 1-Wire pullup voltage, network size and load conditions. The DS28E05 requires a pullup resistor of maximum 1.5kΩ. The idle state for the 1-Wire bus is high. If for any reason a transaction must be suspended, the bus must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs, one or more devices on the bus could be reset. Transaction Sequence The protocol for accessing the DS28E05 through the 1-Wire port is as follows:

• Initialization
• ROM Function Command
• Memory Function Command
• Transaction Data Initialization All transactions on the 1-Wire bus begin with an initializa- tion sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The pres - ence pulse lets the bus master know that the DS28E05 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. 1-Wire ROM Function Commands Once the bus master has detected a presence, it can issue one of the five ROM function commands that the DS28E05 supports. All ROM function commands are 8 bits long. A list of these commands follows (see the flow- chart in Figure 8). Read ROM [33h] The Read ROM command allows the bus master to read the DS28E05’s ROM ID (8-bit family code, unique 48-bit serial number, and 8-bit CRC). This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The family code and 48-bit serial number as read by the master are unlikely to match the CRC. Match ROM [55h] The Match ROM command, followed by a 64-bit ROM ID, allows the bus master to address a specific DS28E05 on a multidrop bus. Only the DS28E05 that exactly matches the 64-bit ROM ID responds to the following memory function command. All other slaves wait for a reset pulse. This command can be used with a single or multiple devices on the bus. Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their ROM ID numbers. By taking advantage of the wired-AND property of the bus, the master can use a pro- cess of elimination to identify the ID of all slave devices. For each bit of the ID number, starting with the least sig- nificant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its ID number bit. On the second slot, each slave device participating in the search outputs the complemented value of its ID number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choos- ing which state to write, the bus master branches in the search tree. After one complete pass, the bus master knows the ROM ID number of a single device. Additional passes identify the ID numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. Skip ROM [CCh] This command can save time in a single-drop bus sys - tem by allowing the bus master to access the memory functions without providing the 64-bit ROM ID. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM com - mand, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result).

Figure 8. ROM Functions Flowchart

Figure 10. Read/Write Timing Diagrams

which the master must perform a read from the data line. but does not go below VTL, it is not recognized (Figure 11). legend and data direction codes. Figure 11. Noise Suppression Scheme Table 5. 1-Wire Communication Legend Table 6. Data Direction Codes

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Package Information

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Ordering Information

1-Wire Communication Examples (continued) +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *Future product—contact factory for availability. PART TEMP RANGE PIN-PACKAGE DS28E05R+T* -40ºC to +85ºC 3 SOT23 (3k pcs) DS28E05P+ -40ºC to +85ºC 6 TSOC DS28E05P+T -40ºC to +85ºC 6 TSOC (4k pcs) PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

3 SOT23 U3+2 21-0051 90-0179

6 TSOC D6+1 21-0382 90-0321

Writing within a page, not reaching the end of the page. PD Select DataData DataData FFh FFh 00h DataData Release Repeat CS = AAh RST RST RM Read Memory Starting at address 33h, reading 6 bytes PD Select RST FF Loop FF Loop FF Loop Wait tPROGRST WM PB Writing through the end of the page. PD Select Release Repeat CS = AAh Wait tPROGRST WM PB Writing fails with protection error PD Select Release CS = 33h RST WM Invalid parameter byte PD Select PB = 7Eh FF LoopRST RM Invalid parameter byte PD Select PB = 80h RST<6 bytes> 00h 00h <10 bytes>RST RM Starting at the manufacturer ID, reading beyond the end of memory PD Select PB = 76h PB = 33h

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. DS28E05 1-Wire EEPROM © 2012 Maxim Integrated Products, Inc. │ 17

Revision History

0 12/12 Initial release — For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.