DS28DG02 MAXIM | Alldatasheet

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Technical content

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS28DG02 combines 2Kb (256 x 8) EEPROM with 12 PIO lines, a real-time clock (RTC) and calendar with alarm function, a CPU reset monitor, a battery monitor, and a watchdog. Communication with the device is accomplished with an industry- standard SPI™ interface. The user EEPROM is organized as four blocks of 64 bytes each with single-byte and up to 16-byte page write capability. Additional registers provi de access to PIOs and to setup functions. Individual PIO lines can be configured as inputs or ou tputs. The power-on state of PIOs programmed as outputs is stored in nonvolatile (NV) memory. All PIOs may be reconfigured by the user through the serial interface. The RTC/calendar operates in the 12/24-hour format and automatically corrects for leap years. Battery monitor threshold and watchdog timeout are user- programmable through NV registers. The reset monitor generates a reset to the CPU if the voltage at the V CC pin falls below the factory-set limit. The reset output includes a debounce circuit for manual pushbutton reset.

APPLICATIONS

Broadband Access Network Equipment Patient-Monitoring Systems Home Lighting Control Systems Holter Heart Monitors Typical Operating Circuit appears on page 32. Pin Configuration appears on page 33.

FEATURES

 2Kb (256 x 8) EEPROM Organized in Four 64-Byte Blocks  Single Byte and Up to 16-Byte EEPROM Write Sequences  EEPROM Write-Protect Control Pin Protects 1, 2, or All 4 Blocks  Endurance 200k Cycles per Page at +25°C; 10ms (max) EEPROM Write Cycle  SPI Serial Interface Supporting Modes (0,0) and (1,1) at Up to 2MHz Clock Frequency  12 PIO Lines with LED Drive Capability  Each PIO is Configured to Input or Output, Open-Drain/Push-Pull on Startup by Stored Value  All PIOs are Reconfigurable After Startup  RTC/Calendar/Alarm with BCD Format and Leap-Year Compensation  RTC Controlled Through 32.768kHz, 12.5pF Crystal or External TCXO  CPU Reset Through Fast-Response Precision V CC Monitor with Hysteresis or Pushbutton  Battery Monitor 2.5V, 2.25V, 2.0V, 1.75V, -5%  Watchdog Timer 1.6s, 0.8s, 0.4s, 0.2s (typ)  Unique Factory-Programmed 64-Bit Device Registration Number  Operating Range: 2.2V to 5.25V, -40°C to +85°C  ±4kV IEC 1000-4-2 ESD Protection Level (Except Crystal Pins)  Available in 28-Lead, 4.4mm TSSOP or 36-Lead 6mm × 6mm QFN Package

ORDERING INFORMATION

PART TEMP RANGE V CC TRIP PIN-PACKAGE PKG CODE DS28DG02E-3C+ -40°C to +85°C 3.3V -5% 28 TSSOP-EP * (4.4mm) U28E+5 DS28DG02E-3C+T -40°C to +85°C 3.3V -5% 28 TSSOP-EP * T&R U28E+5 DS28DG02G-3C+ -40°C to +85°C 3.3V -5% 36 TQFN-EP * (6mm × 6mm) T3666+3 DS28DG02G-3C+T -40°C to +85°C 3.3V -5% 36 TQFN-EP * T&R T3666+3 *EP = Exposed Paddle. +Denotes lead-free/RoHS compliant device. For additional VCC monitor trip points or other device options, contact the factory. Note: Registers are capitalized for clarity. SPI is a trademark of Motorola, Inc. DS28DG02 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog www.maxim-ic.com EV KIT AVAILABLE

DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog 2 of 34 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground -0.5V, +6V Maximum Current SO, ALMZ, RSTZ, WDOZ Pins 20mA Maximum Current Each PIO Pin 50mA Maximum GND and VCC Current 270mA Operating Temperature Range -40°C to +85°C Junction Temperature +150°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/JEDEC J-STD-020 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.

ELECTRICAL CHARACTERISTICS

(TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Battery monitor off 2.2 5.25 Supply Voltage V CC Battery monitor enabled 2.7 5.25 V Battery Voltage V BAT (Note 1) 1.5 3.0 V CC V RTC oscillator off 2 RTC oscillator on 0.4 10 Battery Current (VBAT = 3.0V, Note 1) IBAT RTC oscillator on, +25°C 4.7 µA Standby Current (Note 2) I CCS SPI idle, ALMZ, WDOZ, RTSZ high, VCC = 5.25V, RTC oscillator on, all PIOs grounded 60 100 µA Operating Current I CCA Reading EEPROM at 2 Mbps, ALMZ, WDOZ, RTSZ high, VCC = 5.25V, RTC oscillator on, all PIOs grounded 550 800 µA Programming Current I PROG V CC = 5.25V 600 1000 µA VCC Monitor Trip Point V TRIP (Note 3) 2.97 3.05 3.14 V +25°C -1.5 +1.5 VCC Monitor Trip-Point Tolerance VTRIPTOL -40°C to +85°C -2.5 +2.5 %VTRIP VCC Monitor Hysteresis V HYST 0.4 0.5 0.6 %V TRIP Power-Up Wait Time t POIP 60 µs EEPROM Programming Time t PROG 10 ms Endurance N CYCLE At +25°C (Notes 4, 5) 200k — Data Retention t RET At +85°C (Notes 5, 6) 40 years REAL-TIME CLOCK Frequency Deviation F (Notes 5, 7) -46 +46 PPM PIO PINS (See Figures 21, 22, 23) VCC = 2.2V 6 9.5 VCC = 3.3V 12.5 22.0 LOW-Level Output Current at VOL = 0.5V (Note 8) IOL VCC = 5.25V 19 30 mA VOH = 2.4V, VCC = 3.3V 6.5 11.0 HIGH-Level Output Current (Note 8) IOH VOH = 4.5V, VCC = 5.25V 12.5 18.0 mA

DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog 3 of 34 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOW-Level Input Voltage V IL 0.8 V HIGH-Level Input Voltage V IH 0.7 × VCC VCC + 0.5V V Low-current mode (Note 9) 1 Output Transition Time t OT High-current mode (Note 10) 25 µs Power-On Setting Time tPOS High-current mode (Note 11) 25 µs PIO Read Setup Time t PS (Note 5) 100 ns PIO Read Hold Time t PH (Note 5) 100 ns Leakage Current I L High impedance, at VCCMAX -1 +1 µA RSTZ PIN (Note 12) (See Figures 6, 7) LOW-Level Output Voltage V OL At 4mA sink current 0.3 V LOW-Level Input Voltage V IL 0.3 × VCC V Input Leakage Current I L -1 +1 µA Minimum VCC for Valid RSTZ V POR (Notes 5, 13) 2.13 V RSTZ Pulse Duration t RST 176 328 532 ms Manual Reset Pulse Width t MPW 1 µs Manual Reset Release Threshold VTRMS (Note 14) V IL V Manual Reset Debounce Time t DEB t RST ms RSTZ Delay t DEL VCC falling below VTRIP (Note 15) 90 µs ALMZ, WDOZ PINS LOW-Level Output Voltage V OL At 4mA sink current 0.3 V WDI PIN LOW-Level Input Voltage V IL 0.3 × VCC V HIGH-Level Input Voltage V IH 0.7 × VCC VCC + 0.5V V Input Leakage Current I L -1 +1 µA Minimum Input Pulse Width t MPW 1 µs Watchdog Timeout t WD User programmable 0.88 0.44 0.22 0.11 1.64 0.82 0.41 0.20 2.66 1.33 0.67 0.33 s WPZ, SI, SCK, CSZ PINS LOW-Level Input Voltage V IL 0.3 × VCC V HIGH-Level Input Voltage V IH 0.7 × VCC VCC + 0.5V V Input Leakage Current I L -1 +1 µA SO PIN LOW-Level Output Voltage V OL At 1mA sink current and VCCmin 0.2 V HIGH-Level Output Voltage V OH At 1mA source current 0.7 × VCC V Output Leakage Current I L High impedance, at VCCmax -1 +1 µA

DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog 4 of 34 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BATTERY MONITOR (See Figure 8) VBAT Trip Point V BTP Measured with VBAT falling; trip point is user programmable 2.25 2.03 1.80 1.58 2.31 2.08 1.85 1.62 2.38 2.14 1.90 1.66 V +25°C -1.5 +1.5 VBAT Monitor Trip-Point Tolerance VTRIPTOL -40°C to +85°C -2.5 +2.5 %VBTP Battery Test Load Current I LOAD 7.5 20 µA Battery Test Duration t BTPW Load applied to battery (Notes 5, 16) 2 s SPI INTERFACE TIMING (See Figures 9, 10) CSZ Setup Time t CSS (Note 5) 0.4 µs CSZ Hold Time t CSH (Note 5) 0.4 µs Normal communication 0.25 CSZ Standby Pulse Width (Note 5) tCPH (Note 17) 2.0 µs CSZ to High-Z at SO t CHZ 0.25 µs SCK Clock Frequency f CLK 2 MHz Data Setup Time t DS (Note 5) 50 ns Data Hold Time t DH (Note 5) 50 ns SCK Rise Time t SCKR (Note 5) 1 µs SCK Fall Time t SCKF (Note 5) 1 µs Output Valid time t V (Note 5) 0 120 ns Note 1: If no battery is used, connect the VBAT pin to VCC. The RTC is powered by VBAT if VCC falls below VCCmin. Note 2: To the first order, this current is independent of the supply voltage value. Note 3: Nominal values: 3.3V -5%, set at factory. Measured with VCC falling; for VCC rising, the actual threshold is VTRIP + VHYST. Note 4: This specification is valid for each 16-byte memory page. Note 5: Not production tested. Either guaranteed by design (GBD) or guaranteed by a reliability study (EEPROM lifetime parameters). Note 6: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-time storage at elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C. Note 7: Valid with 32KHz crystal, 12.5pF, ESR  45k, +25°C. Note 8: Total PIO sink and source currents through all PIO pins must be externally limited to less than the absolute maximum rating of 270mA minus 1.5mA for EEPROM programming and SPI communication. Exceeding the absolute maximum rating can cause damage. Note 9: Assumes the configuration of the system and the part is such that changing GOV<i> (0 ≤ i ≤ 11) between ‘b1 and ‘b0 switches between sourcing no current and sinking the absolute maximum current at the PIO<i> pin. The limit refers to the switching time between sinking 20% of the DC current and 80% of the DC current. The same is true for changing between 'b0 and 'b1 causing the part to switch from sinking no current to sourcing the absolute maximum current at the PIO<i> pin. Note 10: Each output pin transitions in 1µs with a pause of 1µs before the next pin transitions. Note 11: All PIO are tri-stated at beginning of reset prior to setting to power-on values. Note 12: If the part has battery power (normal case) the active pulldown of RSTZ is supported by the battery. Note 13: If VBAT is tied to VCC (no battery supply) the state of the RSTZ pulldown transistor is not guaranteed when VCC falls below VPOR. Note 14: Threshold refers to the manual reset function obtained by forcing RSTZ low. Note 15: Transient response to a step on VCC from above VTRIP down to (VTRIP - 1mV). Glitches on VCC that are shorter than tDELmin are guaranteed to be suppressed, regardless of their amplitude. Glitches on VCC that are longer than tDELmax are guaranteed not to be suppressed. This parameter is tested at high VCC and guaranteed by design at low. Note 16: If enabled, this test takes place every hour on the hour. The battery voltage is compared to VBTP during the second half of the tBTPW window. The timing is controlled by the RTC. Note 17: Extended duration applies to the following cases: 1) Aborted WREN, WRDI, RDSR, and WRSR command. 2) WRITE command aborted before transmitting the firs t complete data byte after command and address. 3) READ command aborted before reading the firs t complete data byte after command and address. 4) Read aborted before the end of a byte.

Control/Setup Register description for more information. Register description at address 134h for more information. description for more information. Register description for more information. VBAT 28 31 Backup Battery Supply for RTC and RSTZ support. operation. See Application Note 3273 for additional information. Figure 1. The SPI interface aut omatically adjusts to SPI modes (0,0) and (1,1). The V CC trip point, which controls week or once a month at a user-defined time. RTC, watchdog, and battery alarm can be individually enabled.

Figure 1. Block Diagram and 3 only, or block 3 only and for all writeable registers from address 120h and higher.

Figure 2. Memory Map 000h to 03Fh EEPROM R/W User memory block 0. 040h to 07Fh EEPROM R/W User memory block 1. 080h to 0BFh EEPROM R/W User memory block 2. 0C0h to 0FFh EEPROM R/W User memory block 3. 100h to 109h — — Reserved, contents undefined. 10Ah EEPROM R/W Power-on default for PI O output state (PIO0 to PIO7). 10Bh EEPROM R/W Power-on default for PI O output state (PIO8 to PIO11). 10Ch EEPROM R/W Power-on default for PIO direction (PIO0 to PIO7). 10Dh EEPROM R/W Power-on default for PIO direction (PIO8 to PIO11). 10Eh EEPROM R/W Power-on default for PI O read-inversion (PIO0 to PIO7). output mode (same mode for all PIOs). 110h to 117h — — Reserved, contents is undefined. 118h to 11Fh ROM R 64-bit unique registration number. 120h SRAM R/W PIO output st ate (PIO0 to PIO7). 121h SRAM R/W PIO output state (PIO8 to PIO11). 122h SRAM R/W PIO direction (PIO0 to PIO7). 123h SRAM R/W PIO direction (PIO8 to PIO11). 124h SRAM R/W PIO read-inversion (PIO0 to PIO7). 126h — R PIO read access (PIO0 to PIO7). 127h — R PIO read access (PIO8 to PIO11). 128h — — Reserved, contents undefined. 129h to 12Fh NV SRAM R/W RTC and calendar. 130h to 133h NV SRAM R/W RTC alarm. 134h NV SRAM R/W Multifunction control/setup register. 135h NV SRAM R/Clear Alarm and status register. 136h and above — — Reserved, contents undefined.

DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog 8 of 34 DETAILED REGISTER DESCRIPTIONS Power-On Default for PIO Output State ADDR b7 b6 b5 b4 b3 b2 b1 b0 10Ah POV7 POV6 POV5 POV4 POV3 POV2 POV1 POV0 10Bh X X X X POV11 POV10 POV9 POV8 There is general read and write access to these addresses. Factory default: 10Ah: FFh; 10Bh: 0Fh. The contents of this register are automatically transferred to address 120h/121h when the device powers up. BIT DESCRIPTION BIT(S) DEFINITION POVn: PIO Power-On Default State — Power-on default output state of PIO0 to PIO11. POV0 applies to PIO0, etc. X: (Not Assigned) — Reserved for future use. Power-On Default for PIO Direction ADDR b7 b6 b5 b4 b3 b2 b1 b0 10Ch POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 10Dh X X X X POD11 POD10 POD9 POD8 There is general read and write access to these address es. Factory default: 10Ch: FFh; 10Dh: 0Fh. The contents of this register are automatically transferred to address 122h/123h when the device powers up. BIT DESCRIPTION BIT(S) DEFINITION PODn: PIO Power-On Default Direction — Power-on default direction of PIO0 to PIO11. POD0 applies to PIO0, etc. Legend: 0  output; 1  input X: (Not Assigned) — Reserved for future use. Power-On Default for PIO Read Inversion (PIO0 to PIO7) ADDR b7 b6 b5 b4 b3 b2 b1 b0 10Eh PIM7 PIM6 PIM5 PIM4 PIM3 PIM2 PIM1 PIM0 There is general read and write access to this address. Factory default: 00h. The cont ents of this register are automatically transferred to address 124h when the device powers up. BIT DESCRIPTION BIT(S) DEFINITION PIMn: PIO Power-On Default Read-Inversion — Power-on default state of the read-inversion bit of PIO0 to PIO7. PIM0 applies to PIO0, etc. Legend: 0  no inversion; 1  inversion

automatically transferred to address 125h when the device powers up. Figure 3. 64-Bit Registration Number from address 10Ah/10Bh when the device powers up. OVn: PIO Output State — Output state of PIO0 to PIO11. OV0 applies to PIO0, etc. X: (Not Assigned) — Reserved for future use.

DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog 10 of 34 PIO Direction ADDR b7 b6 b5 b4 b3 b2 b1 b0 122h DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 123h X X X X DIR11 DIR10 DIR9 DIR8 There is general read and write access to these addres ses. These registers are automatically loaded with data from address 10Ch/10Dh when the device powers up. BIT DESCRIPTION BIT(S) DEFINITION DIRn: PIO Direction — Direction of PIO0 to PIO11. DIR0 applies to PIO0, etc. Legend: 0  output; 1  input X: (Not Assigned) — Reserved for future use. PIO Read Inversion (PIO0 to PIO7) ADDR b7 b6 b5 b4 b3 b2 b1 b0 124h IMSK7 IMSK6 IMSK5 IMSK4 IMSK3 IMSK2 IMSK1 IMSK0 There is general read and write access to this address. This register is automatically loaded with data from address 10Eh when the device powers up. BIT DESCRIPTION BIT(S) DEFINITION IMSKn: PIO Read- Inversion — Read-inversion bit of PIO0 to PIO7. IMSK0 applies to PIO0, etc. Legend: 0  no inversion; 1  inversion PIO Read Inversion (PIO8 to PIO11), PIO Output Type and Output Mode ADDR b7 b6 b5 b4 b3 b2 b1 b0 125h OTM OT3 OT2 OT1 IMSK11 IMSK10 IMSK9 IMSK8 There is general read and write access to this address. This register is automatically loaded with data from address 10Fh when the device powers up. BIT DESCRIPTION BIT(S) DEFINITION IMSKn: PIO Read- Inversion b0 to b3 Read-inversion bit of PIO8 to PIO11. PIM8 applies to PIO8, etc. Legend: 0  no inversion; 1  inversion OT1: Output Type b4 Output type of PIO0 to PIO3; Legend: 0  push-pull; 1  open drain OT2: Output Type b5 Output type of PIO4 to PIO7; Legend: 0  push-pull; 1  open drain OT3: Output Type b6 Output type of PIO8 to PIO11; Legend: 0  push-pull; 1  open drain OTM: Output Mode b7 Output mode of PIO0 to PIO11; Legend: 0  low-current, simultaneous switching; 1  high-current, sequential switching

DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog 12 of 34 RTC and Calendar Registers ADDR b7 b6 b5 b4 b3 b2 b1 b0 129h 0 10 Seconds Single Seconds 12Ah 0 10 Minutes Single Minutes 10hrs 12Bh 0 12/24 A/P 10hrs Single Hours 12Ch 0 0 0 0 0 Day of Week 12Dh 0 0 10 Date Single Date 12Eh 0 0 0 Single Months 12Fh 10 Years Single Years There is general read and write access to these addresses. Bits shown as 0 cannot be written to 1. The RTC and calendar registers are reset to 00h when the battery voltage ramps up. Writes take effect immediately. To prevent unexpected increments during write access, first update the seconds; this crea tes a 1s window to finish updating the RTC/Calendar registers without any carryover from the Seconds register. Whenever the DS28DG02 receives a SPI Read command, the RTC and Calendar registers are copied to a buffer. When during a read access the address counter points to the RTC/Calendar registers, data from the buffer is transmitted. To obtain most accurate RTC data, start reading at the Seconds register. The number representation of the RTC/ Calendar registers is BCD (binary-coded decimal). The RTC can run in the 12-hour AM/PM and the 24-hour mode. The “12/24” bit (b it 6 of address 12Bh) defin es the mode. For 12-hour AM/PM mode, set this bit to 1; bit 5 of address 12Bh then indicates AM (0b) or PM (1b). In the 24-hour mode, bit 5 and bit 4 together indicate the multiple of 10 hours. The Day of Week register counts from 1 to 7. The calendar logic is designed to automatically compensate for leap years. For every year value that is either 00 or a multiple of 4 the device will add a 29th of February. This will work correctly up to (but not including) the year 2100. RTC Alarm Registers ADDR b7 b6 b5 b4 b3 b2 b1 b0 130h AM1 10 Seconds Single Seconds 131h AM2 10 Minutes Single Minutes 10hrs 132h AM3 12/24 A/P 10hrs Single Hours 0 0 0 Day of Week 133h AM4 DY/DT

10 Date Single Date

There is general read and write access to these addresses. Bits shown as 0 cannot be written to 1. The RTC Alarm registers are reset to 00h when the battery voltage ra mps up. To generate an alarm, there must be a match between Alarm registers and RTC regi sters. Alarm register addresses 130h to 132h correspond to RTC register addresses 129h to 12Bh; bits 6:0 participate in the comp arison. The lower 6 bits of register address 133h correspond to 12Ch if DY/DT is 1 and to 12Dh if DY/DT is 0; the upper 2 bits of this register do not participate in the comparison. The control bits AM1, AM2, AM3, and AM4 deter mine the frequency of the alarm, as shown in Table 1. When the alarm occurs, the CLKA bit of the Alarm and St atus register at address 135h changes to 1. The RTC must be running for the device to generate RTC alarms (OSCE at address 134h = 1).

Table 1. Alarm Frequency Control bits in the generation of the ALMZ, RSTZ, and WDOZ signals. Enable b0 Enable/disable control of the RTC/Calendar alarm. Enable/disable control of the watchdog and its alarm. (Power-on reset) or applying a positive pulse at the WDI pin. Output Selection b3 Pin selection for watchdog alarm signaling. Selection of the nominal Battery Monitor Trip Point voltage. Enable/disable control of the Battery Monitor and its alarm. = 1) for the battery monitor to function. use of the CLKA, WDA, and BATA bits in the generation of the ALMZ, RSTZ, and WDOZ signals.

cleared by writing to the Alarm and Status register. above VBATmin; cleared by writing to the Alarm and Status register. above VCCmin; cleared by writing to the Alarm and Status register. CC ramp up: WPZ pin state; VBAT attach: not affected. by writing to the Alarm and Status register. Figure 5. ALMZ, WDOZ, and RSTZ Generation BME, CAE, WDE, WDOS are defined in the Control/Setup register. BATA, CLKA, WDA are alarm signals readable through the Alarm/Status register.

immediately after VCC ramps up above VPOR. Figure 8 shows the details. Figure 8. Battery Monitor Operation

DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog 17 of 34 SPI INTERFACE The DS28DG02 is a slave device that communicates with its master, a microcontroller, through the serial SPI interface. This interface uses the signals CSZ (chip select), SCK (bit transfer clock), SI (serial input), and SO (serial output). Common to SPI devices is a WPZ input (write prot ect), which can protect the nonvolatile bits in the SPI Status register from inadvertent changes. Pin Description Chip Select (CSZ) A low level on the CSZ pin selects the device; a high leve l deselects the device. A low-to-high transition on CSZ after a valid EEPROM write sequence initiates an internal programming cycle. A programming cycle already initiated or in progress will be completed, regardless of the CSZ input signal. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. After powerup, a low level on CSZ is required prior to any sequence being initiated. The CSZ pin must remain low while the DS28DG02 is receiving or transmitting data. Serial Clock (SCK) The SCK is used to synchronize the communication between a master and the DS28DG02. Instructions, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on the rising edge of the serial clock. Serial Output (SO) The SO pin is used to transfer data out of the DS28DG02. Du ring a read cycle, data is shifted out on this pin after the falling edge of the serial clock. Write Protect (WPZ) The WPZ pin, if enabled, prevents writes to the nonvolatile bits in the SPI Status register. As factory default, the WPZ pin function is disabled. This allows the user to install the DS28DG02 in a system with WPZ pin grounded and still being able to write to the Status register. For more details see Principles of Operation. SPI Modes and Bit Timing The SPI protocol defines communication in full bytes with the MS bit being transmitted first. Every SPI communication sequence begins with at least one byte wri tten to the slave device. The first byte that the slave receives from the master is understood as an instruct ion. Depending on the instruction the slave may need more bytes, e.g., address and data; for a read function, after having received the instruction and address, the slave starts sending data to the master. The SPI protocol knows four communication modes, which differ in the polarity and phase of the SCK signal. The DS28DG02 supports modes (0,0) and mode (1,1). These m odes have in common that data is clocked into the slave on the rising edge and clocked out to the master on the falling edge of SCK. The master then clocks in the data on the rising edge of SCK. The DS28DG02 detects the mode from the logic state of SCK when CSZ gets active (high to low transition). Therefore, SCK must be stable for the duration of a setup and hold time around the falling edge of CSZ. Figures 9 and 10 show the timing details. The read timing of these graphics begins with the first bi t that the DS28DG02 transmits to the master and ends when the master ends the communication by deactivating CSZ (low to high transition). The dotted line indicates the transition between read and write, with the last bit of the command or address being clocked in on the rising edge and the first bit of read data appearing at SO after the falling edge of SCK.

the instruction code, marked as "X". Figure 11. SPI Instruction Set Tx SPI Status Byte To update the SPI Status register. end of an EEPROM write cycle. is accepted. The WEN bit is automatically cleared after successful execution of a write instruction. bit WPEN in conjunction with the logic state at the WPZ pin.  Write-Protect bits for memory blocks and the registers from address 120h and higher. register bit functions is found in Figure 12. Table 2. Write Protection Summary 0 x x Write-protected (because WEN = 0). Write-protected (because WEN = 0). 1 0 x Writeable (because WPEN = 0). AND the WPZ pin is at logic 0).

Figure 12. SPI Status Register Only Bit) b0 Indicates whether an EEPROM write cycle is in progress. completion of a valid WRITE or a valid WRSR instruction. protected (independent of WPEN and WPZ). is enabled (WDE at address 134h = 1). These are nominal values; for tolerances see Electrical Characteristics. higher are write-protected (independent of WPEN and WPZ). writeable or whether the WPZ pin state controls the write-protection. protected and a WRSR instruction is not valid. timing diagram for both SPI communication modes. access instruction. Figure 14 shows the instruction’s timing diagram for both SPI communication modes.

Figure 15. Write SPI Status Register Timing pulses, without having to resend the instruction code. The RDSR instruction ends with the positive edge on CSZ.

Figure 16. Read SPI Status Register Timing

into the device (highlighted SCK transition) and ends after the power-up wait time (tPOIP) is over. Figure 17. Refresh PIO Registers Timing varies. Table 3 shows the cases that need to be distinguished. Table 3. Write Access Cases 000h to 0FFh User memory (can be write-protected through BP1:BP0). 100h to 10Fh EEPROM registers (reserved and powe r-on default values, no write-protection). 110h to 11Fh Read-only memory. 120h to 135h SRAM, PIO, and NV SRAM (m ay be write-protected through RPROT). 136h to 1FFh Nonexisting memory. (pre-loaded) with data from the addressed 16-byte EEPROM segment. Inco ming data replaces pre-loaded data.

DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog 25 of 34 is 1 AND the number if bits sent by the master is a multiple of 8 (i.e., full by te only), the write cycle (transfer from the buffer to EEPROM) begins with the positive edge of CSZ. The duration of the write cycle is t PROG, during which the RDYZ bit of the SPI Status register reads 1. After the write cycle is comp leted, the WEN bit is cleared. If the target memory is write-protected OR WEN was not set to 1 before issuing the WRITE instruction OR the number of data bits that followed the address byte was not a multip le of 8, the positive edge on CSZ does not start a write cycle and the WEN bit is not cleared. The six EEPROM registers, together with the reserved addresses, form another memory segment. Write access to this segment is essentially the same as for the user me mory with the following differences: The data sent by the master that normally would apply to the first 10 bytes of t he segment is discarded. A write cycle is initiated only if the WEN bit of the SPI Status register is 1 AND the number if bits sent by the master is a multiple of 8 (i.e., full byte only) AND at least one EEPROM byte is to be updated. If WEN was not set to 1 before issuing the WRITE instruction OR the number of data bits that followed the address byte was not a multiple of 8 OR all data bytes sent by the master applied to the nonwriteable addresses, the positive edge on CSZ does not start a write cycle and the WEN bit is not cleared. Write access to the SRAM, PIO, and NV SRAM does not in volve a write buffer. If the WEN bit is 1 AND RPROT = 0 AND the target address is writeable, a data byte that fo llows the target address becomes effective as soon as its transmission is completed. The address pointer increments after each data byte, directing subsequent bytes to the next higher addresses. If the target addr ess is read-only, data for that address is discarded. After address 135h is updated, the address pointer wraps around to 120h. The master may continue sending data bytes indefinitely. The write access ends with the positive edge on CSZ. The last byte, if incomplete, is ignored. The WEN bit is cleared only if at least one byte was written to a writeable addr ess. If RPROT = 1 the memory is not updated and the WEN bit remains set. The RTC should be updated starting with the Seco nds register. If the starting target address specified after the instruction code poi nts to the PIO Output State register s (address 120h or 121h) and the PIO output mode OTM is 0 (low current) the address pointer toggles between 120h and 121h after the data byte is transmitted. This allows fast PIO updates, e.g., for generating data patterns. For OTM = 1 (high-current) the address pointer increments to the next higher address . For a PIO-update timing diagram and the differences between low-current and high-current mode, see the PIO Read/Write Access section. Upon receiving a write instruction with an address targeting the read-only memory or non-existing memory, all data is discarded and no write cycle or data update takes place. Since the write access is not successful, the WEN bit in the SPI Status register is not cleared. As a precondition for a successful WRITE instruction, the WEN bit in the SPI Status register must be 1. The WEN bit is set through the WREN instruction, which must be completed before the WRITE instruction. The WRITE timing diagram for both SPI communication modes is shown in Figu re 18 (single-byte write) and Figure 19 (multiple-byte write). The programming time t PROG applies only to EEPROM writes. For writes to the SRAM, PIO, and NV SRAM in SPI mode (0,0) the actual transfer to the target memory takes place on the falling SCK edge of the LS-bit of a data byte. In SPI mode (1,1) the actual transfer to the target memory also takes place on the falling SCK edge of the LS- bit of a data byte, except for the last byte, which is transferred on the rising edge of CSZ.

Figure 19. Multiple-Byte Write to Memory and PIO Timing (continued) command such as WRDI after WRSR to ensure reading from the intended address. Figure 20. Read Memory and PIO Timing

8 Falling Edges for Each Data Byte

Note: This edge ends the LS bit (0) of the previous byte and begins the MS bit (7) of the next byte. 1) The first byte delivered by the device is the SPI Status Byte. After that the memory data follows.

Figure 20. Read Memory and PIO Timing (continued) Note: This edge ends the LS bit (0) of the previous byte and begins the MS bit (7) of the next byte. 1) The first byte delivered by the device is the SPI Status Byte. After that the memory data follows. between 126h or 127h after a data byte is transmitted. This allows fast PIO reads, e.g., to monitor several signals. For a PIO-read timing diagram see the PIO Read/Write Access section. increments normally, wrapping around to 000h after having reached 135h. connected to the PIO pins. The output dr ivers of PIOs that are configured as input are tri-stated (high impedance). The PIO output drivers of the DS28DG02 are designed to deliver high curr ents for driving LEDs or similar loads. evaluated. Since writing to PIOs is a write function, the WEN bit must be set before issuing the WRITE instruction. and PIO8:11. This way the fastest rate for a PIO to change its state is fCLK / 16.

Figure 23. PIO Read-Access Timing

DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog 31 of 34 Command-Specific Communication—Color Codes Master-to-Slave Slave-to-Master Programming Communication Examples Set the WEN Bit in the SPI Status Register (Write Enable) SEL WREN DSEL Clear the WEN Bit in the SPI Status Register (Write Disable) SEL WRDI DSEL Write to the SPI Status Register Sequence SEL WREN DSEL SEL WRSR <byte> DSEL Programming Note: It is advisable to execute a WRDI command right after the WRSR sequence is completed to ensure read access to the user memory. Read Status Register (e.g., to Detect the End of a Write Cycle) SEL RDSR <byte> <byte> <byte> DSEL Refresh PIOs with Power-On Defaults SEL RFSH DSEL Write 3 Bytes to User Memory Sequence, Starting Address = 067h SEL WREN DSEL SEL WRITEL <67h> <byte> <byte> <byte> DSEL Programming See Read Status register example to test for the end of the write cycle. Set RTC and Calendar, Starting Address = 129h SEL WREN DSEL SEL WRITEH <29h> <7 bytes RTC data> DSEL SRAM, no programming time. Read User Memory Block 1, Starting Address = 040h, 64 Bytes SEL READL <40h> <64 bytes memory data> DSEL Read all PIOs 3 Times, Starting Address = 126, 6 Bytes SEL READH <26h> <6 bytes PIO data> DSEL Continue reading until RDYZ bit is is 0

Figure 24. Crystal Placement on PCB

DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog 33 of 34 Pin Configurations V BAT CSZ SCK SI SO ALMZ PIO1 PIO5 PIO9 GND PIO11 PIO7 PIO3 V CC RSTZ WDI WDOZ WPZ PIO0 PIO4 PIO8 GND PIO10 PIO6 PIO2 VCC

36 RSTZ

N.C. N.C. VBAT CSZ N.C. SCK N.C. SI SO ALMZ PIO1 PIO5 PIO9 N.C. GND 10 11 12 13 14 15 16 17 18 PIO10 PIO6 PIO2 VCC N.C. VCC PIO3 PIO7 PIO11 N.C. WDI WDOZ WPZ PIO0 PIO4 PIO8 N.C. GND 4.4mm 28-Lead TSSOP (Top View) Thin 36-Lead 6mm × 6mm QFN (Top View)

PACKAGE INFORMATION

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

28 TSSOP — 21-0108

36 TQFN — 21-0141

DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog 34 of 34

REVISION HISTORY

 Text in Unique Registration Number section was rewritten. In compliance with SPI conventions, the registration number is stored with the CRC at 118h and family code at 11Fh (not the opposite sequence, as originally described).  Added address information to Figure 3 (118h over CRC, 119h-11Eh over 48- bit S/N, 11Fh over family code)