DS28C39 AD | Alldatasheet

Document overview

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Technical content

The DS28C39 is an ECDSA public-key-based bidirectional secure authenticator that incorporates Analog Devices’ patented ChipDNA™ feature, a physically unclonable function (PUF) to provide a cost-effective solution with the ultimate protection against security attacks. Using the random variation of semiconductor device characteristics that naturally occur during wafer fabrication, the ChipDNA circuit generates a unique output value that is repeatable over time, temperature, and operating voltage. Attempts to probe or observe ChipDNA operation modifies the underlying circuit characteristics, preventing discovery of the unique value used by the chip cryptographic functions. The DS28C39 utilizes the ChipDNA output as key content to cryptographically secure all device stored data and as the private key for the ECDSA signing operation. With ChipDNA capability, the device provides a core set of cryp- tographic tools derived from integrated blocks including an asymmetric (ECC-P256) hardware engine, a FIPS/NIST- compliant true random number generator (TRNG), 2Kb of secured EEPROM, and a unique 64-bit ROM identification number (ROM ID). The ECC public/ private key capabili- ties operate from the NIST-defined P-256 curve to provide a FIPS 186-compliant ECDSA signature generation func- tion. The unique ROM ID is used as a fundamental input parameter for cryptographic operations and serves as an electronic serial number within the application. Lastly, the DS28C39 supports I 2C communication at the 100kHz standard mode.

Applications

  • Authentication of Medical Sensors and Tools
  • IoT Node Authentication
  • Peripheral Authentication
  • Reference Design License Management
  • Printer Cartridge Identification and Authentication Ordering Information appears at end of data sheet. 19-100700; Rev 1; 8/23 Benefits and Features
  • Robust Countermeasures Protect Against Security Attacks
  • Patented Physically Unclonable Function Secures Device Data
  • Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts
  • All Stored Data Cryptographically Protected from Discovery
  • ECDSA Authenticated R/W of Stored Data
  • Efficient Public-Key Authentication Solution to Authenticate Peripherals
  • FIPS 186-Compliant ECDSA P256 Signature for Challenge/Response Authentication
  • ChipDNA Generated Public/Private Key Pair.
  • TRNG with NIST SP 800-90B Compliant Entropy Source
  • Supplemental Features Enable Easy Integration into End Applications
  • 2Kb of EEPROM for User Data, Key, Control Registers, and Certificate
  • Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
  • I2C Communication: Up to 200kHz
  • Operating Range: 3.3V ±10%, -40°C to +85°C
  • 6-Pin TDFN-EP Package (3mm x 3mm) DeepCover is a registered trademark and ChipDNA is a trademark of Maxim Integrated Products, Inc. Click here to ask an associate for production status of specific part numbers. Request Security User Guide and Developer Software › DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection DS28C39 © 2023 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EVALUATION KIT AVAILABLE

Typical Application Circuit µC DS28C39 VCC SDA GND VCC GND VCC VCC I2C PORT SDA SCL VCC PIOA PIOB IO IORp DS2476 SCL VCC www.analog.com Analog Devices │ 2 DS28C39 DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection

6 TDFN-EP

Land Pattern Number 90-0058 Thermal Resistance, Single-Layer Board: Junction to Ambient (θJA) 55°C/W Junction to Case (θJC) 9°C/W Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 42°C/W Junction to Case (θJC) 9°C/W Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For detailed information on package thermal considerations, refer to https://www.analog.com/en/technical-articles/thermal-char- acterization-of-ic-packages.html. For the latest package outline information and land patterns (footprints), go to https://www.analog.com/en/design-center/packaging- quality-symbols-footprints/package-index.html. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Package Information

www.analog.com Analog Devices │ 3 DS28C39 DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection

(Limits are 100% tested at TA = 25ºC. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum and maximum operating temperature are guaranteed by design and are not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC (Note 1) 2.97 3.3 3.63 V Supply Current ICC Standby 4 mA Communicating/active (Note 2) 10 mA CRYPTO FUNCTIONS Computation Current ICMP (Note 3) 10 mA Generate ECC Key Pair tGKP 200 ms Generate ECDSA Signature tGES 130 ms TRNG On-Demand Check tODC 20 ms EEPROM Read Memory tRM 30 ms Write Memory tWM 65 ms Write State tWS 15 ms Write/Erase Cycles (Endurance) NCY TA = +85°C (Note 4) 100K Data Retention tDR TA = +85°C (Note 5) 10 years I2C SCL AND SDA PINS (Note 6) Low-Level Input Voltage VIL -0.3 0.3 × VCC V High-Level Input Voltage VIH 0.85 × VCC VCC + 0.3V V Hysteresis of Schmitt Trigger Inputs VHYS (Note 2) 0.1 × VCC V Low-Level Output Voltage at 4mA Sink Current VOL (Note 7) 0.4 V Output Fall Time from VIH(MIN) to VIL(MAX) with a Bus Capaci- tance from 10pF to 400pF tOF (Note 2) 180 ns Input Current with an Input Voltage Between 0.1VCCmax and 0.9VCCmax II (Note 2) -1 +1 µA

Electrical Characteristics

www.analog.com Analog Devices │ 4 DS28C39 DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection

Note 1: System requirement. Note 2: Guaranteed by design and/or characterization only. Not production tested. Note 3: Current drawn from VCC during the EEPROM programming interval or Crypto computation. Note 4: Write-cycle endurance is tested in compliance with JESD47G. Note 5: Data retention is tested in compliance with JESD47G. Note 6: All I2C timing values are referred to V IH(MIN) and VIL(MAX) levels. Note 7: The I-V characteristic is linear for voltages less than 1V. Note 8: tLOW min = tHD:DAT max + 200ns for rise or fall time + t SU:DAT min. Values greater than these can be accommodated by extending tLOW accordingly. Note 9: The DS28C39 provides a hold time of at least 100ns for the SDA signal (referenced to the V IH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 10: The DS28C39 can be used in a standard-mode I 2C-bus system, but the requirement t SU:DAT ≥ 250ns must then be met. Also the acknowledge timing must meet this setup time (I 2C bus specification Rev. 03, 19 June 2007). Note 11: CB = Total capacitance of one bus line in pF. The maximum bus capacitance allowable may vary from this value depending on the actual operating voltage and frequency of the application (I 2C bus specification Rev. 03, 19 June 2007). Note 12: I2C communication should not take place for the max t OSCWUP time following a power-on reset. (Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Capacitance CI (Note 2) 10 pF SCL Clock Frequency fSCL (Note 1) 0 200 kHz Hold Time (Repeated) START Condition tHD:STA 1 µs Low Period of the SCL Clock tLOW (Note 8) 1 µs High Period of the SCL Clock tHIGH (Note 2) 3 µs Setup Time for a Repeated START Condition tSU:STA (Note 2) 1 µs Data Hold Time tHD:DAT (Notes 2, 8, 9) 0.55 µs Data Setup Time tSU:DAT (Notes 2, 8, 10) 250 ns Setup Time for STOP Condition tSU:STO (Note 2) 1 µs Bus Free Time Between a STOP and START Condition tBUF (Note 2) 2 µs Capacitive Load for Each Bus Line CB (Notes 1, 11) 400 pF Warm-Up Time tOSCWUP (Note 1, 12) 12 ms Electrical Characteristics (continued) www.analog.com Analog Devices │ 5 DS28C39 DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection

1, 2 N.C. No Connection. The pins are not wire-bonded to the IC pads.

3 GND Ground

4 SCL I2C Serial Clock Input. Must be connected to VCC through a pullup resistor. 5 SDA Open-Drain, I2C Serial Data Input/Output. Must be connected to VCC through a pullup resistor.

6 VCC Power Supply Input

– EP Exposed Pad (TDFN Only). Solder evenly to the board's ground plane for proper operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information. Pin Description Pin Configuration DS28C39 TOP VIEW

6 VCC

5 SDA

4 SCL3GND

2N.C. 1N.C. TDFN-EP 3mm x 3mm www.analog.com Analog Devices │ 6 DS28C39 DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection

protect all device stored data from invasive discovery. ory, ECC key set, control registers, and certificates. circuit elements of the DS28C39. mable options to set protection modes. Figure 1. Block Diagram

PART TEMP RANGE PIN-PACKAGE DS28C39Q+T -40°C to +85°C 6 TDFN (2.5k pcs) +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel.

Ordering Information

www.analog.com Analog Devices │ 10 DS28C39 DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection

0 11/19 Initial release — 1 8/23 Updated General Description, Applications, Benefits and Features, Detailed Description, and Figure 1 1, 7

Revision History

DS28C39 DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection www.analog.com Analog Devices │ 11 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.