DS28C36_V01 MAXIM | Alldatasheet

Document overview

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Technical content

The DS28C36 is a DeepCover ® secure authenticator that provides a core set of cryptographic tools derived from integrated asymmetric (ECC-P256) and symmetric (SHA-256) security functions. In addition to the security services provided by the hardware implemented crypto engines, the device integrates a FIPS/NIST true random number generator (RNG), 8Kb of secured EEPROM, a decrement-only counter, two pins of configurable GPIO, and a unique 64-bit ROM identification number (ROM ID). The ECC public/private key capabilities operate from the NIST defined P-256 curve and include FIPS 186 compliant ECDSA signature generation and verification to support a bidirectional asymmetric key authentication model. The SHA-256 secret-key capabilities are compli - ant with FIPS 180 and are flexibly used either in conjunc - tion with ECDSA operations or independently for multiple HMAC functions. Two GPIO pins can be independently operated under command control and include configurability supporting authenticated and nonauthenticated operation including an ECDSA-based crypto-robust mode to support secure- boot of a host processor. DeepCover embedded security solutions cloak sensitive data under multiple layers of advanced security to provide the most secure key storage possible. To protect against device-level security attacks, invasive and noninvasive countermeasures are implemented including active die shield, encrypted storage of keys, and algorithmic methods.

Applications

  • IoT Node Crypto-Protection
  • Accessory and Peripheral Secure Authentication
  • Secure Storage of Cryptographic Keys for a Host Controller
  • Secure Boot or Download of Firmware and/or System Parameters Benefits and Features
  • ECC-256 Compute Engine
  • FIPS 186 ECDSA P256 Signature and Verification
  • ECDH Key Exchange with Authentication Prevents Man-in-the-Middle Attacks
  • ECDSA Authenticated R/W of Configurable Memory
  • FIPS 180 SHA-256 Compute Engine
  • HMAC
  • SHA-256 OTP (One-Time Pad) Encrypted R/W of Configurable Memory Through ECDH Established Key
  • Two GPIO Pins with Optional Authentication Control
  • Open-Drain, 4mA/0.4V
  • Optional SHA-256 or ECDSA Authenticated On/Off and State Read
  • Optional ECDSA Certificate to Set On/Off after Multiblock Hash for Secure Boot
  • RNG with NIST SP 800-90B Compliant Entropy Source with Function to Read Out
  • Optional Chip Generated Pr/Pu Key Pairs for ECC Operations
  • 17-Bit One-Time Settable, Nonvolatile Decrement- Only Counter with Authenticated Read
  • 8Kbits of EEPROM for User Data, Keys, and Certificates
  • Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
  • Optional Input Data Component to Crypto and Key Operations
  • I2C Communication Up to 1MHz
  • Operating Range: 2.2V to 3.63V, -40°C to +85°C
  • 6-Pin TDFN Package Ordering Information appears at end of data sheet. Typical Application Circuit appears at end of data sheet. 19-8564; Rev 3; 12/20 DeepCover is a registered trademark of Maxim Integrated Products, Inc. Click here for production status of specific part numbers. DS28C36 DeepCover Secure Authenticator EVALUATION KIT AVAILABLE ABRIDGED DATA SHEET

6 TDFN-EP

Land Pattern Number 90-0058 Thermal Resistance, Single-Layer Board: Junction to Ambient (θJA) 55°C/W Junction to Case (θJC) 9°C/W Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 42°C/W Junction to Case (θJC) 9°C/W

Electrical Characteristics

(TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC DS28C36 2.97 3.3 3.63 VDS28C36B 2.2 Active Supply Current ICC (Note 2) 300 µA Standby Supply Current ICCS 250 µA Computation Current ICMP (Note 3) 7.5 mA GPIO Output Low PIOVOL 0.4 V Input Low PIOVIL -0.3 VCC x 0.3 V Input High PIOVIH VCC x 0.7 VCC + 0.3 V Leakage current IL DS28C36 -10 +10 µADS28C36B -1 +1 ECC ENGINE Generate ECDSA Signature Time tGES 50 ms Generate ECC Key Pair tGKP 100 ms Verify ECDSA Signature or Compute ECDH Time tVES 150 ms SHA-256 ENGINE Computation Time (HMAC or RNG) tCMP 3 ms DS28C36 DeepCover Secure Authenticator www.maximintegrated.com Maxim Integrated │ 2 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Package Information

(TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EEPROM W/E Endurance NCY (Note 4) 100K — Read Memory Time tRM 1 ms Write Memory Time tWM 15 ms Data Retention tDR TA = +85°C (Note 5) 10 years I2C SCL AND SDA PINS (Note 6) Low-Level Input Voltage VIL -0.3 0.3 × VCC V High-Level Input Voltage VIH 0.7 × VCC VCC + 0.3 V Hysteresis of Schmitt Trigger Inputs VHYS (Note 7) 0.05 × VCC V Low-Level Output Voltage at 4mA Sink Current VOL 0.4 V Output Fall Time from VIH(MIN) to VIL(MAX) with a Bus Capacitance from 10pF to 400pF tOF (Note 7) 30 ns Pulse Width of Spikes that are Suppressed by the Input Filter tSP (Note 7) 50 ns Input Current with an Input Voltage Between 0.1VCCmax and 0.9VCCmax II DS28C36 -10 +10 µADS28C36B (Note 8) -1 +1 Input Capacitance CI (Note 7) 10 pF SCL Clock Frequency fSCL (Note 9) DS28C36 0 0.4 MHzDS28C36B 0 1 Hold Time (Repeated) START Condition tHD:STA DS28C36 0.6 µsDS28C36B 0.45 Low Period of the SCL Clock tLOW (Note 10) DS28C36 1.3 µsDS28C36B 0.65 High Period of the SCL Clock tHIGH DS28C36 0.6 µsDS28C36B 0.35 Setup Time for a Repeated START Condition tSU:STA DS28C36 0.6 µsDS28C36B 0.35 Data Hold Time tHD:DAT (Notes 7, 10, 11) DS28C36 0.9 µsDS28C36B 0.35 Data Setup Time tSU:DAT (Notes 10, 12) 100 ns Setup Time for STOP Condition tSU:STO DS28C36 0.6 µsDS28C36B 0.35 Bus Free Time Between a STOP and START Condition tBUF DS28C36 1.3 µsDS28C36B 0.6 Capacitive Load for Each Bus Line CB (Notes 9, 13) 400 pF Warm-Up Time tOSCWUP (Note 14) DS28C36 0.25 msDS28C36B 1.0 DS28C36 DeepCover Secure Authenticator www.maximintegrated.com Maxim Integrated │ 3 Electrical Characteristics (continued) ABRIDGED DATA SHEET

(TA = -40°C to +85°C.) (Note 1) Note 1: Limits are 100% production tested at T A = +25°C and/or TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Typical values at +25°C. Note 2: Operating current continuously reading memory at 400kHz with < 25ns rise and fall times on SDA and SCL. Note 3: Average current drawn from VCC during EEPROM read, EEPROM write, RNG calculation, SHA-256 calculation, or ECDSA calculation. Note 4: Write-cycle endurance is tested in compliance with JESD47H. Note 5: Data retention is rested in compliance with JESD47H. Note 6: All I2C timing values are referred to V IH(MIN) and VIL(MAX) levels. Note 7: Guaranteed by design and/or characterization only. Not production tested. Note 8: I/O pins of the DS28C36B do not obstruct the SDA and SCL lines if V CC is switched off. Note 9: System requirement. Note 10: tLOW min = tHD:DAT max + tEDGE max + tSU:DAT min, where tEDGE is rise or fall time. For the DS28C36, tEDGE max = 300ns; for the DS28C36B, tEDGE max = 200ns. Values greater than these can be accommodated by extending tLOW accordingly. Note 11: The DS28C36 provides a hold time of at least 100ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. The master can provide a hold time of 0ns when writing to the device. Note 12: The DS28C36 can be used in a standard-mode I 2C bus system, but the requirement t SU:DAT ≥ 250ns must then be met (I2C bus specification Rev. 03, 19 June 2007). Note 13: CB = total capacitance of one bus line in pF. The maximum bus capacitance allowable can vary from this value depending on the actual operating voltage and frequency of the application (I 2C bus specification Rev. 03, 19 June 2007). Note 14: I2C communication should not take place for max t OSCWUP time following a power-on reset. DS28C36 DeepCover Secure Authenticator www.maximintegrated.com Maxim Integrated │ 4 Electrical Characteristics (continued) ABRIDGED DATA SHEET

1 SCL I2C CLK. Connect to VCC with a pullup resistor. 2 SDA I2C Data. Connect to VCC with a pullup resistor.

3 GND Ground

4 PIOB General-Purpose IO

5 PIOA General-Purpose IO

6 VCC Supply Voltage

— EP Exposed Pad. Solder evenly to the board’s ground plane for proper operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information. SCL SDA GND

6 VCC

5 PIOA

4 PIOB

(3mm x 3mm) TOP VIEW DS28C36 EP* DS28C36 DeepCover Secure Authenticator www.maximintegrated.com Maxim Integrated │ 5 Pin Configuration Pin Description ABRIDGED DATA SHEET

+Denotes a lead(Pb)-free/RoHS-compliant package. T= Tape and reel. *EP = Exposed pad. †Not recommended for new designs. PART TEMP RANGE PIN-PACKAGE DS28C36Q+T† -40°C to +85°C 6 TDFN-EP* (2.5k pcs) DS28C36BQ+T -40°C to +85°C 6 TDFN-EP* (2.5k pcs) µC 3.3V VCC GND I2C PORT SDA SCL RP1 DS28C36 GND VCC PIOA IO PIOB IO RP2 RP3 RP4 DS28C36 DeepCover Secure Authenticator www.maximintegrated.com Maxim Integrated │ 6 Typical Application Circuit

Ordering Information

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. DS28C36 DeepCover Secure Authenticator © 2020 Maxim Integrated Products, Inc. │ 7 REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 6/16 Initial release — 1 10/18 Updated Electrical Characteristics and Notes, Typical Operating Conditions, authenticated SHA2 Write Memory HMAC input tables, and general corrections 1–63 2 1/19 Added indications of GPIO volatility in the Memory Resources section, Table 1, and power-up states in Table 5 7, 10 3 12/20 Updated Package Information 2

Revision History

For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html. ABRIDGED DATA SHEET