DS28C16 AD | Alldatasheet

Document overview

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Technical content

The DS28C16 secure authenticator combines FIPS202-compliant Secure Hash Algorithm (SHA-3) chal- lenge and response authentication with secured EEP - ROM. The device provides a core set of cryptographic tools de- rived from integrated blocks including a SHA-3 engine, 256 bits of secured user EEPROM, a decrement-only counter, and a unique 64-bit ROM identification number (ROM ID). The unique ROM ID is used as a fundamental input parameter for cryptographic operations and serves as an electronic serial number within the application.

Applications

  • Medical Tools/Accessories Authentication and Calibration
  • Accessory and Peripheral Secure Authentication
  • Battery Authentication and Charge Cycle Tracking Request DS28C16 Security User Guide Benefits and Features
  • Robust Countermeasures Protect Against Security Attacks
  • All Stored Data Cryptographically Protected from Discovery
  • Efficient Secure Hash Algorithm to Authenticate Peripherals
  • FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication
  • FIPS 198-Compliant Keyed-Hash Message Authentication Code (HMAC)
  • Supplemental Features Enable Easy Integration into End Applications
  • 17-Bit, One-Time Settable, Nonvolatile Decrement- Only Counter with Authenticated Read
  • Secure Storage for Secrets
  • 256 Bits of Secure EEPROM for User Data
  • Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
  • I2C Communications up to 1MHz
  • Operating Range: 1.62V to 3.63V, -40°C to +85°C
  • 8-Pin, 2mm x 2mm TDFN-EP Package Typical Application Circuit µC VCC VCC GND I2C PORT SDA SCL DS28C16 DS28C16 VCC GND Click here to ask an associate for production status of specific part numbers. DS28C16 I2C Low-Voltage SHA-3 Authenticator Ordering Information appears at end of data sheet. 19-100753; Rev 3; 1/22 © 2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Package Information

8 TDFN-EP

Land Pattern Number 90-0065 Thermal Resistance, Single-Layer Board: Junction to Ambient (θJA) — Junction to Case (θJC) — Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 85.1°C/W Junction to Case (θJC) 20.8°C/W For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics

(Limits are 100% tested at T A = +25ºC and T A = +85ºC. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC (Note 1) 1.62 3.3 3.63 V Supply Current ICC Standby 3.5 12 μA Communicating (Note 2) 60 I2C SCL AND SDA PINS (Note 3) Low-Level Input Voltage VIL -0.3 0.3 × VCC V High-Level Input Voltage VIH VCC > 1.98V 0.7 × VCC VCC + 0.3 V VCC ≤ 1.98V 0.8 × VCC VCC + 0.3 Hysteresis of Schmitt Trigger Inputs VHYS (Note 4) 0.05 × VCC V Low-Level Output Voltage at 4mA Sink Current VOL (Note 5) 0.4 V DS28C16 I2C Low-Voltage SHA-3 Authenticator www.analog.com Analog Devices | 2

Electrical Characteristics (continued) (Limits are 100% tested at T A = +25ºC and T A = +85ºC. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Fall Time from VIH(MIN) to VIL(MAX) with a Bus Capacitance from 10pF to 400pF tOF (Note 4) 30 ns Pulse Width of Spikes that are Suppressed by the Input Filter tSP 50 ns Input Current with an Input Voltage Between 0.1VCC(MAX) and 0.9VCC(MAX) II (Note 4, Note 6) -1 +1 µA Input Capacitance CI (Note 4) 10 pF SCL Clock Frequency fSCL (Note 1) 1 MHz Hold Time (Repeated) START Condition tHD:STA 0.45 µs Low Period of the SCL Clock tLOW (Note 7) 0.65 µs High Period of the SCL Clock tHIGH 0.35 µs Setup Time for a Repeated START Condition tSU:STA 0.35 µs Data Hold Time tHD:DAT (Note 4, Note 7, Note 8) 0.35 µs Data Setup Time tSU:DAT (Note 7, Note 9) 100 ns Setup Time for STOP Condition tSU:STO 0.35 µs Bus Free Time Between a STOP and START Condition tBUF 0.6 µs Capacitive Load for Each Bus Line CB (Note 1, Note 10) 400 pF Warm-Up Time tOSCWUP (Note 1, Note 11) 1 ms CRYPTO FUNCTIONS Computation Current ICMP 3 mA Read Memory Time tRM 5 ms Write Memory Time tWM 60 ms Short Write Memory Time tWMS 15 ms Computation Time tCMP 15 ms EEPROM Write/Erase Cycles (Endurance) NCY (Note 12) 100k Data Retention tDR TA = +85ºC (Note 13) 10 years DS28C16 I2C Low-Voltage SHA-3 Authenticator www.analog.com Analog Devices | 3

Note 1: System requirement. Note 2: Operating current during I2C communication at 1MHz with < 25ns rise and fall times on SDA and SCL. Note 3: All I2C timing values are referred to VIH(MIN) and VIL(MAX) levels. Note 4: Guaranteed by design and/or characterization only. Not production tested. Note 5: The I-V characteristic is linear for voltages less than 1V. Note 6: I/O pins of the DS28C16 do not obstruct the SDA and SCL lines if VCC is switched off. Note 7: tLOW min = t HD:DAT max + 200ns for rise or fall time + t SU:DAT min. Values greater than these can be accommodated by extending tLOW accordingly. Note 8: The DS28C16 provides a hold time of at least 100ns for the SDA signal (referenced to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 9: The DS28C16 can be used in a standard-mode I2C-bus system, but the requirement tSU:DAT ≥ 250ns must then be met. Also, the acknowledge timing must meet this setup time (I2C bus specification Rev. 03, 19 June 2007). Note 10: CB = Total capacitance of one bus line in pF. The maximum bus capacitance allowable may vary from this value depending on the actual operating voltage and frequency of the application (I2C bus specification Rev. 03, 19 June 2007). Note 11: I2C communication should not take place for at least tOSCWUP after VCC reaches VCC(MIN). Note 12: Write-cycle endurance is tested in compliance with JESD47H. Note 13: Data retention is tested in compliance with JESD47H. DS28C16 I2C Low-Voltage SHA-3 Authenticator www.analog.com Analog Devices | 4

EP* *EP = EXPOSED PAD Pin Description PIN NAME FUNCTION 1–3, 5 DNC Do Not Connect 4 GND Ground Reference. Connect all contacts to GND. 6 SCL I2C Clock. Connect to VCC with pullup resistor. 7 SDA I2C Data. Connect to VCC with pullup resistor.

8 VCC Supply Voltage

— EP Exposed Pad (TDFN Only). Solder evenly to the board's ground plane for proper operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information. DS28C16 I2C Low-Voltage SHA-3 Authenticator www.analog.com Analog Devices | 5

counter, and control registers. The device operates from an I2C interface. Figure 1. Block Diagram section provides an overview including the decrement counter. Refer to the DS28C16 Security User Guide for details. additional decrements are possible.

change in state of SDA from high to low while SCL remains high. change in state of SDA from low to high while SCL remains high. START condition, but without leaving the bus idle after a STOP condition. With the exception of the START and STOP condition, transitions of SDA can occur only during the low state of SCL. pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL pulse. generates all SCL clock pulses, including those needed to read from a slave. NOTE:NOTE: TIMING REFERENCED TO VIH(MIN) AND VIL(MAX). Figure 4. I2C Timing Diagram

Ordering Information

PART NUMBER TEMP RANGE PIN-PACKAGE DS28C16Q+T -40°C to +85°C 8 TDFN-EP* (2.5k pcs) +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. DS28C16 I2C Low-Voltage SHA-3 Authenticator www.analog.com Analog Devices | 9

Revision History

0 2/20 Initial release — 1 7/20 Added user guide link 1 2 10/20 Updated data sheet title All 3 1/22 Updated I2C Slave Address 7 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. DS28C16 I2C Low-Voltage SHA-3 Authenticator w w w . a n a l o g . c o m Analog Devices | 10