DS2751 MAXIM | Alldatasheet
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Technical content
FEATURES
/g167/g32Available in Two Configurations - Internal 25m /g87 Sense Resistor - External User-Selectable Sense Resistor /g167/g32Current Measurement - 12-Bit Bidirectional Measurement - Internal Sense Resistor Configuration: 0.625mA LSB and ±1.9A Dynamic Range - External Sense Resistor Configuration: 15.625/g109V LSB and ±64mV Dynamic Range /g167/g32Current Accumulation - Internal Sense Resistor: 0.25mAhr LSB - External Sense Resistor: 6.25 /g109Vhr LSB /g167/g32Voltage Measurement with 4.88mV Resolution /g167/g32Temperature Measurement Using Integrated Sensor with 0.125/g176C Resolution /g167/g3232 Bytes of Lockable EEPROM /g167/g3216 Bytes of General-Purpose SRAM /g167/g32Dallas 1-Wire ® Interface with Unique 64-Bit Device Address /g167/g32Supports 1-Cell Li+/Polymer or 3-Cell Ni Battery Packs /g167/g323mm Dimension of 8-Pin TSSOP Package Allows Mounting on Side of Thin Li+ and Li+/Polymer Cells (Lead Free available) /g167/g32Low Power Consumption: - Active Current: 60 /g109A (typ), 90/g109A (max) - Sleep Current: 1 /g109A (typ), 2/g109A (max) PIN CONFIGURATION PIN DESCRIPTION VIN Voltage-Sense Input VSS Device Ground PIO Programmable I/O Pin VDD Power-Supply Input (2.5V to 5.5V) IS1 Current-Sense Input IS2 Current-Sense Input SNS Sense Resistor Connection DQ Data Input/Output DS2751 Multichemistry Battery Fuel Gauge www.maxim-ic.com DS2751E 8-Pin TSSOP Package (Lead Free Available) VIN DQ SNS IS2 PIO V SS 2 VDD 4 IS1 1-Wire is a registered trademark of Dallas Semiconductor.
ORDERING INFORMATION
PART MARKING TEMP RANGE DESCRIPTION DS2751E 2751E -20/g176C to +70/g176C 8-Pin TSSOP, External Sense Resistor DS2751E+ 2751E (Note 1) -20/g176C to +70/g176C 8-Pin Lead Free TSSOP, External Sense Resistor DS2751E-025 2751R -20/g176C to +70/g176C 8-Pin TSSOP, 25m /g87 Sense Resistor DS2751E+025 2751R (Note 1) -20/g176C to +70/g176C 8-Pin Lead Free TSSOP, 25m/g87 Sense Resistor DS2751E/T&R 2751E -20/g176C to +70/g176C DS2751E on Tape-and-Reel DS2751E+T&R 2751E (Note 1) -20/g176C to +70/g176C DS2751E+ on Tape-and-Reel (Lead Free) DS2751E-025/T&R 2751R -20/g176C to +70/g176C DS2751E-025 on Tape-and-Reel DS2751E+025/T&R 2751R (Note 1) -20/g176C to +70/g176C DS2751E+025 on Tape-and-Reel (Lead Free) Note 1: A “+” will be marked on the package near the Pin 1 indicator.
DESCRIPTION
The DS2751 multichemistry battery fuel gauge is a da ta-acquisition and inform ation-storage device tailored for cost-sensitive and space-constraine d 1-cell Li+/polymer or 3-cell Ni battery-pack applications. The DS2751 provides the key hardwa re components required to accurately estimate remaining capacity by integrating low-power, precision measurements of temperature, voltage, current, and current accumulation, as well as nonvolatile (NV) da ta storage, into the small footprint of a 3.0mm x 4.4mm 8-pin TSSOP package. Through its 1-Wire interface, the DS2751 gives the host system read/write access to status and control registers, instrumentation registers, and general-pur pose data storage. Each device has a unique factory- programmed 64-bit net address that allows it to be individually addressed by the host system, supporting multibattery operation. The DS2751 performs temperature, voltage, and current measurement to a resolution sufficient to support process-monitoring applications such as battery charge control and remaining capacity estimation. Temperature is measured using an on-chip sensor, eliminating the need for a separate thermistor. Bidirectional current measurement and accumulati on are accomplished using either an internal 25m /g87 sense resistor or an external device. The DS2751 also features a programmable I/O pin that allows the host system to sense and control ot her electronics in the pack, incl uding switches, vibration motors, speakers, and LEDs. Three types of memory are provided on the DS2751 fo r battery information storage: EEPROM, lockable EEPROM, and SRAM. EEPROM memory saves important battery data in true NV memory that is unaffected by severe battery depletion, accidental shorts, or ESD events. Lockable EEPROM becomes ROM when locked to provide additional securi ty for unchanging battery data. SRAM provides inexpensive storage for temporary data.
ABSOLUTE MAXIMUM RATINGS* Voltage on PIO Pin, Relative to VSS -0.3V to +12V Voltage on All Other Pins, Relative to VSS -0.3V to +6V Continuous Internal Sense Resistor Current /g1772.5A Pulsed Internal Sense Resistor Current /g17750A for <100µs/s, <1000 Pulses Operating Temperature Range -40°C to +85°C Storage Temperature Range -55°C to +125°C Soldering Temperature See J-STD-020A Specification * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = 2.5V /g163 VDD /g163 5.5V, -20/g176C to +70/g176C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V DD (Note 1) 2.5 5.5 V Data Pin DQ (Note 1) -0.3 +5.5 V VDD /g179 4.2V (Notes 1, 2) -0.3 +4.5 V VIN Pin V IN 2.5V < VDD < 4.2V (Notes 1, 2) VDD + 0.3 V DC ELECTRICAL CHARACTERISTICS (TA = 2.5V /g163 VDD /g163 5.5V, -20/g176C to +70/g176C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Active Current I ACTIVE DQ = VDD, normal operation 60 90 /g109A Sleep-Mode Current I SLEEP DQ = 0V, no activity 1 2 /g109A Input Logic High: DQ, PIO VIH (Note 1) 1.5 V Input Logic Low: DQ, PIO VIL (Note 1) 0.4 V Output Logic Low: DQ, PIO VOL IOL = 4mA (Note 1) 0.4 V DQ Pulldown Current I PD 1 /g109A Input Resistance: VIN R IN 5 M/g87 Internal Current-Sense Resistor RSNS +25/g176C 20 25 30 m/g87 DQ Low-to-Sleep Time tSLEEP 2.2 s Undervoltage Detect V UV (Note 1) 2.5 2.6 2.7 V Undervoltage Delay T UVD 90 100 110 ms
ELECTRICAL CHARACTERISTICS: TEMPERATURE, VOLTAGE, CURRENT (TA = 2.5V /g163 VDD /g163 5.5V, -20/g176C to +70/g176C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Temperature Resolution T LSB 0.125 /g176C Temperature Full-Scale Magnitude TFS 127 /g176C Temperature Error T ERR (Note 3) /g1773 /g176C Voltage Resolution V LSB 4.88 mV Voltage Full-Scale Magnitude VFS (Note 4) 4.5 V Voltage Offset Error V OERR (Note 5) 1 LSB Voltage Gain Error V GERR 3 %V reading (Note 6) 0.625 mA Current Resolution I LSB (Note 7) 15.625 /g109V (Notes 6, 7) 1.9 2.56 A Current Full-Scale Magnitude I FS (Note 8) 64 mV Current Offset Error I OERR (Note 9) 1 LSB (Notes 6, 10) 3 Current Gain Error I GERR (Note 7) 1 reading (Note 6) 0.25 mAhr Accumulated Current Resolution q CA (Note 7) 6.25 µVhr Current Sampling Frequency fSAMP 1456 Hz 0°C to +50°C (Note 11) /g1771 /g1773 Internal Timebase Accuracy tERR -20°C to +70°C ±5 ELECTRICAL CHARACTERISTICS—1-WIRE INTERFACE (TA = 2.5V /g163 VDD /g163 5.5V, -20/g176C to +70/g176C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Time Slot t SLOT 60 120 /g109s Recovery Time t REC 1 /g109s Write 0 Low Time t LOW0 60 119 /g109s Write 1 Low Time t LOW1 1 15 /g109s Read Data Valid t RDV 15 /g109s Reset Time High t RSTH 480 /g109s Reset Time Low t RSTL 480 960 /g109s Presence-Detect High t PDH 15 60 /g109s Presence-Detect Low t PDL 60 240 /g109s DQ Capacitance C DQ 60 pF
EEPROM RELIABILITY SPECIFICATION (TA = 2.5V /g163 VDD /g163 5.5V, -20/g176C to +70/g176C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Copy to EEPROM Time t EEC 2 10 ms EEPROM Copy Endurance NEEC (Note 12) 25,000 cycles Note 1: All voltages are referenced to VSS. Note 2: Operating VIN > 4.5V relative to VSS, or VIN > VDD + 0.3V can induce errors in voltage, temperature, or current measurements. Note 3: Self heating due to output pin loading and sense resistor power dissipation can alter the reading from ambient conditions. Note 4: Although the Voltage Register is large enough to report values larger than 4.75V, the internal compensation for circuit variations can reduce the maximum reportable voltage to as low as 4.75V. Note 5: Voltage offset measurement is with respect to 4.35V at +25°C. Note 6: Internal current-sense resistor configuration. Note 7: External current-sense resistor configuration. Note 8: The Current Register supports measurement magnitudes up to 2.56A using the internal sense- resistor option and 64mV with the external resistor option. Compensation of the internal sense-resistor value for process and temperature variation may reduce the maximum reportable magnitude to 1.9A. Note 9: Current offset error null to ±1 LSb typically requires a one time 3.5s in-system calibration by user. Note 10: Current gain-error specification applies to gain error in converting the voltage difference at IS1 and IS2, and excludes any error remaining after the DS2751 compensates for the internal sense-resistor’s temperature coefficient of 3700ppm//g176C to an accuracy of /g177500ppm//g176C. The DS2751 does not compensate for external sense resistor characteristics, and any error terms arising from the use of an external sense resistor should be taken into account when calculating total current measurement error. Note 11: Typical value for t ERR valid at 3.6V and +25/g176C. Note 12: Four year data retention at +70/g176C.
Figure 1. FUNCTIONAL DIAGRAM
Figure 2. APPLICATION EXAMPLE 1) RSENS is present for external sense resistor configurations only. 2) RSENSINT is present for internal sense resistor configurations only. SLEEP (2.2s) (pack disconnection). IN is above VUV. The factory default for the DS2751 is UVEN = PMOD = 0. The DS2751 defaults to active mode when power is first applied.
reported at the limit of the range. The format of the Current Register is shown in Figure 3. temperature effects when reporting current. Register in units of volts, with a resolution of 15.625/g109V and a /g17764mV full-scale range. Figure 3. CURRENT REGISTER FORMAT complement format. The format of the Current Accumulator is shown in Figure 4. 6.25/g109Vhrs and a /g177205mVhrs full-scale range. The Current Accumulator is a read/write register that can be altered by the host system as needed.
Table 3. MEMORY MAP
00 Reserved
01 Status Register R
07 EEPROM Register R/W
08 Special Feature Register R/W
10 Accumulated Current Register MSB R/W
11 Accumulated Current Register LSB R/W
18 Temperature Register MSB R
19 Temperature Register LSB R
*Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only. in detail in the following paragraphs. Figure 8. STATUS REGISTER FORMAT DQ line goes low for greater than t SLEEP. A value of 0 disables the DS2751 from entering the sleep mode. be set in bit 4 of address 31h. The factory default is 0.
upon power-up and after each subsequent occurrence of a POR. PIO— PIO Pin Sense and Control. See the Programmable I/O section for details on this read/write bit. Bus System section of this data sheet. Figure 11. 1-WIRE NET ADDRESS FORMAT in a communication channel with a very high level of integrity. Dallas Semiconductor Touch Memory Products.
All transactions of the 1-Wire bus begin with an initialization sequence consisting of a reset pulse transmitted by the bus master followed by a pres ence pulse simultaneously transmitted by the DS2751 and any other slaves on the bus. The presence pulse te lls the bus master that one or more devices are on the bus and ready to operate. For more details, see the I/O Signaling section. NET ADDRESS COMMANDS Once the bus master has detected the presence of one or more slaves, it can issue one of the net address commands described in the following paragraphs. The name of each ROM command is followed by the 8-bit opcode for that command in square brackets. Figu re 14 presents a transaction flowchart of the net address commands. Read Net Address [33h or 39h]. This command allows the bus master to read the DS2751’s 1-Wire net address. This command can only be used if there is a single slave on the bus. If more than one slave is present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The RNAOP bit in the Status Re gister selects the opcode for this command, with RNAOP = 0 indicating 33h and RNAOP = 1 indicating 39h. Match Net Address [55h]. This command allows the bus master to specifically address one DS2751 on the 1-Wire bus. Only the addressed DS2751 responds to any subsequent function command. All other slave devices ignore the function command and wait for a reset pulse. This command can be used with one or more slave devices on the bus. Skip Net Address [CCh]. This command saves time when there is only one DS2751 on the bus by allowing the bus master to issue a function command without specifying the address of the slave. If more than one slave device is present on the bus, a subs equent function command can cause a data collision when all slaves transmit data at the same time. Search Net Address [F0h]. This command allows the bus master to use a process of elimination to identify the 1-Wire net addresses of all slave devices on the bus. The search process involves the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple three-step routine on each bit location of the net address. After one complete pass through all 64 bits, the bus master knows the address of one device. The remaining devices can then be identified on additional iterations of the process. See Chapter 5 of the Book of DS19xx i Button® Standards for a comprehensive discussion of a net address search, including an actual example. This publication can be found on the Maxim/Dallas website at www.maxim-ic.com. FUNCTION COMMANDS After successfully completing one of the net address commands, the bus master can access the features of the DS2751 with any of the function commands described in the following paragraphs. The name of each function is followed by the 8-bit opcode for that command in square brackets. Read Data [69h, XX]. This command reads data from the DS2751 st arting at memory address XX. The LSb of the data in address XX is available to be r ead immediately after the MSb of the address has been entered. Because the address is automatically incremented after the MSb of each byte is received, the LSb of the data at address XX + 1 is available to be read immediately after the MSb of the data at address XX. If the bus master continues to read beyond addr ess FFh, the DS2751 outputs logic 1 until a reset pulse occurs. Addresses labeled “reserved” in the memo ry map contain undefined data. The Read Data command can be terminated by the bus master with a reset pulse at any bit boundary. iButton is a registered trademark of Dallas Semiconductor.
LSb to be stored at address XX + 1 can be written immediately after the MSb to be stored at address XX. EEPROM block containing address XX. Copy Data co mmands that address lock ed blocks are ignored. permanent; a locked block can never be written again. Table 4. FUNCTION COMMANDS
Figure 14. NET ADDRESS COMMAND FLOW CHART
1 BYTE
6 BYTES
Read Data. All of these types of signaling except the presence pulse are initiated by the bus master. The initialization sequence required to begin any communication with the DS2751 is shown in Figure 15. A presence pulse following a rese t pulse indicates the DS2751 is read y to accept a net address command. PDH and then transmits the Presence Pulse for tPDL. Figure 15. 1-WIRE INITIALIZATION SEQUENCE slot, the bus line must be pulled low and held low for the duration of the write time slot. 1/g109s minimum recovery time, tREC, between cycles. See Figure 16 for more information.
Figure 16. 1-WIRE WRITE AND READ TIME SLOTS