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19-4632; 5/09 DS2746 Low-Cost 2-Wire Battery Monitor with Ratiometric A/D Inputs 1 of 17 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. www.maxim-ic.com GENERAL DESCRIPTION The DS2746 provides system-side battery capacity monitoring in cost-sensitive applications. Voltage, bidirectional current, and accumulated current measurement data is provided to the host processor over a 2-wire interface. Offset bias and offset blanking features greatly enhance the accuracy of the coulomb counter. In addition, the DS2746 has two auxiliary A/D inputs to sample the pack identification resistor, ther mistor, or other voltage source. The results are reported as a ratiometric fraction of the supply voltage eliminating error related to the supply. The DS2746 reduces the total power consumption of the measurement circuit by enabling the resistor dividers, through the V OUT pin, only while measurements are made. When the system is inactive, a low power sleep mode reduces current consumption while maintaining the coulomb count. The tiny 3mm × 3mm TDFN package consumes only 9mm 2 of PCB space.
APPLICATIONS
2.5G/3G Wireless Handsets PDA/Smartphones Digital Still and Video Cameras Handheld Computers and Terminals TYPICAL OPERATING CIRCUIT
FEATURES
14-Bit Bidirectional Current Measurement - 6.25 V LSB, ±51.2mV Dynamic Range - 416.7 A LSB, ±3.4A Range (RSNS = 15m) Current Accumulation Register Resolution - 6.25 Vhr LSB, 409.6mVh Range - 417 Ahr LSB, 27.31Ah Range 11-Bit Battery Voltage Measurement - 2.44mV LSB, 0V to 4.5V Input Range - ±10mV Accuracy at 3.6V Input Two 11-Bit Aux Input Voltage Measurements - Ratiometric Inputs Eliminate Supply Error - VOUT drives Dividers, Reduces Power - ±8 LSB Accuracy Low Power Consumption: - Active Current: 70 A typical, 100A max - Sleep Current: 1 A typical, 3A max
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS2746G+ -20ºC to +70ºC 10-Pin 3mm×3mm TDFN DS2746G+T&R -20ºC to +70ºC DS2746G+ in Tape- and-Reel + Denotes lead(Pb)-free/RoHS-compliant package. PIN CONFIGURATION TOP VIEW 3mm × 3mm TDFN
DS2746 Low-Cost 2-Wire Battery Monitor 2 of 17 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground -0.3V to +6V Operating Temperature Range -40°C to +85°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/JEDECJ-STD-020A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (VDD = 2.5V to 4.5V, TA = -20°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDD (Note 1) +2.5 +4.5 V Data I/O Pins SCL, SDA (Note 1) -0.3 +5.5 V Programmable I/O Pin PIO (Note 1) -0.3 +5.5 V VIN, AIN0, AIN1 Pin VIN, AIN0, AIN1 (Note 1) -0.3 V DD + 0.3 V DC ELECTRICAL CHARACTERISTICS (VDD = 2.5V to 4.5V, TA = -20°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 70 100 Active Current IACTIVE VDD = 4.5V 105 A VDD = 2.0V, SCL, SDA = Vss 0.5 1.0 Sleep-Mode Current ISLEEP SCL, SDA = Vss 1 3 Current Resolution ILSB 6.25 V Current Full-Scale Magnitude IFS (Note 1) ±51.2 mV Current Offset IOERR (Note 2) -12.5 +12.5 V Current Gain Error IGERR (Note 11) -1.5 +1.5 % of reading VDD = 3.6V at +25°C -1 +1 TA = 0C to +70C -2 +2 % Timebase Accuracy tERR VDD = VIN = 3.6V -10 +10 Voltage Error VGERR -20 +20 mV Input Resistance VIN, AIN0, AIN1 RIN 15 MΩ AIN0, AIN1 Error AINGERR (Note 10) -8 +8 LSB VOUT Output Drive IO = 1mA VDD -0.1 V VOUT Precharge Time tPRE VODIS bit = 0 13.3 14.2 ms Input Logic High: SCL, SDA VIH (Note 1) 1.5 V Input Logic Low: SCL, SDA VIL (Note 1) 0.6 V Output Logic Low: SDA VOL IOL = 4mA, (Note 1) 0.4 V Pulldown Current: IPD V DD = 4.2V, 0.2 A
DS2746 Low-Cost 2-Wire Battery Monitor 3 of 17 SCL, SDA V PIN = 0.4V Input Capacitance: SCL, SDA CBUS 50 pF Bus Low Timeout tSLEEP (Note 3) 1.5 2.2 S DC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (VDD = 2.5V to 4.5V, TA = -20°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency fSCL (Note 4) 0 400 KHz Bus Free Time Between a STOP and START Condition tBUF 1.3 µs Hold Time (Repeated) START Condition tHD:STA (Note 5) 0.6 µs Low Period of SCL Clock tLOW 1.3 µs High Period of SCL Clock tHIGH 0.6 µs Setup Time for a Repeated START Condition t SU:STA 0.6 µs Data Hold Time tHD:DAT (Note 6, 7) 0 0.9 µs Data Setup Time tSU:DAT (Note 6) 100 ns Rise Time of Both SDA and SCL Signals t R 20 + 0.1CB 300 ns Fall Time of Both SDA and SCL Signals tF 20 + 0.1CB 300 ns Setup Time for STOP Condition tSU:STO 0.6 µs Spike Pulse Widths Suppressed by Input Filter tSP (Note 8) 0 50 ns Capacitive Load for Each Bus Line C B (Note 9) 400 pF SCL, SDA Input Capacitance CBIN 60 pF Note 1: All voltages are referenced to VSS. Note 2: Offset specified after auto-calibration cycle and Current Offset Bias register = 0x00. Note 3: The DS2746 enters the sleep mode 1.5s to 2.2s after ( SCL < Vil.) AND ( SDA < Vil ). Note 4: Timing must be fast enough to prevent the DS2746 from entering sleep mode due t o bus low for period > tSLEEP. Note 5: fSCL must meet the minimum clock low time plus the rise/fall times. Note 6: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 7: This device internally provides a hold time of at least 100ns for the SDA signal (referr ed to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 8: Filters on SDA and SCL suppress noise spikes at the input buffers and dela y the sampling instant. Note 9: Cb – total capacitance of one bus line in pF. Note 10: The AINGERR spec is only valid when this equation is satisfied: (VAINx + 2VOUT) (11.6V - (TA - 25C)10mV/C). See Figure 1. Note 11: Accuracy specification valid for VSS - SNS ≥ ±2.5mV, below which offset error is dominant.
DS2746 Low-Cost 2-Wire Battery Monitor 5 of 17 PIN DESCRIPTION PIN NAME FUNCTION 1 AIN1 Aux Voltage Input Number 1. 2 AIN0 Aux Voltage Input Number 0. 3 SCL Serial Clock Input. Input only 2-wire clock line. Connect this pin to the CLOCK signal of the 2-wire interface. This pin has a 0.2µA typical pulldown to sense disconnection.
4 SDA
Serial Data Input / Output. Open drain 2-wire data line. Connect this pin to the DATA signal of the 2-wire interface. This pin has a 0.2µA typical pulldown to sense disconnection. 5 SNS Current-Sense Input. Connect to the handset side of the sense resistor. 6 V SS Device Ground. Connect to the battery side of the sense resistor. 7 CTG Connect to Ground. Connect to the battery side of the sense resistor. 8 V OUT Voltage Out. Supply for Aux input voltage Measurement dividers. Connect to high side of resistor divider circuits. 9 V IN Battery Voltage Input. The voltage of the cell pack is measured through this pin. 10 V DD Power-Supply Input. 2.5V to 4.5V input range. Connect to system power through a decoupling network. PAD PAD Exposed Pad. Connect to VSS.
Figure 3. Block Diagram Current register (ACR) to maintain a sum of all charge entering and exiting the cell. consumption when the auxiliary inputs are not in use. IN, AIN0, and AIN1 pins repeatedly in that order. An internal reference is used to measure VIN voltage. wide temperature and operating conditions. DS2746 into a low power sleep mode where A/D measurements are paused and the ACR register is maintained. FuelPack is a trademark of Maxim Integrated Products, Inc.
Figure 4. APPLICATION EXAMPLE allowed to all registers. In sleep mode, the DS2746 operates in a low-power mode with no measurement activity. remains in SLEEP and cannot accumulate the charge current. every 878ms with the average for that time period. sequence as long as the VODIS (VOUT Disable) bit is cleared. See Figure 5.
Table 1. Current Resolution for Various RSNS Values Table 2. Current Range for Various RSNS Values approximately once per hour. The resulting correction fa ctor is applied to the subsequent 1023 measurements. much less than 1/1024 of the expected reading. charge values and at 0000h when accumulating discharge values. cleared. A write to the ACR also forces the ADC to measure its offset and update the offset correction factor. ACR’s dynamic range for several different sense resistor options. Figure 9. Accumulated Current Register Format
Table 3. Accumulated Current Range for Various RSNS Values interface on power-up. Figure 10 describes the COBR address, format, and resolution. Figure 10. Current Offset Bias Register Format Status/Config register. See the register description for additional information. that are too small to measure. ABR value is not subject to the Current Blanking thresholds. subsequent current measurements. ABR can be set to any value between +193.75V and -200V in 6.25V steps. address, format, and resolution.
Figure 1. Accumulation Bias Register Format always read the MSB and the LSB of a two-byte register during the same read data command sequence. Table 4. Memory Map
00 Reserved —
01 Status/Config Register R/W X1110X00b
08 Auxiliary Input 0 Register MSB R 00h
09 Auxiliary Input 0 Register LSB R 00h
10 Accumulated Current Register MSB R/W Undefined
11 Accumulated Current Register LSB R/W Undefined
61 Offset Bias Register R/W 00h
62 Accumulation Bias Register R/W 00h
well as program or select device functionality. Figure 12. Status/Config Register Format charge to full in order to synchronize the ACR with the battery charge state. PORF is read/write-to-zero. for tSLEEP. A value of 0 disables the transition to sleep mode. The power-up default is SMOD = 1. of 0 disables blanking of negative currents. The power-up default is NBEN = 1. the AIN1 conversion ends. The power-up default is VODIS = 0, a value of 1 disables the VOUT output. the AIN1 bit is set, should the AIN1 register be read. the AIN0 bit is set, should the AIN0 register be read. well as the START and STOP bits which begin and end each transaction. change in SDA when SCL is high is interpreted as a START or STOP control signal.
DS2746 Low-Cost 2-Wire Battery Monitor 14 of 17 Bus Idle The bus is defined to be idle, or not busy, when no master device has control. Both SDA and SCL remain high when the bus is idle. The STOP condition is the proper method to return the bus to the idle state. START and STOP Conditions The master initiates transactions with a START condition (S), by forcing a high-to-low transition on SDA while SCL is high. The master terminates a transaction with a STOP condition (P), a low-to-high transition on SDA while SCL is high. A REPEATED START condition (Sr) can be used in place of a STOP then STAR T sequence to terminate one transaction and begin another without returning the bu s to the idle state. In multimaster systems, a REPEATED START allows the master to retain control of the bus. The START and STOP conditions are the only bus activities in which the SDA transitions when SCL is high. Acknowledge Bits Each byte of a data transfer is acknowledged with an Ac knowledge bit (A) or a No Acknowledge bit (N). Both the master and the DS2746 slave generate acknowledge bits. To generate an Acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until SCL returns low. To generate a No Acknowledge (also called NAK), the receiver releases SDA before the rising edge of the acknowledge-related clock pulse an d leaves SDA high until SCL returns lo w. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer can oc cur if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should re- attempt communication. Data Order A byte of data consists of 8 bits ordered most significant bit (msb) first. The least significant bit (lsb) of each byte is followed by the Acknowledge bit. DS2746 registers composed of multibyte values are ordered most significant byte (MSB) first. The MSB of multibyte registers is stored on even data memory addresses. Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by a Slave Address (SAddr) and the read/write (R/W) bit. When the bus is idle, the DS2746 continuously monitors for a START condition followed by its slave address. When the DS2746 receives a slave address that matches its Slave Address, it responds with an Acknowledge bit during the clock period following the R/W bit. The 7-bit Slave Address is fixed. DS2746 Slave Address 0110110 Read/Write Bit The R/W bit following the slave address determines the data direction of subsequent bytes in the transfer. R/W = 0 selects a write transaction, with the following bytes being written by the master to the slave. R/W = 1 selects a read transaction, with the following bytes being read from the stave by the master. Bus Timing The DS2746 is compatible with any bus timing up to 400kHz. No special configuration is required to operate at any speed. 2-Wire Command Protocols The command protocols involve several transaction formats. The simplest format consists of the master writing the START bit, slave address, R/W bit, and then monitoring the acknowledge bit for presence of the DS2746. More complex formats such as the Write Data, Read Data and Function command protocols write data, read data and execute device specific operations. All bytes in each command format require the slave or host to return an Acknowledge bit before continuing with the next byte. Each function command definition outlines the required transaction format. The following key applies to the transaction formats.
Table 5. 2-Wire Protocol Key except for the Acknowledge cycles. the master following the Acknowledge clock. sending a STOP or REPEATED START after receiving the last acknowledge bit. memory. As noted in the Memory Section, writes to unlocked EEPROM blocks modify the shadow RAM only. from MAddr + 1 and DataN represents the last byte read by the master.
DS2746 Low-Cost 2-Wire Battery Monitor 16 of 17 Data is returned beginning with the most significant bit (msb) of the data in MAddr. Because the address is automatically incremented after the least significant bit (lsb) of each byte is return ed, the msb of the data at address MAddr + 1 is available to the host immediately after the acknowledgement of the data at address MAddr. If the bus master continues to read beyond address FFh, the DS2746 outputs data values of FFh. Addresses labeled “Reserved” in the memory map return undefined data. The bus master terminates the re ad transaction at any byte boundary by issuing a No Acknowledge followed by a STOP or REPEATED START.
PACKAGE INFORMATION
For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
10 TDFN T1033+1 21-0137
DS2746 Low-Cost 2-Wire Battery Monitor 17 of 17
REVISION HISTORY
Changed the VDD maximum operating range in the Electrical Characteristics table to 4.5V. 2, 3
051209 Added “VIN pin is limited to VDD voltage” text in the Voltage Measurement
section. 8 17 of 17 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.