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19-4631; 5/09 DS2745 Low-Cost I2C Battery Monitor
FEATURES
16-Bit Bidirectional Current Measurement 1.56V LSB, ±51.2mV Dynamic Range 104A LSB, ±3.4A Dynamic Range (RSNS = 15m) Current Accumulation Register Resolution 6.25Vhr LSB, ±204.8mVh Range 0.417mAhr LSB, ±13.65Ah Range (RSNS = 15m) 11-Bit Voltage Measurement 4.88mV LSB, 0V to 4.5V Input Range 11-Bit Temperature Measurement 0.125ºC Resolution, -20ºC to +70ºC Industry Standard I 2C* Interface Low Power Consumption: Active Current: 70A typical, 100A max Sleep Current: 1A typical, 3A max BLOCK DIAGRAM www.maxim-ic.com PIN CONFIGURATION VDD
DESCRIPTION
The DS2745 provides current-flow, voltage, and temperature measurement data to support battery- capacity monitoring in cost-sensitive applications. The DS2745 can be mounted on either the host side or pack side of the applicati on. Current measurement and coulomb counting is accomplished by monitoring the voltage drop across an external sense resistor, voltage measurement is accomplished through a separate voltage-sense input, and temperature measurement takes place on-chip. A standard I interface with software programmable address gives the controlling microprocessor access to all data and status registers inside the DS2745. A low-power sleep mode state conserves energy when the cell pack is in storage.
APPLICATIONS
Table 1. ORDERING INFORMATION +Denotes lead(Pb)-free/RoHS-compliant package. C Standard Specification as defined by Philips. See Table 1 for Ordering Information.
DS2745 Low-Cost I2C Battery Monitor 2 of 15 ABSOLUTE MAXIMUM RATINGS* Voltage on All Pins Relative to VSS -0.3V to +6V Operating Temperature Range -40°C to +85°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/JEDECJ-STD-020A * This is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (2.5V VDD 4.5V; TA = 0C to +70C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDD (Note 1) +2.5 +4.5 V Serial Data I/O Pin SDA (Note 1) -0.3 +5.5 V Serial Clock Pin SCL (Note 1) -0.3 +5.5 V Programmable I/O Pin PIO (Note 1) -0.3 +5.5 V VIN Pin VIN (Note 1) -0.3 VDD +0.3 V DC ELECTRICAL CHARACTERISTICS (2.5V VDD 4.5V; TA = 0C to +70C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 70 100 Active Current IACTIVE VDD = 4.5V 105 Sleep-Mode Current ISLEEP SCL = SDA = VSS, PIO = VSS 1 3 A Current Resolution ILSB 1.56 V/R Current Full-Scale Magnitude IFS (Note 1) 51.2 mV/R Current Offset IOERR (Note 2) -7.82 +12.5 V/R Current Gain Error IGERR -1.0 +1.0 % of reading Accumulated Current Resolution qCA 6.25 Vh/R Accumulated Current Offset qOERR V SNS = VSS, (Notes 4, 5) -188 +0 µVh/R per day Voltage Resolution VLSB 4.88 mV Voltage Full-Scale VFS 0 4.992 V Voltage Error VGERR (Note 12) -25 +25 mV Temperature Resolution TLSB 0.125 °C Temperature Error TERR -3 +3 ºC Current Sample Clock Frequency f SAMP 18.6 kHz Timebase Accuracy tERR VDD = 3.8V, TA = +25°C ±1 %
DS2745 Low-Cost I2C Battery Monitor 3 of 15 2.5V ≤ VDD ≤ 4.5V ±3 Input Resistance, VIN RIN 15 M Input Logic High: SCL, SDA, PIO VIH (Note 1) 1.5 V Input Logic Low: SCL, SDA, PIO VIL (Note 1) 0.6 V Output Logic Low: SDA, PIO VOL IOL = 4mA (Note 1) 0.4 V Pulldown Current: SCL, SDA, PIO I PD 0.25 A Input Capacitance: SCL, SDA CBUS 50 pF SLEEP Timeout tSLEEP (Note 3) 2.2 S 2-WIRE INTERFACE TIMING SPECIFICATIONS (VDD = 2.5V to 4.5V, TA = -20C to +70C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency fSCL (Note 6) 0 400 KHz Bus Free Time Between a STOP and START Condition tBUF 1.3 µs Hold Time (Repeated) START Condition tHD:STA (Note 7) 0.6 µs Low Period of SCL Clock tLOW 1.3 µs High Period of SCL Clock tHIGH 0.6 µs Setup Time for a Repeated START Condition tSU:STA 0.6 µs Data Hold Time tHD:DAT (Note 8, 9) 0 0.9 µs Data Setup Time tSU:DAT (Note 8) 100 ns Rise Time of Both SDA and SCL Signals tR 20 + 0.1CB 300 ns Fall Time of Both SDA and SCL Signals tF 20 + 0.1CB 300 ns Setup Time for STOP Condition tSU:STO 0.6 µs Spike Pulse Widths Suppressed by Input Filter tSP (Note 10) 0 50 ns Capacitive Load for Each Bus Line CB (Note 11) 400 pF SCL, SDA Input Capacitance C BIN 60 pF
Note 1: All voltages are referenced to VSS. Note 2: Offset specified after auto-calibration cycle and Curre nt Offset Bias register (COBR) set to 00h. Note 5: Parameters guaranteed by design. Note 7: fSCL must meet the minimum clock low time plus the rise/fall times. the SCL signal) to bridge the undefined region of the falling edge of SCL. n SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant. Note 11: CBtotal capacitance of one bus line in pF. Note 12: The first volta ge measurement after writing the ACR or after device POR is not valid. Figure 1. I2C Bus Timing Diagram
1 SCL
2 SDA
to a pull up resistor for bidirectional operation. 4 SNS Sense Resistor Connection. Connect to the negative terminal of the battery pack. Connect the sense resistor between VSS and SNS. protection FETs. Connect the sense resistor between VSS and SNS. 7 VIN Voltage Sense Input. The voltage of the Li+ cell is monitored through this input pin. Figure 2. BLOCK DIAGRAM
Temperature is reported in the two-byte Temperature register with 0.125C resolution. wide temperature and operating conditions. and Measurement registers. Additionally, the I2C slave address can be changed from the default after power up. Figure 3. APPLICATION EXAMPLE
1 Cell Li+
FuelPack is a trademark of Maxim Integrated Products, Inc.
SMOD = 1 AND (SDA < VIL AND SCL < VIL) for tSLEEP. battery that is charged on a standalone charger. register in two’s compliment form. Voltages above the maximum register value are reported as 7FFFh. Figure 4. VOLTAGE REGISTER FORMAT cycle after either of these two conditions occur before reading voltage. The DS2745 uses an integrated temperature sensor to measure battery temperature with a resolution of 0.125°C.
Status/Config register. See the register description for additional information. that are too small to measure. ABR value is not subject to the Current Blanking thresholds. interface on power-up. Figure 9 describes the ABR address, format, and resolution. Figure 9. ACCUMULATION BIAS REGISTER FORMAT always read the MSB and the LSB of a two-byte register during the same read data command sequence.
Table 5. MEMORY MAP
00 Reserved —
01 Status/Config Register R/W 11000000b
10 Accumulated Current Register MSB R/W No Change
11 Accumulated Current Register LSB R/W No Change
61 Offset Bias Register R/W 00h
62 Accumulation Bias Register R/W 00h
well as program or select device functionality. Figure 10. STATUS/CONFIG REGISTER FORMAT charge to full in order to synchronize the ACR with the battery charge state. PORF is read/write-to-zero. pins is low for 2s. A value of 0 disables the transition to sleep mode. The power-up default of SMOD = 0. of 0 disables blanking of negative currents. The power-up default of NBEN = 0. readback of an external signal. Reading PIO returns the logic state on the pin. PIO is RESET on POR.
DS2745 Low-Cost I2C Battery Monitor 12 of 15 2-WIRE BUS SYSTEM The 2-Wire bus system supports operation as a slave only device in a single or multi-slave, and single or multi- master system. Up to 128 slave devices may share the bu s by uniquely setting the 7-bit slave address. The 2-wire interface consists of a serial data line (SDA) and seri al clock line (SCL). SDA and SCL provide bidirectional communication between the DS2745 slave device and a ma ster device at speeds up to 400kHz. The DS2745’s SDA pin operates bidirectionally, that is, when the DS2745 receives data, SDA operates as an input, and when the DS2745 returns data, SDA operates as an open-drain output, with the host system prov iding a resistive pull-up. The DS2745 always operates as a slave device, receiv ing and transmitting data under the control of a master device. The master initiates all transactions on the bus and generates the SCL signal as well as the START and STOP bits which begin and end each transaction. Bit Transfer One data bit is transferred during each SCL clock cycle, with the cycle defined by SCL transitioning low-to-high and then high-to-low. The SDA logic level must remain stab le during the high period of the SCL clock pulse. Any change in SDA when SCL is high is interpreted as a START or STOP control signal. Bus Idle The bus is defined to be idle, or not busy, when no master device has control. Both SDA and SCL remain high when the bus is idle. The STOP condition is the proper method to return the bus to the idle state. START and STOP Conditions The master initiates transactions with a START condition (S), by forcing a high-to-low transition on SDA while SCL is high. The master terminates a transaction with a STOP condition (P), a low-to-high transition on SDA while SCL is high. A Repeated START condition (Sr) can be used in place of a STOP then START sequence to terminate one transaction and begin another without returning the bus to the idle state. In multimaster systems, a Repeated START allows the master to retain control of the bus. The START and STOP conditions are the only bus activities in which the SDA transitions when SCL is high. Acknowledge Bits Each byte of a data transfer is acknowledged with an Acknowledge bit (A) or a No Acknowledge bit (N). Both the master and the DS2745 slave generate acknowledge bits. To generate an Acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-relate d clock pulse (ninth pulse) and keep it low until SCL returns low. To generate a No Acknowledge (also called NAK), the receiver releases SDA before the rising edge of the acknowledge-related clock pulse an d leaves SDA high until SCL returns low. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An un successful data transfer can occur if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should re- attempt communication. Data Order A byte of data consists of 8 bits ordere d most significant bit (msb) first. The least significant bit (lsb) of each byte is followed by the Acknowledge bit. DS2745 registers composed of multi-byte values are ordered most significant byte (MSB) first. The MSB of multi-byte registers is stored on even data memory addresses. Slave Address A bus master initiates communication with a slave dev ice by issuing a START condition followed by a Slave Address (SAddr) and the read/write (R /W) bit. When the bus is idle, the DS2745 continuously monitors for a START condition followed by its slave address. When the DS2745 receives a slave address that matches the value in its Status/Config register, it responds with an Acknowledge bit during the clock period following the R/W bit. The default Slave Address at power-up is 1001000. The lower three bits of t he slave address can be re-programmed, refer to the Status/Config register description for details.
transaction, with the following bytes being read from the stave by the master. transaction format. The following key applies to the transaction formats. Table 3. 2-Wire Protocol Key except for the Acknowledge cycles. the master following the Acknowledge clock.
DS2745 Low-Cost I2C Battery Monitor 14 of 15 Write Data Protocol The write data protocol is used to write to register and shadow RAM data to the DS2745 starting at memory address MAddr. Data0 represent s the data written to MAddr, Data1 represents the data written to MAddr + 1 and DataN represents the last data byte, wri tten to MAddr + N. The master indicates the end of a write transaction by sending a STOP or Repeated START after receiving the last acknowledge bit. S SAddr W A MAddr A Data0 A Data1 A … DataN A P The msb of the data to be stored at address MAddr can be written immedi ately after the MAddr byte is acknowledged. Because the address is automatically incremented after the least significant bit (lsb) of each byte is received by the DS2745, the msb of the data at address MAddr + 1 is can be written immediately after the acknowledgement of the data at address MAddr. If the bus master continues an auto-incremented write transaction beyond address FFh, the DS2745 ignores the data. Data is also ignored on writes to read-only addresses and reserved addresses. Incomplete bytes and bytes that are Not Acknowledged by the DS2745 are not written to memory. Read Data Protocol The Read Data protocol is used to read register a nd shadow RAM data from the DS2745 starting at memory address specified by MAddr. Data0 represents the data byte in memory location MAddr, Data1 represents the data from MAddr + 1 and DataN represents the last byte read by the master. S SAddr W A MAddr A Sr SAddr R A Data0 A Data1 A … DataN N P Data is returned beginning with the most significant bit (msb) of the data in MAddr. Because the address is automatically incremented after the least significant bit (l sb) of each byte is returned, the msb of the data at address MAddr + 1 is available to the host immediately after the acknowledgement of the data at address MAddr. If the bus master continues to read beyond address FFh, the DS2745 outputs data values of FFh. Addresses labeled “Reserved” in the memory map return undefined data. The bus master terminates the read transaction at any byte boundary by issuing a No Acknowledge followed by a STOP or Repeated START.
PACKAGE INFORMATION
For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 8 MAX U8+1 21-0036
DS2745 Low-Cost I2C Battery Monitor
REVISION HISTORY
Changed the VDD maximum operating range in the Electrical Characteristics table to 4.5V. 2, 3
51209 Added “VIN pin is limited to VDD voltage” text in the Voltage Measurement
section. 7 15 of 15 15 of 15 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.