DS2726 MAXIM | Alldatasheet
Document overview
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Technical content
Features
♦ Complete Protection for 5- to 10-Cell Li+ Packs ♦ Pin Programmable for 5 to 10 Cells ♦ ±50mV Overvoltage Accuracy ♦ Internal Cell-Balancing Circuit, Shunts Up to 300mA ♦ Pin-Programmable VOV Threshold ♦ Pin-Programmable Cell-Balance Voltage ♦ Overdischarge Current and Short-Circuit Current Set with External Resistors ♦ Overdischarge Current and Short-Circuit Current Timeout Delay Set with External Capacitors ♦ Low Power Consumption: 60µA (typ) ♦ Low Shutdown Power Consumption: 5µA (typ) ♦ 7mm x 7mm, 32-Pin TQFN Lead-Free Package DS2726 5- to 10-Cell Li+ Protector with Cell Balancing
Ordering Information
Simplified Typical Application Circuit Rev 0; 4/08 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. +Denotes a lead-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad. Pin Configuration appears at end of data sheet. PART TEMP RANGE PIN-PACKAGE DS2726G+ -20°C to +85°C 32 TQFN-EP* DS2726G+T&R -20°C to +85°C 32 TQFN-EP*
5- to 10-Cell Li+ Protector with Cell Balancing ABSOLUTE MAXIMUM RATINGS RECOMMENDED DC OPERATING CONDITIONS (TA = -20°C to +85°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on V00–V10, PKP, Voltage Range on CSCD, SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, SLEEP, CBCFG, V Human Body Model (HBM) ESD Limit of Voltage Range on Any V Continuous Power Dissipation (TA = +70°C) 32-Pin, 7mm x 7mm Thin QFN J-STD-020 Specification. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Range V IN (Notes 1, 2, 3, 4) 5 50 V Input Range: SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, CSCD, CDOCD, SLEEP, CBCFG (Note 1) -0.3 VCC + 0.3 V DC ELECTRICAL CHARACTERISTICS (TA = -20°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IDD Protector mode, no fault (Notes 4, 9) 70 90 IDD_BAL Load balancing (Note 11) 400 Supply Current ISLEEP Sleep mode 5.0 7.5 μA V00–V10 Leakage Current All cell voltages = 4.2V (Note 10) -2 +2 μA Input Logic-High: SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, SLEEP VIH I LOAD = 2μA (Notes 1, 5) VCC - 0.4 V Input Logic-Mid: SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, SLEEP VIM I LOAD = 0 (Notes 1, 5) 1.30 1.65 2.00 V Input Logic-Low: SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, SLEEP VIL I LOAD = -2μA (Notes 1, 5) GND + 0.4 V VCC Output Voltage I LOAD = 1mA (Notes 1, 5, 8) 4.75 5.00 5.25 V VCC Dropout Voltage (Note 6) 5.5 V Output Low: CC V OLCC I OL = -100μA, V PKP 13V (Notes 3, 5) PKP - 12 PKP - 8 V CC = VOLCC + 2V -3 -1 Output Low: CC Driver Current CC = VOHCC - 1V -15 -7 mA
5- to 10-Cell Li+ Protector with Cell Balancing DC ELECTRICAL CHARACTERISTICS (continued) (TA = -20°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High: CC V OHCC I OH = 100μA PKP - 0.5 PKP + 0.3 V CC = VOLCC + 2V 7 15 Output High: CC Driver Current CC = VOHCC - 1V 0.5 1.5 mA Output Low: DC V OLDC I OL = -100μA, V VIN 13V (Notes 3, 5) VIN - VIN - 8 V DC = VOLDC + 2V -3 -1 Output Low: DC Driver Current DC = VOHDC - 1V -15 -7 mA Output High: DC V OHDC I OH = 100μA VIN - 0.5 VIN + 0.3 V DC = VOLDC + 2V 7 15 Output High: DC Driver Current DC = VOHDC - 1V 0.5 1.5 mA Maximum Balancing Current I BAL 300 mA Balance FET: On-Resistance I BAL = 180mA 1.7 3.2 7.0 ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUIT (TA = 0°C to +50°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS OVS1 = GND, OVS0 = GND 4.05 4.10 4.15 OVS1 = GND, OVS0 = VCC 4.15 4.20 4.25 OVS1 = VCC, OVS0 = GND 4.35 4.40 4.45 Overvoltage Detect V OV OVS1 = VCC, OVS0 = VCC 4.45 4.50 4.55 V Charge-Enable Voltage V CE VOVMIN - 0.15 VOVMAX - 0.15 V Charge-Balance Voltage V BAL VBAL lowest typical set point limited to 3.75V VOVMIN - Cell- Balancing Threshold VOVMAX - Cell- Balancing Threshold V Undervoltage Release V UVREL 2.7 2.8 2.9 V Undervoltage Detect V UV 2.2 2.3 2.4 V RDOC, RSC Output Current V VIN - VRDOC = VVIN - VRSC = 2V 0.95 1.00 1.05 μA RDOC, RSC Input Offset Voltage -3 +3 mV
5- to 10-Cell Li+ Protector with Cell Balancing Note 1: All voltages relative to GND. Note 2: Voltages below this level cannot be monitored; therefore, CC and DC are off below this value. Note 3: Full-gate drive is not achieved until the voltage source for the gate driver (VPKP or VVIN) is above 13V. Note 4: With 10µF decoupling capacitor. Note 5: ILOAD is the current load on the pin specified in the parameter. Note 6: VCC cannot meet specification if VVIN is below this value. Note 7: Capacitance tolerance introduces additional error. Note 8: With ≥ 0.1µF decoupling capacitor. Note 9: Current is an average. Spikes up to 200µA when measuring cell voltages. Note 10: Current is an average. Spikes up to 15µA when measuring cell voltages. Note 11: Current depends on the number of cells being balanced. Note 12: Includes switching time and comparator delay with 25mV overdrive. ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUIT (continued) (TA = 0°C to +50°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Overvoltage Delay t OVD 128 x tDOCDMIN 128 x tDOCDMAX ms Undervoltage Delay t UVD 128 x tDOCDMIN 128 x tDOCDMAX ms ms CSCD = 100pF (Notes 7, 12) 45 58 72 Short-Circuit Delay t SCD CSCD = 1000pF (Notes 7, 12) 405 508 612 μs Charger-Detect Threshold (VPKP - VVIN) VCDET 3 17 mV Test Threshold V TP DOC conditions 0.8 1.2 1.7 V DOC condition, VIN - VPKP = 2V 68 120 200 μA Test Current I TST DOC condition, VIN - VPKP = 50V 0.5 1.20 1.8 mA
5- to 10-Cell Li+ Protector with Cell Balancing Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) OV ACCURACY vs. TEMPERATURE DS2726 toc01 TEMPERATURE (°C) OV ACCURACY (V) 603510-15 -0.007 -0.005 -0.003 -0.001 0.001 0.003 0.005 0.007 0.009 -0.009 -40 85 UV ACCURACY vs. TEMPERATURE DS2726 toc02 TEMPERATURE (°C) UV ACCURACY (V) 6035-15 10 0.002 0.004 0.006 0.008 0.012 0.010 0.014 -40 85 TEST CURRENT vs. (VVIN - VPKP) DS2726 toc03 (VVIN - VPKP) (V) ITST (mA) 5040302010 0.2 0.4 0.6 0.8 1.0 1.2 06 0 VTP = 1.16V DISCHARGE OVERCURRENT DELAY (CDOCD = 1000pF, RDOC = 110kΩ WITH RDS_ON = 2.75kΩ) TIME (ms) VGS DISCHARGE FET (V) LOAD CURRENT (A) 40302010 -11 -10 05 0 DS2726 toc04 DOC CONDITION VGS DISCHARGE FET DISCHARGE OVERCURRENT THRESHOLD LOAD CURRENT SHORT-CIRCUIT DELAY (CDOCD = 1000pF, RSC = 247.5kΩ WITH RDS_ON = 2.75MΩ) TIME (μs) 10050 -11 VGS DISCHARGE FET (V) LOAD CURRENT (A) 100 120 DS2726 toc05 LOAD CURRENT SHORT-CIRCUIT CONDITION SHORT-CIRCUIT THRESHOLD VGS DISCHARGE FET FET TURN-OFF TIME (WITH 460nC TOTAL GATE CHARGE) DS2726 toc06 20μs/div 5V/div 18016020 40 60 120 10080 140 200
Figure 1. Block Diagram
5- to 10-Cell Li+ Protector with Cell Balancing Pin Description PIN NAME FUNCTION 1 RSC Short-Circuit Voltage Threshold. The resistor from this pin to the positive terminal of the cell stack selects the threshold voltage for a short-circuit condition in the discharge direction. 2 RDOC Discharge Overcurrent Voltage Threshold. The resistor from this pin to the positive terminal of the cell stack selects the threshold voltage for an overcurrent condition in the discharge direction.
3 V CC
Regulator Supply Output. VCC supplies power to internal circuits and can be used to pull configuration pins to V IH. It should be bypassed to GND with at least a 0.1μF ceramic capacitor. 4, 5 SEL0, SEL1 Select Number of Cells in the Battery Stack. This input is a three-level input. Connect to ground or V CC for a logic-low or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 2 for how to drive this pin for a particular number of cells. 6 CDOCD Discharge Overcurrent Delay Time. Connect a capacitor from this pin to GND to select the amount of time for which a discharge overcurrent condition must persist before shutting off the DC FET.
7 SLEEP
Sleep-Mode Select Input. Driving this pin to a logic-low level forces the part into the lowest power state. The part exits Sleep Mode once a charge voltage is applied. When CBCFG is high, a logic-high on this pin enables cell balancing. 8 CSCD Short-Circuit Current Delay Time. Connect a capacitor from this pin to GND to select the amount of time for which a short-circuit current condition must persist before shutting off the DC FET.
9 CBCFG
Charge-Balance Configuration Input. When this pin is at a logic-low, charge balancing is enabled if VPKP > VVIN + VCDET. When this pin is at a logic-high, charge bal ancing is enabled if the SLEEP pin is at a logic-high. 10, 11 CBS0, CBS1 Select Cell-Balancing Voltage. This input is a three-level input. Connect to gr ound or VCC for a logic-low or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 4 for how to drive this pin for a particular cell-balancing voltage threshold. 12, 13 OVS0, OVS1 Select Overvoltage Threshold. This input is a three-level input. Connect to ground or V CC for a logic-low or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 3 for how to drive this pin for a particular overvoltage threshold. 14, 30 N.C. No Connection. Not internally connected. 15 GND Ground. Connect to the negative terminal of the lowest voltage cell. 16 V00 Negative Terminal Voltage Sense. Connect to the negative terminal of the 1st cell in the battery stack. 17 V01 Cell 01 Voltage Sense. Connect to the positive terminal of the 1st cell in the battery stack. 18 V02 Cell 02 Voltage Sense. Connect to the positive terminal of the 2nd cell in the battery stack. 19 V03 Cell 03 Voltage Sense. Connect to the positive terminal of the 3rd cell inf the battery stack. 20 V04 Cell 04 Voltage Sense. Connect to the positive terminal of the 4th cell in the battery stack. 21 V05 Cell 05 Voltage Sense. Connect to the positive terminal of the 5th cell in the battery stack. 22 V06 Cell 06 Voltage Sense. Connect to the positive terminal of the 6th cell in the battery stack. 23 V07 Cell 07 Voltage Sense. Connect to the positive terminal of the 7th cell in the battery stack. 24 V08 Cell 08 Voltage Sense. Connect to the positive terminal of the 8th cell in the battery stack. 25 V09 Cell 09 Voltage Sense. Connect to the positive terminal of the 9th cell in the battery stack. 26 V10 Cell 10 Voltage Sense. Connect to the positive terminal of the 10th cell in the battery stack.
27 V IN Connect to the Most Positive Cell Terminal
28 DC Discharge Control Output. DC controls the gate of the discharge FET. Driven from V IN to VOLDC to turn on and turn off the discharge FET.
detecting short-circuit and discharge overcurrent conditions. 32 PKP Pack Positive. The voltage on PKP is used to detect charger-attach and protection-release conditions. — EP Exposed Pad Ground. Connect to the negative terminal of the lowest voltage potential cell. Figure 2. Typical Application Circuit
olds and delays are component programmable. FETs to the appropriate state. there is a pulldown current from PKP to GND. when the SLEEP pin is driven to a logic-high state. Table 1. Li+ Protection Conditions and DS2726 Responses *All voltages are with respect to GND. CC Off: VCC = VPKP, DC Off: VDC = VVIN. Note 13: The DC FET remains off until VCELL > VUV_REL. Note 14: With test current ITST flowing from VIN to PKP. Note 15: If a DOC condition persists indefinitely and a UV condition is reached, the IC does not enter Sleep Mode.
current is flowing through the body diode of the DC FET. not disabled if an undervoltage condition is reached. Figure 3. Li+ Protection Circuitry Example Waveforms
the SEL0 and SEL1 pins according to Table 2. 7th cell, and so on (see Figure 4).
9 CELLS
8 CELLS
7 CELLS
6 CELLS
5 CELLS
Figure 4. Cell Bypassing Connection Table 2. Number of Cells Configuration Note: The DC FET remains off until VCELL > VUV_REL.
using the OVS0 and OVS1 pins according to Table 3. voltage must exist for cell balancing to occur. ured using the CBS0 and CBS1 pins according to Table 4. ancing voltage is never allowed a value below 3.75V. damaging the internal cell-balancing FETs. The DS2726 has three distinct states during balancing. Table 3. OV Threshold Configuration Table 4. Cell-Balancing Threshold Configuration
5- to 10-Cell Li+ Protector with Cell Balancing Setting the Short-Circuit Threshold and Delay Time The DS2726 allows the selection of a short-circuit cur- rent threshold. This threshold is set using a resistor from the RSC pin to the positive terminal of the cell stack. The RSC pin sinks 1µA (nominal). The short-cir- cuit comparator triggers when the voltage on the SNS pin is less than the voltage on the RSC pin. For exam- ple, assume a 500k Ω resistor is used on RSC, along with a DC FET with an R DS_ON of 10m Ω. This corre- sponds to an RSC voltage of 500k Ω x 1µA = 0.5V. Because the FET is 10m Ω, the short-circuit threshold is 0.5V/10mΩ = 50A: The DS2726 allows for a delayed reaction to a short-cir- cuit event. The short threshold must persist for the entire delay time before the DC FET begins to turn off (actual turn-off time varies based on the gate capaci- tance of the DC FET; see the DC pin drive capabilities in the details). The short-circuit delay time is set using a capacitor on the CSCD pin. The short-circuit delay time can be calculated by the equation: t SCD = CSCD x 500kΩ Be sure to select threshold and delay times that fall within the safe operating area of the FETs chosen for DC and CC. Setting the Discharge Overcurrent Threshold and Delay Time The DS2726 allows the selection of a discharge over- current threshold. This threshold is set using a resistor from the RDOC pin to the positive terminal of the cell stack. The RDOC pin sinks 1µA (nominal). The overcur- rent circuit comparator triggers when the voltage on the SNS pin is less than the voltage on the RDOC pin. For example, assume a 200k Ω resistor is used on RDOC, along with a DC FET with an R DS_ON of 10m Ω. This corresponds to a voltage on RDOC of 200k Ω x 1µA = 0.2V. Because the FET is 10mΩ, the discharge overcur- rent threshold is 0.2V/10mΩ = 20A: The DS2726 allows for a delayed reaction to a dis- charge overcurrent event. The discharge overcurrent threshold must persist for the entire delay time before the DC FET begins to turn off (actual turn-off time varies based on the gate capacitance of the DC FET; see DC pin drive capabilities in the Characteristics table for more details). The discharge overcurrent delay time is set using a capacitor on the CDOCD pin. The discharge overcurrent delay can be calculated by the equation: t DOCD = CDOCD x 32MΩ Be sure to select threshold and delay times that fall within the safe operating area for the FETs chosen for DC and CC. If the voltage on the CDOCD pin is within approximately 1V of V CC or GND, the condition is considered to be a fault, and the CC and DC outputs are disabled. This results in a delay before enabling the FETs when the part awakens from Sleep Mode. This delay occurs until the voltage on CDOCD reaches an acceptable level. This is a function of the capacitor on CDOCD. The CDOCD startup delay is in addition to a typical regulator startup of 100µs, and is given by the equation: STARTUP DELAY ≈ 100µs + C DOCD x 1.65MΩ Be sure to select threshold and delay times that fall within the safe operating area for the FETs chosen for DC and CC. I µA R RDOC DOC DS ON = ×1 I µA RSC RSC DS ON = ×1
DOCD. Figure 5 illustrates the measurement sequence. Figure 5. Cell Balancing and Measurement Periods
5- to 10-Cell Li+ Protector with Cell Balancing Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. DS2726 TQFN (7mm × 7mm) TOP VIEW RDOC SEL0 SEL1 CDOCD SLEEP RSC V07 V05 V04 V08 V03 V02 DC 4567 2324 22 20 19 18 SNS N.C. N.C. OVS1 OVS0 CBS1 VCC V06 31 10CC CBS0*EP *EXPOSED PAD. 32 9PKP CBCFG VIN 26 15 GNDV10 25 16 V00 CSCD V01 V09 Pin Configuration Package Information For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.