DS2722-F-03

ML2722 MICRO-LINEAR | Alldatasheet

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900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet DS2722-F-05 DECEMBER 2003 GENERAL DESCRIPTION The ML2722 is a fully integrated 1.5Mbps frequency shift keyed (FSK) transceiver that operates in the unlicensed 900MHz ISM frequency band. The device has been optimized for digital cordless telephone applications and includes all the f requency generation, receive and transmit functions. Automatically adjusted filters eliminate mechanical tuning. The transmitter generates a -1 dBm FSK output signal. The single conversion Low -IF receiver has all the sensitivity and selectively advantages of a traditional super - heterodyne without requiring costly, bulky external filters, while providing the integration advantages of direct conversion. The phase locked loop (PLL) synthesizer is completely integrated, including the voltage controlled oscillat or (VCO), tuning circuits, and VCO resonator. This allows the ML2722 to be used in frequency hopped spread spectrum (FHSS) applications. The ML2722 contains internal voltage regulation. It also contains PLL and transmitter configuration registers. The device can be placed in a low power standby mode for current sensitive applications. It is packaged in a 32TQFP. PIN CONFIGURATION VCC5 TRFO RVCC4 RRFI GND GND GND GND 8 9 101 11 21 31 41 51 6 32 31 30 29 28 27 26 25 XCEN RXON PAON EN DATA CLK TPC/TPQ VSS REF RVCC1 QPO GND VCC2 RVCC3 VTUNE GND DOUT VDD DIN RVCC7 RSSI/TPI RVCC6 VBG GND

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE PUBLICATION ML2722DH -10oC to +60 oC 32 Pin TQFP 7mm body DS2722-F-05

FEATURES

§ Single chip ISM band 900MHz Radio Transceiver with -1 dBm transmit output power § 1.5Mbps maximum data rate § Typical receiver sensitivity: -95dBm at 12.5% CER § Fully integrated frequency synthesizer with internal VCO resonator § Automatic filter calibration: Requires no mechanical tuning adjustments during manufacturing § Low IF Receiver: No external IF filters required § Control outputs correctly sequence and control external PA § 3-wire control interface § Analog RSSI output

APPLICATIONS

§ 900MHz FSK Data Transceivers - Digital Cordless Phones - Wireless Streaming Media - Wireless PC Peripherals BLOCK DIAGRAM

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 2 TABLE OF CONTENTS CHANGE LOG VERSION DATE AUTHOR CHANGES/COMMENTS DS2722-F-03 9/26/03 Derby Reformatted and updated from F02 DS2722-F-04 10/13/03 Derby Error on Page 21 Table 5 – Divide Ratio = fc / 0.512 DS2722-F-05 12/12/03 Derby Some graphics printed poorly to PDF.

Figure 1. Simplified Application Diagram

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 4

ELECTRICAL CHARACTERISTICS

Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. OPERATING CONDITIONS Unless otherwise specified, VCC5 & VDD = 2.7V to 3.8V, T A = Operating Temperature Range (Note 1) 6.144 or 12.288MHz reference frequency input PARAMETER CONDITIONS MIN TYP MAX UNITS POWER CONSUMPTION ISTBY All Circuits, Standby Mode 10 100 µA IRX, ITX Receive or Transmit Mode TA = 25°C, VCC5 & VDD = 3.3V 30 50 63.5 mA IRX, ITX Receive or Transmit Mode TA = Operating Temperature Range 20 50 70 mA SYNTHESIZER fC LO output frequency In 512 KHz steps 902 928 MHz Φ N Phase noise at driver output

1.2 MHz

3 MHz

7 MHz VCO phase locked, loop bandwidth 50KHz. Discontinuities, other than reference spurs, not allowed. -100 -120 -125 dBc/Hz fREF LO PLL reference frequency at phase detector PLL main divider input is at 1.83 GHz 1.024 MHz N LO division range integer PLL divider limits 1024 4093 Count IP LO charge pump sink/source current 5.5 mA tTX2RX LO lock up time for Transmit/Receive frequency change From RXON asserted 50 µs tFH LO lock up time for channel switch From EN asserted, any channel change in 902 to 928 MHz band 100 µs tWAKE LO lock up time from sleep From XCEN, PLL dividers programmed 240 µs VFREF Reference signal input level 6.144 or 12.288MHz sine wave, capacitively coupled 2.0 3.0 Vp-p

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 5 RECEIVER ZIN Receiver RF impedance fc=915 MHz 17-j50 Ω NF Receiver RF noise figure fc=915 MHz 9 dB DRRX Data Rate FSK modulation, fdev=+/-460KHz 1.536 Mbps S Input Sensitivity For better than 12.5% CER -95 dBm BWRX Bandwidth 3dB nominal 770 kHz PIMAX Maximum RX RF input <12.5% CER at 1.536Mchip/s 8 dBm IIP3 Receiver input IP3 Test tones 2 and 4 channels away -12 dBm LO Leakage at RXI -80 dBm IRR Receive RF mixer image rejection Measured at 3.5MHz offset 35 dB Adjacent channel rejection -80dBm wanted signal <12.5% CER (a single interferer with 2GFSK modulation to give a -20dBc bandwidth of 1.5MHz) 1 channel 2 channels 3 or more channels dB Receiver settling time RXON high to valid data 120 µs IF FILTERS fIFC IF filter center frequency After Automatic Filter Alignment 1.024 MHz BWIF IF filter 3dB bandwidth After Automatic Filter Alignment 1405 kHz LIMITER, AGC, AND FM DEMODULATOR tOVLD Recovery from overload From 0dBm at input 5 12 µs Eb/No For 12.5% CER 3 dB Co-Channel rejection, 12.5% CER -80 dBm, modulated with 1.536Mbps GFSK, BT=0.5, PRBS data 4 dB AM tolerance for 12.5% or better CER -80 dBm wanted signal, AM modulation depth at 100 KHz rate 90 % RSSI PERFORMANCE tRRSSI RSSI rise time: < -100dBm to -15dBm into the IF mixer 20 pF load, 20% to 80% 1 5.3 10 µs tFRSSI RSSI fall time: <-15dBm to <-100dBm into the IF mixer 20 pF load, 20% to 80% 1 4.4 10 µs VRSMX RSSI maximum voltage -15dBm in 2.2 2.8 V VRSMN RSSI minimum voltage No signal 0.05 V GRSMID RSSI sensitivity, mid range 28 35 42 mV/dB PRSMX RSSI maximum signal Sensitivity is >50% mid range -20 dBm PRSMN RSSI minimum signal Sensitivity is >50% mid range -95 dBm RSSI accuracy Measured at -40dBm input power 1.5 1.9 2.1 V

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 6 TRANSMIT RF BUFFER POUT Driver amplifier output power When matched into 50Ω -4.5 -1.0 +2.0 dBm Driver amplifier output return loss 902 to 928 MHz 14 dB TRANSMIT MODULATION fDEV Modulation Deviation, internal VCO 5 consecutive 1 or 0 bits 400 460 560 kHz fOS Modulation center frequency offset Between 50 µs and 10 ms after PAON high -100 +100 kHz TRANSMIT DATA FILTER BWTX Transmit data filter bandwidth 3dB Bandwidth 1.4 MHz INTERFACE LOGIC LEVELS VIH Input high voltage never exceed VDD 0.75 * VDD VDD V VIL Input low voltage 0.25 * VDD V IB Input bias current -5 0 5 µA CIN Input capacitance measured at 1MHz 4 6 pF VOH DOUT high voltage Sourcing 0.1 mA Typical value assumes 3.3V VDD VDD - 0.6 3.08 V VOL DOUT low voltage Sinking 0.1 mA 0.18 0.6 V INTERFACE TIMING tRX2PA RX to TX switching time Time from RXON low to PAON high 62.5 70 µs tTX2EN TX to RX switching time Time from RXON high to receiver enabled 72 80 µs tRXEN Channel switching time Time from write to PLL tuning register (EN high) to receiver enabled 320 342 µs tXCEN Chip enable time From XCEN high to receiver enabled with continuous reference applied 320 342 µs Note 1: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 7 PIN DESCRIPTIONS PIN SIGNAL NAME I/O FUNCTION DIAGRAM POWER & GROUND

8 VSS I (digital) Ground for digital I/O circuits and control

logic.

10 RVCC1 O (analog) DC power supply decoupling point for the

PLL dividers, phase detector, and charge pump. This pin is connected to the output of the regulator and to the PLL supplies. There must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator.

12 GND I (analog) Ground for the PLL dividers, phase

detector, and charge pump.

13 VCC2 I (analog) DC Power Supply Input to the VCO

voltage regulator. Must be connected to RVCC6 (pin 27) or RVCC7 (pin 29) via decoupling network.

14 RVCC3 O (analog) DC power supply decoupling point for the

VCO. Connected to the output of the VCO regulator. A capacitor must be tied between this pin and ground to decouple (bypass) noise and to stabilize the regulator. 16 GND I (analog) DC ground for VCO and LO circuits.

17 GND I (analog) Signal ground for RF small signal

circuits. Pins 17, 18, and 19 should have short, direct connections to each other and additional connections to ground. 18 GND I (analog) Ground return for the Receive RF input. 19 GND I (analog) Signal ground for the Receive mixers.

20 GND I (analog) DC and Signal ground for the Transmit

RF Output buffer.

22 RVCC4 O (analog) DC power supply decoupling point for the

LO chain. Connected to the output of a regulator. There must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator.

24 VCC5 I (analog) DC power supply input to voltage

Regulators and unregulated loads. VCC5 is the main (or master) analog VCC pin. There must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator.

25 GND I (analog) DC ground to IF, Demodulator, and Data

Slicer circuits.

27 RVCC6 O (analog) DC power supply decoupling point for

Quadrature Mixer and IF filter circuits. A capacitor must be tied between this pin and ground to decouple (bypass) noise

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 8 PIN SIGNAL NAME I/O FUNCTION DIAGRAM and to stabilize the regulator.

29 RVCC7 O (analog) DC power supply decoupling point for IF,

Demodulator, and Data Slicer circuits. A capacitor must be tied between this pin and ground to decouple (bypass) noise and to stabilize the regulator.

31 VDD I (digital) DC power supply input to the interface

logic and control registers. This supply is not connected internally to any other supply pin, but its voltage must be less than or equal to the VCC5 supply and greater than 2.7 V. A capacitor must be tied between this pin and ground to decouple (bypass) noise. TRANSMIT/RECEIVE 21 RRFI I (analog) Receive RF Input. Nominal impedance at 902 to 928 MHz is 17-50j Ω with a simple matching network required for optimum noise figure. This input is to the base of an NPN transistor and should be AC coupled. (PIN 24) (PIN 8) VSS GND RRFI VCC5 0.7V VCC5 VSS

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 9 PIN SIGNAL NAME I/O FUNCTION DIAGRAM 23 TRFO O (analog) Transmit RF Output. This output is an emitter follower and should be AC coupled. VCC5 12mA TRFO VSS Ω DATA 30 DIN I (CMOS) Transmit Data Input. Drives the transmit pulse shaping circuits. Serial digital data on this pin becomes FSK modulation on the Transmit RF output. The logic timing on this pin controls data timing. Internal circuits determine the modulation deviation. This is a standard CMOS input referenced to VDD and VSS. VSS XCEN VDD RXON DIN

32 DOUT O (CMOS) Serial digital output after demodulation,

chip rate filtering and center data slicing. A CMOS level output (VSS to VDD) with controlled slew rates. A low drive output designed to drive a PCB trace and a CMOS logic input while generating minimal RFI. In digital test modes this pin becomes a test access port controlled by the serial control bus. VSS VDD 250 Ω

32 DOUT

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 10 PIN SIGNAL NAME I/O FUNCTION DIAGRAM MODE CONTROL AND INTERFACE LINES

1 XCEN I (CMOS) Enables the bandgap reference and

voltage regulators when high. With XCEN low the device consumes only leakage current in STANDBY mode when low. XCEN low also preserves register contents and allows register writes. This is a CMOS input, and the thresholds are referenced to VDD and VSS. VSS XCEN VDD RXON DIN

2 RXON I (CMOS) Switches the transceiver between

TRANSMIT and RECEIVE modes. Circuits are powered up and signal paths reconfigured according to the operating mode. This is a CMOS input, and the thresholds are referenced to VDD and VSS. VSS XCEN VDD RXON DIN

3 PAON O (CMOS) Enables the off-chip PA at the correct

times in a Transmit slot. Goes high when transmit RF is present at TRFO; goes low 5µs before transmit RF is removed from TRFO. Has interlock logic to shut down the PA if the PLL does not lock. VSS VDD

3 PAON

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 11 PIN SIGNAL NAME I/O FUNCTION DIAGRAM

7 TPC/TPQ O (open

drain) Transmit power control output. This open-drain output is pulled low when the TPC bit in serial register #0 is set. Transitions on TPC are synchronized to the falling edge of RXON. In analog test modes, this pin and the RSSI output become test access points controlled by the serial control bus. VSS VDD 100

7 TPC/TPQ

Ω 9 REF I Input for the 12.288 MHz or 6.144 MHz reference frequency. This input is used as the reference frequency for the PLL and as a calibration frequency for the on- chip filters. This is a self-biased CMOS input that is designed to be driven either by an AC-coupled sine wave. VSS REF VCC5 40k 40k

11 QPO O Charge Pump Output of the phase

detector. This is connected to the external PLL loop filter. VSS R VCC1

11 QPO

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 12 PIN SIGNAL NAME I/O FUNCTION DIAGRAM

15 VTUNE I VCO Tuning Voltage input from the PLL

loop filter. This pin is very sensitive to noise coupling and leakage currents. 26 VBG O Internal Bandgap Reference Voltage. Decoupled to ground with a 220nF capacitor.

28 RSSI/TPI O Buffered Analog RSSI output with a

nominal sensitivity of 35mV/dB. An RF input signal range of – 95 to – 20 dBm gives an RSSI voltage output of zero to 2.7 V. VSS VCC5 100 Ω

28 RSSI/TPI

4 EN I (CMOS) Enable pin for the three-wire serial

control bus that sets the operating frequency and programmable options. The control registers are loaded on a low-to-high transition of the signal. Serial control bus data is ignored when this signal is high. This is a CMOS input, and the thresholds are referenced to VDD and VSS. 5 DATA I (CMOS) Serial Control Bus Data. 16-bit words, which include programming data and the two-bit address of a control register. This is a CMOS input, and the thresholds are referenced to VDD and VSS.

6 CLK I (CMOS) Serial control bus data is clocked in on

the rising edge when EN is low. This is a CMOS input; the thresholds are referenced to VDD and VSS. VSS VDD 5.5k 4EN 1.7p5DATA 6CLK VSS VCC2 3.7k 15VTUNE 1.25V VSS VCC2 3.7k 15VTUNE 1.25V

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 13 FUNCTIONAL DESCRIPTION The ML2722 enables the design and manufacture of low -cost, high-performance FSK transceivers. It can also be used as a 900MHz digital cordless telephone transceiver. Integral to the ML2722 is a low -IF receiver whose LO port is driven from an internal synthesizer. Included are image rejection IF filters, limiters, discriminator, data slicers, and baseband low-pass data filters. It also contains internal voltage regulators to protect critical circuits from power su pply noise and transmit modulation circuits. The ML2722 is designed to transmit and receive 1.536M chips per second in 2.048MHz spaced channels in the 902 to 928MHz ISM band. A single synthesizer is used for both the receiver and the FSK transmitter. The phase locked loop (PLL) is completely integrated, including the voltage controlled oscillator (VCO), tuning circuits, and VCO resonator. The ML2722 has an internal control interface that programs the synthesizer, the mode of operation, the external LNA and PA, and provides a convenient and flexible interface to various baseband processors. For power level monitoring an RSSI block is included. In RECEIVE MODE, the ML2722 is a single conversion low IF receiver. The demodulation is followed by a matched bit rate filter and a data slicer. The sliced data is provided to a baseband chip for despreading. All channel filtering and demodulation is performed using active filters, which are automatically aligned. A matched bit rate filter and a data slicer follow the demodulator. The sliced data is provided at the DOUT pin. In TRANSMIT MODE , the ML2722 uses the Receive mode VCO and frequency division, with a driver amplifier providing typically -1 dBm output to feed the power amplifier. The PLL frequency synthesizer l oop is opened during the transmit time slot, and the VCO is directly modulated by low-pass filtered circuits from the internal modulation filter. The ML2722 uses multiple voltage regulators to protect sensitive internal circuits from power supply noise. Se parate regulators supply the PLL dividers, RF circuits and IF circuits. Each of these regulators takes its power from VCC5, and supplies power internally to its respective RVCCn pin. External capacitors are required at each RVCCn pin to decouple the output s of the internal regulators. The VCO regulator takes its power from the VCC2 pin which is normally connected to the RVCC6 (pin 27) or RVCC7 (pin 29). An external decoupling capacitor is also used on the internal bandgap voltage reference to improve the noise performance of the regulators. The integrated PLL frequency synthesizer includes a fully integrated VCO, prescaler, phase detector and charge pump. The reference frequency is generated from the incoming signal at the REF pin, which can be either 6.1 44MHz or 12.288MHz. The loop filter is external to allow customers to optimize their loop bandwidth to their system’s lock time and in-band phase noise requirements. This frequency -agile synthesizer allows the ML2722 to be used in frequency hopped spread spectrum (FHSS) applications with nominal channel spacing of 2.048MHz. Carrier frequency is programmed via the configuration registers and 3 -wire serial interface. The VCO tank circuit (inductor and varactor) is fully integrated. Example 38KHz Loop Filter 2.2nF 470Ω 22nF RVCC3 QPO VTUNE

23 TRFO

1 XCEN

2 RXON

30 DIN

5 DATA

6 CLK

9 REF

21 RRFI

24 VCC5 DC

26 VBG

Figure 2. ML2722 Block Diagram

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 15 MODES OF OPERATION OVERVIEW § STANDBY: All circuits powered down, except the control interface (Static CMOS) § RECEIVE: Receiver circuits active § TRANSMIT: PLL open loop, modulated RF output available from the IC The two operational modes are RECEIVE and TRANSMIT. They are set by the RXON control (pin 2). XCEN (pin 1) is the chip enable/disable and can be set for standby operation. The relationship betwee n the parallel control lines and the mode of operation of the IC is given in Table 1. XCEN RXON MODE TRANSCEIVER MODE

0 X STANDBY Control interfaces active, all other circuits powered down

1 1 RECEIVE Receiver time slot 1 0 TRANSMIT Transmit time slot Table 1: Modes of Operation MODE CONTROL The ML2722 is intended for use in TDD and TDMA radios in battery -powered equipment. To minimize power consumption it is designed to switch rapidly from a low power m ode (STANDBY) to receive or transmit. The ML2722 can also make a quick transition from receive to transmit for TDD operation. Prior to transmitting or receiving, time should be allowed for the PLL to lock up and for the filters to be aligned. When the ML27 22 is operated in single-carrier TDD mode, the LO is automatically shifted by the second (low) IF frequency when the device is switched between RECEIVE and TRANSMIT modes. ML2722 carrier frequency can be changed (hopped) between transmissions. Carrier freq uency (channel) is modified in the ML2722 by writing a corresponding new value to the PLL frequency register. RECEIVE The ML2722 uses a single -conversion heterodyne receiver with a nominal IF of 1.024MHz. The signal flow in RECEIVE mode is from the RF inpu t, through an image reject quadrature mixer, limiter, frequency -to-voltage converter, data filter, and data slicer where the digital NRZ data is available at the DOUT pin. A 20dB step AGC extends the dynamic range of the receiver. The ML2722 receive chain is a Low IF receiver using advanced integrated radio techniques to eliminate external IF filters and minimize external RF filter requirements. The precision filtering and demodulation circuits give improved performance over conventional radio design using external filters while providing integration comparable to advanced direct conversion radio designs.

be used to determine if a given channel is occupied (see Figure 3). Figure 3. Typical RSSI Response does not introduce significant ISI (Inter Symbol Interference). unwanted spurious emissions.

reflected back into the output TRFO (pin 23), be less than – 30dBm. Table 2. Non-Overlapping Channel Frequencies operation is independent of the mode of operation of the PLL. registers are reset at power up. debugging. A test register, available via the 3-wire serial interface, controls the test multiplexers.

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 18 CONTROL INTERFACES There are two control interfaces: PARALLEL and SERIAL. PARALLEL INTERFACE The parallel interface provides immediate control and monitoring of the ML2722. Input signals include: § XCEN: Transceiver enable. Places the ML2722 in Standby or Active (when asserted) modes. § RXON: Receive On. Places an Active ML2722 in Receive mode when asserted. § REF: Reference frequency input Output signals include: § RSSI: Received Signal Strength Indicator: indicates the power of the received signal § PAON: External Power Amplifier Control Pin SERIAL INTERFACE A 3-wire serial interface (EN, DAT A, CLK) is used for programming the ML2722 configuration registers, which control device mode, pin functions, PLL and reference dividers, internal test modes, and filter alignment. Data words are entered beginning with the MSB (“big -endian”). The word is d ivided into a leading 14 -bit data field followed by a 2 -bit address field. When the address field has been decoded the destination register is loaded on the rising edge of EN. Providing less than 16 bits of data will result in unpredictable behavior when EN goes high. Data and clock signals are ignored when EN is high. When EN is low, data on the DATA pin is clocked into a shift register by rising edges on the CLK pin. The information is latched when EN goes high. This serial interface bus is similar to tha t commonly found on PLL devices. The data latches are implemented in static CMOS and use minimal power when the bus is inactive. Table 3 and Figure 4 provide timing and register programming illustrations.

Table 3. 3-Wire Bus Timing Characteristics Figure 4. Serial Bus Timing for Address and Data Programming

Table 4. Register 0 -- PLL Configuration Register Table 5. Register 1 – Channel Frequency Register

Table 6. Register 2 – Test Mode Register be programmed before XCEN is asserted for the first time. specified register. Loading less than 16 bits into any register will cause unpredictable device functionality.

0 Frequency signal < frequency reference. Charge pump sources current. 1 Frequency signal < frequency reference. Charge pump sinks current. Table 7. PLL Charge Pump Polarity This bit sets the reference division of the PLL to either 6 or 12 (see Table 8). Table 8. Reference Frequency Select This bit is used in Receive mode to put the PLL into either open loop or closed loop (see Table 9).

0 PLL open loop

1 PLL closed loop

Table 9. PLL Mode in Normal Receive Operation LO shift for transmit and receive. For normal operations, it is recommended that LOL = 0 (see Table 10). Table 10. PLL Frequency Shift

Used to produce a continuous CW transmitter output for product test with RXON low (see Table 11).

0 PLL Open Loop, FSK Output

1 PLL Closed Loop, CW Output

Table 11. PLL Mode in Transmit Operation only changes state at the falling edge of RXON (see Table 12).

0 High Impedance

1 Pulled to Ground

Table 12. TPC Pin State Table 13. Main Divider

The test mode selected is described in Table 14. The performance of the ML2722 is not specified in these test modes. the transceiver. During normal operation, the ATM field should be set to zero. Table 14. Analog Test Control Bits field should be set to zero. Table 15. Digital Test Control Bits The DIN and DOUT CMOS logic levels are serial data that correspond to FSK modulated data on the radio channel. bit and word rate timing recovery performed in the baseband processor.

The Received Signal Strength Indicator (RSSI) pin supplies a voltage indicating the amplitude of the received RF signal. The ML2722 has two output pins to control and sequence the power amplifier – PAON and TPC (see Figure 6). Figure 6. Power Amplifier Interface will transmit in the next time slot following a transient fault condition. resistor network to set the output power level. to observe internal signals in the ML2722. plane, and the RF block supply pins must be well decoupled to the RF ground pins. Table 16. Typical Receive RF Input Table 17. Typical Transmit RF Output

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 27 PHYSICAL DIMENSIONS (INCHES/MILLIMETERS)

0.048 MAX

(1.20 MAX) SEATING PLANE

0.354 BSC

(9.00 BSC)

0.276 BSC

(7.00 BSC) (7.00 BSC) (9.00 BSC)

0.032 BSC

(0.8 BSC) PIN 1 ID 0.012 - 0.018 (0.29 - 0.45) 0.037 - 0.041 (0.95 - 1.05) 0.018 - 0.030 (0.45 - 0.75) 0.003 - 0.008 (0.09 - 0.20) 0 º - 8 º Package: H32-7 32-Pin (7 x 7 x 1mm) TQFP Leads cannot exceed 0.004 maximum coplanarity (0.102) PART NUMBER TEMPERATURE RANGE PACKAGE PUBLICATION ML2722DH – 10°C to 60°C 32 Pin TQFP 7mm body DS2722-F-04

DS2722-F-05 FINAL DATASHEET DECEMBER 2003 28 WARRANTY Micro Linear makes n o representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document. The circuits contained in this document are offered as possible applications only. Particular uses or applications may invalidate some of t he specifications and/or product descriptions contained herein. The customer is urged to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability whatsoever, and disclaims any express or implied warr anty, relating to sale and/or use of Micro Linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Micro Linear products are not designed for use i n medical, life saving, or life sustaining applications. If this document is “Advance”, its contents describe a Micro Linear product that is currently under development. All detailed specifications including pinouts and electrical specifications may be cha nged without notice. If this document is “Preliminary”, its contents are based on early silicon measurements. Typical data is representative of the product but is subject to change without notice. Pinout and mechanical dimensions are final. Preliminary doc uments supersede all Advance documents and all previous Preliminary versions. If this document is “Final”, its contents are based on a characterized product, and it is believed to be accurate at the time of publication. Final Data Sheets supersede all previously published versions. This document is Final. © 2003 Micro Linear Corporation. All rights reserved. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. paten ts: 4,897,611; 4,964,026; 2,704,176; 2,821,714. Other patents are pending. Micro Linear Corporation

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