DS2720AU

DS2720 MAXIM | Alldatasheet

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Technical content

FEATURES

/g167/g32Rechargeable Lithium-Ion (Li+) Safety Circuit - Overvoltage Protection - Overcurrent/Short-Circuit Protection - Undervoltage Protection - Overtemperature Protection /g167/g32Controls High-Side N-Channel Power MOSFETs Driven from 9V Charge Pump /g167/g32System Power Management and Control Feature Support /g167/g32Eight Bytes of Lockable EEPROM /g167/g32Dallas 1-Wire ® Interface with Unique 64-Bit Device Address /g167/g328-Pin /g32/g109SOP Package /g167/g32Low Power Consumption: - Active Current: 12.5 /g109A typ - Sleep Current: 1.5 /g109A typ PIN CONFIGURATION PIN DESCRIPTION PLS - Battery-Pack Positive Terminal Input PS - Power-Switch Sense Input DQ - Data Input/Output V SS - Device Ground VDD - Power-Supply Input CP - Reservoir Capacitor CC - Charge Control Output DC - Discharge Control Output

DESCRIPTION

The DS2720 single-cell rechargeable Li+ protection IC provides electronic safety functions required for rechargeable Li+ applications including protecting the battery during charge, protection of the circuit from damage during periods of excess current flow and maximization of battery life by limiting the level of cell depletion. Protection is facilitated by electronically disconnecting the charge and discharge conduction path with switching devices such as low-cost N-channel power MOSFETs. Since the DS2720 provides high-side drive to external N-channel protection MOSFETs from a 9V charge pump, superior on-resistance performance results compared to common low-side protector circuits using the same FETs. The FET on-resistance actually decreases as the battery discharges. Adding to the uniqueness of the DS2720 is the ability of the system to control the FETs from either the data interface or a dedicated input thereby eliminating the power-switch control redundancy of rechargeable Li+ battery systems. Through its 1-Wire interface, the DS2720 gives the host system read/write access to status and control registers, instrumentation registers, and general-purpose data storage. Each device has a factory- programmed 64-bit net address that allows it to be individually addressed by the host system. DS2720U /g109SOP PS

8 PLS

V SS VDD CC DC CP DS2720 Efficient, Addressable Single-Cell Rechargeable Lithium Protection IC www.maxim-ic.com 1-Wire is a registered trademark of Dallas Semiconductor.

Two types of user-memory are provided on the DS2720 for battery information storage: EEPROM and lockable EEPROM. EEPROM memory saves important battery data in true nonvolatile (NV) memory that is unaffected by severe battery depletion, accidental shorts, or ESD events. Lockable EEPROM becomes ROM when locked to provide additional security for unchanging battery data.

ORDERING INFORMATION

DS2720AU+ DS2720+ in 8-Lead /g109SOP in Bulk with VOVA = 4.275V DS2720AU+T&R DS2720+ in 8-Lead /g109SOP in Tape-and-Reel with VOVA = 4.275V DS2720BU+ DS2720+ in 8-Lead /g109SOP in Bulk with VOVB = 4.35V DS2720BU+T&R DS2720+ in 8-Lead /g109SOP in Tape-and-Reel with VOVB = 4.35V DS2720CU+ DS2720+ in 8-Lead /g109SOP in Bulk with VOVC = 4.30V DS2720CU+T&R DS2720+ in 8-Lead /g109SOP in Tape-and-Reel with VOVC = 4.30V DS2720AU DS2720 in 8-Lead /g109SOP in Bulk with VOVA = 4.275V DS2720AU/T&R DS2720 in 8-Lead /g109SOP in Tape-and-Reel with VOVA = 4.275V DS2720BU DS2720 in 8-Lead /g109SOP in Bulk with VOVB = 4.35V DS2720BU/T&R DS2720 in 8-Lead /g109SOP in Tape-and-Reel with VOVB = 4.35V DS2720CU DS2720 in 8-Lead /g109SOP in Bulk with VOVC = 4.30V DS2720CU/T&R DS2720 in 8-Lead /g109SOP in Tape-and-Reel with VOVC = 4.30V + Denotes lead-free package.

Figure 1. BLOCK DIAGRAM

Table 1. DETAILED PIN DESCRIPTION closure of a switch to VSS on this pin. PS has a high-impedance internal pullup. DATA terminal of the battery pack. DQ has an internal 0.5/g109A pull-down. VSS Device Ground. Connect directly to the negative terminal of the battery cell. Figure 2. APPLICATION EXAMPLE

mode, DS2720 resumes safety monitoring and conditionally turns on the protection FETs. Table 2. POWER MODE TRANSITION CONDITIONS (1) DS2720 does not transition to Active Mode if V DD < VSC. below and summarized in Table 3 and Figure 3. Table 3. PROTECTION CONDITIONS AND DS2720 RESPONSES All voltages are with respect to VSS. (1) During transition from sleep to active, tOVD = 0. RTST when recovery charge enabled. (3) With test current ITST flowing from VDD to PLS (pullup on PLS).

Overvoltage. If the cell voltage sensed at V DD exceeds overvoltage threshold V OV for a period longer than overvoltage delay t OVD, the DS2720 shuts off the external charge FET and sets the OV flag in the protection register. Discharging remains enabled during overvoltage. The charge FET is re-enabled (unless another protection condition prevents it), when the ce ll voltage falls below charge enable threshold V CE, or a discharge causes VDD - VPLS > VOC. Undervoltage. If the cell voltage sensed at V DD drops below undervoltage threshold V UV for a period longer than undervoltage delay t UVD, the DS2720 shuts off the charge and discharge FETs, sets the UV flag in the protection register, and enters sleep mode. The DS2720 turns on both the charge and discharge FETs after the cell voltage rises above V UV and a charger is present. Short Circuit. If the cell voltage sensed at V DD drops below depletion threshold V SC for a period of tSCD, the DS2720 shuts off the charge and discharge FETs and sets the DOC flag in the protection register. The current path through the charge and discharge FETs is not re-established until the voltage on PLS rises above V DD - VOC. The DS2720 provides a test current through internal resistor R TST from VDD to PLS to pull up PLS when V DD rises above V SC. The test current allows the DS27 20 to detect the removal of the offending low-impedance load. Additionally, a recovery charge path through R TST from PLS to V DD is enabled. Overcurrent. If the voltage across the protection FETs (V DD - V PLS) is greater than V OC for a period longer than tOCD, the DS2720 shuts off the external charge and discharge FETs and sets the DOC flag in the protection register. The current path is not re-established until the voltage on PLS rises above V DD - VOC. The DS2720 provides a test current through internal resistor R TST from V DD to PLS to detect the removal of the offending low-impedance load. Overtemperature. If the device temperature exceeds T MAX, the DS2720 immediately shuts off the external discharge and charge FETs. The FETs are not turned back on until the ce ll temperature drops below TMAX AND the host resets the OT bit.

Figure 3. Li+ PROTECTION CIRCUITRY EXAMPLE WAVEFORMS IOC = Current that produces a voltage drop across FETs equal to VOC threshold. short-circuit threshold, VSC.

The DS27xx family of products is organized into a 256-byte linear address space with registers for instrumentation, status, and control in the lower 32 bytes, with lockable EEPROM memory occupying portions of the remaining address space. All EEPROM memory is general purpose except address 31h, which should be written with the default values for the status register. EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow the data to be verified by the host system before being copied to EEPROM. All reads and writes to/from EEPROM memory in fact access the shadow RAM. In unlocked EEPROM blocks, the write data command updates shadow RAM. In locked EEPROM blocks, the write data command is ignored. The copy data command copies the contents of shadow RAM to EEPROM in an unlocked block of EEPROM but has no effect on locked blocks. The recall data command copies the contents of a block of EEPROM to shadow RAM regardless of whether the block is locked or not. Table 4. MEMORY MAP

00 Protection Register R/W

01 Status Register R

02–06 Reserved —

07 EEPROM Register R

08 Special Feature Register R/W

09–1F Reserved — 20–23 EEPROM, Block 0 R/W (1) 24–2F Reserved — 30–33 EEPROM, Block 1 (31 = Status Register Initialization) R/W (1) 34–FF Reserved — (1) Each EEPROM block is read/write until locked by th e LOCK command, after which it is read-only. PROTECTION REGISTER The protection register consists of flags that indi cate protection circuit status and switches that give conditional control over the charging and discharging paths. Bits OV, UV, and DOC are set when corresponding protection conditions occur and remain set until cleared by the host system. The format of the protection register is shown in Figure 4. The function of each bit is described in detail in the following paragraphs. Figure 4. PROTECTION REGISTER FORMAT

detect future events. The OV bit is a volatile R/W bit, initialized to 0 upon power-on-reset (POR). volatile R/W bit, initialized to 1 upon POR. OHCC). The CC bit is a 0 when the CC pin is driven low (VOLCC). OHDC). The DC bit is a 0 when the DC pin is driven low (VOLDC). from sleep mode to active mode. The CE bit is a volatile R/W bit, initialized to 1 upon POR. transitions from sleep mode to active mode. The DE bit is a volatile R/W bit, initialized to 1 upon POR. in detail in the following paragraphs. Figure 5. STATUS REGISTER FORMAT

BIT 5—This bit is read only. The value of this bit is set by bit 5 of address 31h and is factory set to 0. The value of address 31h bit 5 must not be changed. be set in bit 4 of address 31h. The factory default for RNAOP is 0. BIT 3—This bit is read only. The value of this bit is set by bit 3 of address 31h and is factory set to 0. The value of address 31h bit 3 must not be changed. in the following paragraphs. Figure 6. EEPROM REGISTER FORMAT EEC—EEPROM Copy Flag. A 1 in this read-only bit indicates that a copy data command is in progress. written to unlocked EEPROM blocks if the DS2720 is in the active mode of operation. bit is a volatile R/W bit, initialized to 0 upon POR. 30 to 33h) is locked (read-only) while a 0 indicates block 1 is unlocked (read/write). 20 to 23h) is locked (read-only) while a 0 indicates block 0 is unlocked (read/write).

detail in the following paragraphs. Figure 7. SPECIAL FEATURE REGISTER FORMAT to detect future events. This bit is initialized to a 1 upon POR. a volatile R/W bit, initialized to 0 upon POR. a low-impedance connection to VSS. Connecting PS to VSS wakes up the DS2720 if it was in sleep mode. If the DS2720 was in active mode, PS has no effect. 1-Wire Bus System section of this data sheet.

Figure 10. 1-WIRE BUS INTERFACE CIRCUITRY The sections that follow describe each of these steps in detail. RNAOP = 0 indicating 33h and RNAOP = 1 indicating 39h. one or more slave devices on the bus.

Skip Net Address [CCh]. This command saves time when there is only one 1-Wire device on the bus by allowing the bus master to issue a function command without specifying the address of the slave. If more than one slave device is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at the same time. Search Net Address [F0h]. This command allows the bus master to use a process of elimination to identify the 1-Wire net addresses of all slave devices on the bus. The search process involves the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple three-step routine on each bit location of the net address. After one complete pass through all 64 bits, the bus master knows the address of one device. The remaining devices can then be identified on additional iterations of the process. See Chapter 5 of the Book of DS19xx iButton® Standards for a comprehensive discussion of a net address search, including an actual example. Resume Command [A5H]. In a typical application the DS2720 can be accessed several times to complete control adjustment. To ma ximize data throughput in a multidrop environment, the resume command has been implemented. This function checks the status of an internal flag. If it is set, it directly transfers control in similar fashion to the skip net address command. The only way to set the internal flag is through successfully executing the match net address or search net address. Once the flag has been set, the device can be repeatedly accessed through the resume command. Accessing another device on the bus clears the flag, thus preventing two or more devices from simultaneously responding to the resume command function. FUNCTION COMMANDS After successfully completing one of the net address commands, the bus master can access the features of the DS2720 with any of the function commands described in the following paragraphs. The name of each function is followed by the 8-bit opcode for that command in square brackets. The function commands are summarized in Table 5. Read Data [69h, XX]. This command reads data from the DS2720 starting at memory address XX. The LSb of the data in address XX is available to be read immediately after the MSb of the address has been entered. Because the address is automatically incremented after the MSb of each byte is received, the LSb of the data at address XX + 1 is available to be read immediately after the MSb of the data at address XX. If the bus master continues to read beyond address FFh, data is read starting at memory address 00 and the address is automatically incremented until a reset pulse occurs. Addresses labeled “Reserved” in the memory map contain undefined data. The read data command can be terminated by the bus master with a reset pulse at any bit boundary. Write Data [6Ch, XX]. This command writes data to the DS2720 starting at memory address XX. The LSb of the data to be stored at address XX can be written immediately after the MSb of address has been entered. Because the address is automatically incremented after the MSb of each byte is written, the LSb to be stored at address XX + 1 can be written immedia tely after the MSb to be stored at address XX. If the bus master continues to write beyond address FFh, the data starting at address 00 is overwritten. Writes to read-only addresses, reserved addresses and locked EEPROM blocks are ignored. Incomplete bytes are not written. Writes to unlocked EEPROM blocks are to shadow RAM rather than EEPROM. See the Memory section for more details. Copy Data [48h, XX]. This command copies the contents of shadow RAM to EEPROM for the 4-byte EEPROM block containing address XX. Copy data commands that address locked blocks are ignored. While the copy data command is executing, the EEC bit in the EEPROM register is set to 1 and writes to iButton is a registered trademark of Dallas Semiconductor.

EEPROM addresses are ignored. Reads and writes to non-EEPROM addresses can still occur while the copy is in progress. The copy data command takes t EEC time to execute, starting on the next falling edge after the address is tra nsmitted. The copy data command is ig nored by the DS2720 while in the sleep mode. Recall Data [B8h, XX]. This command recalls the contents of the 4-byte EEPROM block containing address XX to shadow RAM. Lock [6Ah, XX]. This command locks (write-protects) the 4-byte block of EEPROM memory containing memory address XX. The LOCK bit in the EEPROM register must be set to l before the lock command is executed. To help prevent unintenti onal locks, one must issue the lo ck command immediately after setting the LOCK bit (EEPROM register, address 07h, bit 06) to a 1. If the LOCK bit is 0 or if setting the lock bit to 1 does not immediately precede the lock command, the lock command has no effect. The lock command is permanent; a locked block can never be written again. The lock command is ignored by the DS2720 while in the sleep mode. Table 5. FUNCTION COMMANDS 69h, XX Master Rx Up to 256 bytes of data Write Data Writes data to memory starting at address XX 6Ch, XX Master Tx Up to 256 bytes of data Copy Data Copies shadow RAM data to EEPROM block containing address XX 48h, XX Master Reset None Recall Data Recalls EEPROM block containing address XX to RAM B8h, XX Master Reset None Lock Permanently locks the block of EEPROM containing address XX 6Ch, 07h, 4Xh 6Ah, XX Master Reset None

Figure 11. NET ADDRESS COMMAND FLOW CHART

1 BYTE

6 BYTES

data. All of these types of signaling except the presence pulse are initiated by the bus master. The initialization sequence required to begin any communication with the DS2720 is shown in Figure 12. A presence pulse following a reset pulse indicates the DS2720 is ready to accept a net address command. rising edge on the DQ pin, the DS2720 waits for tPDH and then transmits the presence pulse for tPDL. Figure 12. 1-WIRE INITIALIZATION SEQUENCE slot, the bus line must be pulled low and held low for the duration of the write-time slot. with a 1/g109s minimum recovery time, tREC, between cycles. See Figure 13 for more information.

Figure 13. 1-WIRE WRITE- AND READ-TIME SLOTS

ABSOLUTE MAXIMUM RATINGS* Voltage on PLS, Relative to VSS - 0 . 3 V t o + 1 8 V Voltage on CC, DC, and CP Pins, Relative to VSS -0.3V to +12V Voltage on any Other Pin, Relative to VSS -0.3V to +6V Operating Temperature Range -40°C to +85°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/JEDEC-STD-020A This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of th is specification is not im plied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (-20/g176C to +70/g176C, 2.5V /g163 VDD /g163 5.5V) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Supply Voltage V DD 2.5 5.5 V 1 Data Pin DQ -0.3 5.5 V 1 DC ELECTRICAL CHARACTERISTICS (-20/g176C to +70/g176C, 2.5V /g163 VDD /g163 4.5V) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES DQ = VDD 0/g176C /g163 TA /g163 50/g176C 12.5 20 /g109A 2 Active Current I ACTIVE DQ = VDD 25 /g109A 2 Sleep Mode Current I SLEEP DQ = 0V, PS floating 1.5 2.5 /g109A Input Logic High: DQ V IH1 1.5 V 1 Input Logic High: PS VIH2 VDD - 0.2V V 1, 6 Input Logic Low: DQ V IL1 0.4 V 1 Input Logic Low: PS VIL2 0.2 V 1 Output Logic High: CC, DC VOHCP RLOAD > 10M/g87 8.5 9.0 9.5 V 1 Output Logic Low: CC VOLCC RLOAD > 10M/g87 V DD VDD +

0.1 V 1

Output Logic Low: DC VOLDC RLOAD > 10M/g87 VPLS /g163 10V V PLS VPLS +

0.1 V 1, 7

Output Logic Low: DQ VOL1 IOL = 4mA 0.4 V 1 DQ Input Pulldown Current IPD V DQ = 0.4V 0.1 0.5 2.5 /g109A PS Pullup Current IPS V PS = 0.4V 100 nA CC Pulldown Resistance RCCPD 1.2 4 k/g87 DC Pulldown Resistance RDCPD 12 16 k/g87

ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUITRY (0/g176C to +50/g176C, 2.5V /g163 VDD /g163 4.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES V OVA 4.250 4.275 4.300 Overvoltage Detect V OVB 4.325 4.350 4.375 V 1, 3 V OVC 4.275 4.300 4.325 Charge Enable V CE Typ - 75mV VOV/1.022 Typ + 75mV V 1, 3 Undervoltage Detect V UV Typ - 120mV VOV/1.55 Typ + 120mV V 1, 3 Overtemperature Detect T MAX 70 90 110 /g176C 3 Overcurrent Detect V OC 140 200 260 mV 1, 3 Short-Circuit Detect V SC 2.0 2.3 2.6 V 1 Overvoltage Delay t OVD 0.75 1.0 1.25 s 3 Undervoltage Delay t UVD 90 125 160 ms 3 Overcurrent Delay t OCD 12 16 20 ms 3 Short-Circuit Delay t SCD 50 100 150 /g109s Test Resistance, ITST Active R TST1 3 11 k/g87 5 Test Resistance, Recovery Charging RTST2 5 15 k/g87 5 Charger Detect Voltage V CH 20 60 120 mV ELECTRICAL CHARACTERISTICS: 1-WIRE INTERFACE (-20/g176C to +70/g176C, 2.5V /g163 VDD /g163 5.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Time Slot t SLOT 60 120 /g109s Recovery Time t REC 1 /g109s Write 0 Low Time t LOW0 60 120 /g109s Write 1 Low Time t LOW1 1 15 /g109s Read Data Valid t RDV 15 /g109s Reset Time High t RSTH 480 /g109s Reset Time Low t RSTL 480 960 /g109s Presence Detect High t PDH 15 60 /g109s Presence Detect Low t PDL 60 240 /g109s Active Transition to CC/DC Engage tON 100 ms 4 DQ Capacitance C DQ 25 pF

SPECIFICATION: (-20/g176C to +70/g176C, 2.5V /g163 VDD /g163 5.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Copy to EEPROM Time t EEC 1 5 ms EEPROM Copy Endurance N EEC 25,000 cycles EEPROM Data Retention t EEDR 4 years NOTES 1. All voltages are referenced to V SS. 2. Specified with no resistive load on CC, DC, or CP. 3. Contact the factory for different voltage trip points and delay periods. 4. Typical load capacitance on CC, DC is 1000pF CP (charge pump reservoir cap) = 0.1 /g109F. DC load total on CC, DC, CP > 10M/g87. 5. R TST = |VPLS - VDD| / I measured, with VPLS = 3.2V, VDD = 3.6V when test current, ITST, active for RTST1 ; and VPLS = 4.0V, VDD = 2.5V when recovery charging for RTST2. 6. Maximum high-to-low fall time is 5 /g109s. 7. Internal 10V clamp on DC pin limits DC output logic low when PLS > 10V 8. Short-circuit delay tested with V DD ramped from 3.1V to 1.9V in 5/g109s. Delay measured from VDD = 2.5V to DC pin fall to 7V from VOHCP.