DS26401DK MAXIM | Alldatasheet
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1 of 34 REV: 122203 GENERAL DESCRIPTION The DS26401DK is an easy-to-use evaluation board for the DS26401 octal T1/E1/J1 framer. It is intended to be used as a daughter card with the DK101 motherboard or the DK2000 motherboard. The DS26401DK comes complete with a DS26401 octal framer, two DS21448 quad LIUs, transformers, termination resistors, network connectors, and motherboard connectors. The DK101/DK2000 motherboard and the Dallas’ ChipView software give point-and-click access to configurations and status registers from a Windows /g226-based PC. On-board LEDs indicate loss-of-signal, loss-of-frame, and interrupt status. Each DS26401DK is shipped with a free DK101 motherboard. For complex applications, the DK2000 high-performance demo kit motherboard can be purchased separately. Windows is a registered trademark of Microsoft Corp. DESIGN KIT CONTENTS DS26401DK Board DK101 Low-Cost Motherboard CD-ROM ChipView Software DS26401DK Data Sheet DK101 Data Sheet DS26401 Data Sheet DS21448 Data Sheet DS26401 Errata Sheet DS21448 Errata Sheet
FEATURES
/g167/g32Demonstrates Key Functions of the DS26401 Octal T1/E1/J1 Framer /g167/g32Includes Two DS21448 Quad LIUs, Transformers, BNC and RJ45 Connectors, and Termination Passives /g167/g32Compatible with DK101 and DK2000 Demo Kit Motherboards /g167/g32DK101/DK2000 and ChipView Software Provide Point-and-Click Access to the DS26401 Register Set /g167/g32All Equipment-Side Framer Pins are Easily Accessible for External Data Source/Sink /g167/g32Memory-Mapped FPGA Provides Flexible Clock/Data/Sync Connections Among Framer Ports and DK2000 Motherboard /g167/g32LEDs for Loss-of-Signal, Loss-of-Frame, and Interrupt /g167/g32Easy-to-Read Silk-Screen Labels Identify the Signals Associated with All Connectors, Jumpers, and LEDs
ORDERING INFORMATION
DS26401DK DS26401 Demo Kit Daughter Card (with included DK101 motherboard) DS26401DK Octal T1/E1/J1 Framer Design Kit Daughter Card www.maxim-ic.com
DS26401DK Octal T1/E1/J1 Framer Design Kit 2 of 34 COMPONENT LIST DESIGNATION QTY DESCRIPTION SUPPLIER PART C1, C3, C5, C7, C9, C11, C13, C15, C17C24, C26, C28C31, C35C42 29 00.1/g109F 20%, 16V X7R ceramic capacitors (0603) AVX 0603YC104MAT C2, C4, C6, C8, C10, C12, C14, C16 8 1/g109F 10%, 16V ceramic capacitors (1206) Panasonic ECJ-3YB1C105K DS1, DS18 2 LED, green, SMD Panasonic LN1351C DS2DS17 16 LED, red, SMD Panasonic LN1251C J1, J3J10, J12-J18 16 5-pin connectors, 75/g87 BNC vertical Bourns CP-BNCPC-004 J2, J11 2 Right-angle, RJ45 8-pin 4-port jack 3M Electronics 43223-8140 J19, J20 2 50-pin headers, socket, SMD dual row, vertical Samtec TFM-125-02-S-D-LC J21, J23, J25, J27, J29, J31, J33, J35 8 20-pin headers, dual row, vertical Samtec HDR-TSW-110-14-T-D J22, J24, J26, J28, J30, J32, J34, J36 8 10-pin headers, dual row, vertical Murrietta N/A JP1 1 12-pin connector, dual row, vertical Murrietta N/A R1, R2, R5, R6, R9, R10, R13, R14, R17, R18, R21, R22, R25, R26, R29, R30, R67 17 0/g87 1%, 1/16W resistors (0603) AVX CJ10-000F R3, R4, R7, R8, R11, R12, R15, R16, R19, R20, R23, R24, R27, R28, R31, R32 16 60.4/g87 1%, 1/16W resistors (0603) Panasonic ERJ-3EKF60R4V R33R35 3 10k/g87 5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V R36, R37, R68 3 330/g87 5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ331V R38, R59R66 9 30.1/g87 1%, 1/16W resistors (0603) Panasonic ERJ-3EKF30R1V R39R54 16 300/g87 5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ301V R55R58 4 10.0k/g87 1%, 1/16W resistors (0603) Panasonic ERJ-3EKF1002V T1T8 8 XFMR, dual, 16-pin SMT Pulse Engineering TX1467 U1 1 Octal T1/E1/J1 framer Dallas Semiconductor DS26401 U2, U3 2 3.3V E1/T1/J1 quad LIU 128-pin LQFP, 0°C to +70°C Dallas Semiconductor DS21448L U4 1 1M PROM for FPGA 44-pin TQFP Xilinx XC18V01VQ44C_U U6 1 8-pin /g109MAX/SO 2.5V or Adj Maxim MAX1792EUA25 U7 1 XILINX Spartan 2.5V FPGA, 256-pin BGA Xilinx XC2S50-5FG256C
DS26401DK Octal T1/E1/J1 Framer Design Kit 3 of 34 BOARD FLOORPLAN PORT 2 RJ45 PORT 8 RJ45 PORT 1 RJ45 PORT 3 RJ45 PORT 4 RJ45 PORT 6 RJ45 PORT 5 RJ45 PORT 7 RJ45 DS21448 LIU DS26401 FRAMER FPGA CPU INTERFACE CPU INTERFACE TEST POINTS (x4) TCLK TSYSCLK TSYNC TSSYNC TSIG TSER TCHBLK TCLKO RCLK RSYSCLK RSYNC RMSYNC RSIG RSER RCHBLK JTAG I/F LED RLOF, RLOS x 4 PORT 2 BNC PORT 8 BNC PORT 1 BNC PORT 3 BNC PORT 4 BNC PORT 6 BNC PORT 5 BNC PORT 7 BNC XFMR TXRX XFMR TXRX XFMR TXRX XFMR TXRX XFMR TXRX XFMR TXRX XFMR TXRX XFMR TXRX DS21448 LIU LED RLOF, RLOS x 4 CONFIG PROM TEST POINTS (x4) TCLK TSYSCLK TSYNC TSSYNC TSIG TSER TCHBLK TCLKO RCLK RSYSCLK RSYNC RMSYNC RSIG RSER RCHBLK
/g183/g32Connect DS26401DK to DK101 motherboard. /g183/g32Connect serial cable to a PC and DK101. /g183/g32Power DK101 with 3.3V. /g183/g32Load ChipView software. /g183/g32Select Register View. 401_global_e1_DS26401DC.def file. /g183/g32Make sure that all the register settings are correct for the proper function desired for the DS26401DK. (www.maxim-ic.com/DS21448) for all questions pertaining to device functionality. DK101 daughter card address space begins at 0x81000000. All offsets given below are relative to the beginning of the daughter card address space. Table 1. Daughter Card Address Map the definition file named DS26401DC_FPGA.def.
Table 2. FPGA Register map
Table 2. Register Map (continued) BID is read-only with a value of 0xD. XBIDH is read-only with a value of 0x0. XBIDM is read-only with a value of 0x1. XBIDL is read-only with a value of 0x6. BREV is read-only and displays the current fab revision. AREV is read-only and displays the current assembly revision. PREV is read-only and displays the current PLD firmware revision.
The source for TSER is Defined as shown in Table 3. Table 3. TSERx Source Definition
0000 Tri-state TSIG
0001 Drive TSIG with RSIG1
0010 Drive TSIG with RSIG2
0011 Drive TSIG with RSIG3
0100 Drive TSIG with RSIG4
0101 Drive TSIG with RSIG5
0110 Drive TSIG with RSIG6
0111 Drive TSIG with RSIG7
1000 Drive TSIG with RSIG8
1010 Drive TSIG with T1 OSC
1011 Drive TSIG with E1 OSC
1101 Drive TSIG with a logic 0
1110 Drive TSIG with a logic 1
1111 Tri-state TSIG
Note: Initial values are such that all values are tri-stated.
The source for TSER is Defined as shown in Table 4. Table 4. TSERx Source Definition
0000 Tri-state TSER
0001 Drive TSER with RSER1
0010 Drive TSER with RSER2
0011 Drive TSER with RSER3
0100 Drive TSER with RSER4
0101 Drive TSER with RSER5
0110 Drive TSER with RSER6
0111 Drive TSER with RSER7
1000 Drive TSER with RSER8
1010 Drive TSER with T1 OSC
1011 Drive TSER with E1 OSC
1101 Drive TSER with a logic 0
1110 Drive TSER with a logic 1
1111 Tri-state TSER
Note: Initial values are such that all ports are tri-stated.
The source for TSSYNC is Defined as shown in Table 5. Table 5. TSSYNCx Source Definition
0000 Tri-state TSSYNC
0001 Drive TSSYNC with RMSYNC1
0010 Drive TSSYNC with RMSYNC2
0011 Drive TSSYNC with RMSYNC3
0100 Drive TSSYNC with RMSYNC4
0101 Drive TSSYNC with RMSYNC5
0110 Drive TSSYNC with RMSYNC6
0111 Drive TSSYNC with RMSYNC7
1000 Drive TSSYNC with RMSYNC8
1010 Drive TSSYNC with T1 OSC
1011 Drive TSSYNC with E1 OSC
1101 Drive TSSYNC with a logic 0
1110 Drive TSSYNC with a logic 1
1111 Tri-state TSSYNC
Note: Initial values are such that all ports are tri-stated.
The source for TSYSCLK is Defined as shown in Table 6. Table 6. TSYCLKx Source Definition
0000 Tri-state TSYSCLK
0001 Drive TSYSCLK with RCHBLK 1
0010 Drive TSYSCLK with RCHBLK 2
0011 Drive TSYSCLK with RCHBLK 3
0100 Drive TSYSCLK with RCHBLK 4
0101 Drive TSYSCLK with RCHBLK 5
0110 Drive TSYSCLK with RCHBLK 6
0111 Drive TSYSCLK with RCHBLK 7
1000 Drive TSYSCLK with RCHBLK 8
1001 BPCLK
1010 Drive TSYSCLK with T1 OSC
1011 Drive TSYSCLK with E1 OSC
1101 Drive TSYSCLK with a logic 0
1110 Drive TSYSCLK with a logic 1
1111 Tri-state TSYSCLK
Note: Initial values are such that all ports are tri-stated.
The source for RSYSCLK is Defined as shown in Table 7. Table 7. RSYSCLKx Source Definition
0000 Tri-state RSYSCLK
0001 Drive RSYSCLK with TCHBLK 1
0010 Drive RSYSCLK with TCHBLK 2
0011 Drive RSYSCLK with TCHBLK 3
0100 Drive RSYSCLK with TCHBLK 4
0101 Drive RSYSCLK with TCHBLK 5
0110 Drive RSYSCLK with TCHBLK 6
0111 Drive RSYSCLK with TCHBLK 7
1000 Drive RSYSCLK with TCHBLK 8
1010 Drive RSYSCLK with T1 OSC
1011 Drive RSYSCLK with E1 OSC
1101 Drive RSYSCLK with a logic 0
1110 Drive RSYSCLK with a logic 1
1111 Tri-state RSYSCLK
Note: Initial values are such that all ports are tri-stated.
The source for TCLK is Defined as shown in Table 8. Table 8. TCLKx Source Definition
0000 Tri-state TCLK
0001 Drive TCLK with TCLK 1
0010 Drive TCLK with TCLK 2
0011 Drive TCLK with TCLK 3
0100 Drive TCLK with TCLK 4
0101 Drive TCLK with TCLK 5
0110 Drive TCLK with TCLK 6
0111 Drive TCLK with TCLK 7
1000 Drive TCLK with TCLK 8
1010 Drive TCLK with T1 OSC
1011 Drive TCLK with E1 OSC
1101 Drive TCLK with a logic 0
1110 Drive TCLK with a logic 1
1111 Tri-state TCLK
Note: Initial values are such that all ports are tri-stated. RCLK to fan out to all the ports on the DS26401, simply tri-state a port on the FPGA and manually jumper the RCLK X pin to the TCLK X pin. Then you can route that signal with register values 0001 to 1000 in the TCLK_SR.
The source for RSYNC is Defined as shown in Table 9. Table 9. RSYNCx Source Definition
0000 Tri-state RSYNC
0001 Drive RSYNC with TSYNC 1
0010 Drive RSYNC with TSYNC 2
0011 Drive RSYNC with TSYNC 3
0100 Drive RSYNC with TSYNC 4
0101 Drive RSYNC with TSYNC 5
0110 Drive RSYNC with TSYNC 6
0111 Drive RSYNC with TSYNC 7
1000 Drive RSYNC with TSYNC 8
1010 Drive RSYNC with T1 OSC
1011 Drive RSYNC with E1 OSC
1101 Drive RSYNC with a logic 0
1110 Drive RSYNC with a logic 1
1111 Tri-state RSYNC
Note: Initial values are such that all ports are tri-stated.
The source for TSYNC is Defined as shown in Table 10. Table 10. TSYNCx Source Definition
00000 Tri-state TSYNC
00001 Drive TSYNC with RSYNC 1
00010 Drive TSYNC with RSYNC 2
00011 Drive TSYNC with RSYNC 3
00100 Drive TSYNC with RSYNC 4
00101 Drive TSYNC with RSYNC 5
00110 Drive TSYNC with RSYNC 6
00111 Drive TSYNC with RSYNC 7
01000 Drive TSYNC with RSYNC 8
01010 Drive TSYNC with T1 OSC
01011 Drive TSYNC with E1 OSC
01101 Drive TSYNC with a logic 0
01110 Drive TSYNC with a logic 1
10001 Drive TSYNC with RMSYNC 1
10010 Drive TSYNC with RMSYNC 2
10011 Drive TSYNC with RMSYNC 3
10100 Drive TSYNC with RMSYNC 4
10101 Drive TSYNC with RMSYNC 5
10110 Drive TSYNC with RMSYNC 6
10111 Drive TSYNC with RMSYNC 7
11000 Drive TSYNC with RMSYNC 8
11111 Tri-state TSYNC
Note: Initial values are such that all ports are tri-stated.
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Ma xim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specification s without notice at any time. Table 11. MCLK A Source Definition
00 Tri-state MCLK
11 Tri-state MCLK
Note: Initial values are such that MCLK is 2.048MHz. Table 12. MCLK B Source Definition Note: Initial values are such that that MCLK is 2.048MHz. Table 13. MCLK A Source Definition
00 Tri-state REF CLK
11 Tri-state REF CLK
Note: Initial values are such that REF is 2.048MHz. For technical support, please email your questions to telecom.support@dalsemi.com. The DS26401DK schematics are featured in the following pages.