DS25BR110_0711

DS25BR110_0711 NSC | Alldatasheet

Document overview

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Technical content

Features

■ DC - 3.125 Gbps low jitter, high noise immunity, low power operation ■ Four levels of receive equalization reduce ISI jitter ■ On-chip 100Ω input and output termination minimizes insertion and return losses, reduces component count and minimizes board space ■ 7 kV ESD on LVDS I/O pins protects adjoining components ■ Small 3 mm x 3 mm 8-LLP space saving package

Applications

■ Clock and data buffering ■ Metallic cable equalization ■ FR-4 equalization Typical Application 30005310 © 2007 National Semiconductor Corporation 300053 www.national.com DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

Pin Name Pin Name Pin Type Pin Description EQ0 1 Input Equalizer select pin. IN+ 2 Input Non-inverting LVDS input pin. IN- 3 Input Inverting LVDS input pin. EQ1 4 Input Equalizer select pin. NC 5 NA "NO CONNECT" pin. OUT- 6 Output Inverting LVDS output pin. OUT+ 7 Output Non-inverting LVDS Output pin. VCC 8 Power Power supply pin. GND DAP Power Ground pad (DAP - die attach pad) Control Pins (EQ0 and EQ1) Truth Tables EQ1 EQ0 Equalization Level 0 0 Off 0 1 Low (Approx. 4 dB at 1.56 GHz) 1 0 Medium (Approx. 8 dB at 1.56 GHz) 1 1 High (Approx. 16 dB at 1.56 GHz) Ordering Codes and Configurations NSID Function Available Equalization Levels Available Pre-emphasis Levels DS25BR100TSD Buffer/Repeater Low / Medium Off / Medium DS25BR110TSD Receiver Off / Low / Medium / High NA DS25BR120TSD Driver NA Off / Low / Medium / High DS25BR150TSD Buffer/Repeater NA NA www.national.com 2 DS25BR110

Absolute Maximum Ratings (Note 4) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +4V LVCMOS Input Voltage (EQ0, EQ1) −0.3V to (VCC + 0.3V) LVDS Input Voltage (IN+, IN−) −0.3V to +4V LVDS Differential Input Voltage ((IN+) - (IN−)) 0V to 1.0V LVDS Output Voltage (OUT+, OUT−) −0.3V to (VCC + 0.3V) LVDS Differential Output Voltage ((OUT+) - (OUT−)) 0V to 1.0V LVDS Output Short Circuit Current Duration 5 ms Junction Temperature +150°C Storage Temperature Range −65°C to +150°C Lead Temperature Range Soldering (4 sec.) +260°C Maximum Package Power Dissipation at 25°C Derate SDA Package 16.7 mW/°C above +25°C Package Thermal Resistance θJA +60.0°C/W θJC +12.3°C/W ESD Susceptibility HBM (Note 1) ≥7 kV MM (Note 2) ≥250V CDM (Note 3) ≥1250V Note 1: Human Body Model, applicable std. JESD22-A114C Note 2: Machine Model, applicable std. JESD22-A115-A Note 3: Field Induced Charge Device Model, applicable std. JESD22-C101-C Recommended Operating Conditions Min Typ Max Units Supply Voltage (VCC) 3.0 3.3 3.6 V Receiver Differential Input Voltage (VID) 1.0 V Operating Free Air Temperature (TA) −40 +25 +85 °C Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7) Symbol Parameter Conditions Min Typ Max Units LVCMOS INPUT DC SPECIFICATIONS (EQ0, EQ1) VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = 3.6V VCC = 3.6V 0 ±10 μA IIL Low Level Input Current VIN = GND VCC = 3.6V 0 ±10 μA VCL Input Clamp Voltage ICL = −18 mA, VCC = 0V -0.9 −1.5 V LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-) VOD Differential Output Voltage RL = 100Ω 250 350 450 mV ΔVOD Change in Magnitude of VOD for Complimentary Output States -35 35 mV VOS Offset Voltage RL = 100Ω 1.05 1.2 1.375 V ΔVOS Change in Magnitude of VOS for Complimentary Output States -35 35 mV IOS Output Short Circuit Current (Note 8) OUT to GND -35 -55 mA OUT to VCC 7 55 mA COUT Output Capacitance Any LVDS Output Pin to GND 1.2 pF ROUT Output Termination Resistor Between OUT+ and OUT- 100 Ω 3 www.national.com DS25BR110

Symbol Parameter Conditions Min Typ Max Units LVDS INPUT DC SPECIFICATIONS (IN+, IN-) VID Input Differential Voltage 0 1 V VTH Differential Input High Threshold VCM = +0.05V or VCC-0.05V 0 +100 mV VTL Differential Input Low Threshold −100 0 mV VCMR Common Mode Voltage Range VID = 100 mV 0.05 VCC - 0.05 V IIN Input Current VIN = 3.6V or 0V VCC = 3.6V or 0V ±1 ±10 μA CIN Input Capacitance Any LVDS Input Pin to GND 1.7 pF RIN Input Termination Resistor Between IN+ and IN- 100 Ω SUPPLY CURRENT ICC Supply Current EQ0 = 0, EQ1 = 0 35 43 mA Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. www.national.com 4 DS25BR110

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10) Symbol Parameter Conditions Min Typ Max Units LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-) tPHLD Differential Propagation Delay High to Low RL = 100Ω 350 465 ps tPLHD Differential Propagation Delay Low to High 350 465 ps tSKD1 Pulse Skew |tPLHD − tPHLD| (Note 12) 45 100 ps tSKD2 Part to Part Skew (Note 13) 45 150 ps tLHT Rise Time RL = 100Ω 80 150 ps tHLT Fall Time 80 150 ps JITTER PERFORMANCE WITH EQ = OFF tRJ1A Random Jitter (RMS Value) No Test Channels (Note 14) VID = 350 mV VCM = 1.2V Clock (RZ) EQ0 = 0, EQ1 = 0 2.5 Gbps 0.5 1 ps tRJ2A 3.125 Gbps 0.5 1 ps tDJ1A Deterministic Jitter (Peak to Peak) No Test Channels (Note 15) VID = 350 mV VCM = 1.2V K28.5 (NRZ) EQ0 = 0, EQ1 = 0

2.5 Gbps 11 40 ps

3.125 Gbps 11 47 ps

tTJ1A Total Jitter (Peak to Peak) No Test Channels (Note 16) VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) EQ0 = 0, EQ1 = 0 2.5 Gbps 0.05 0.16 UIP-P tTJ2A 3.125 Gbps 0.08 0.20 UIP-P 5 www.national.com DS25BR110

Symbol Parameter Conditions Min Typ Max Units JITTER PERFORMANCE WITH EQ = LOW (Figures 5 and 6 ) tRJ1B Random Jitter (RMS Value) Test Channel D (Note 14) VID = 350 mV VCM = 1.2V Clock (RZ) EQ0 = 1, EQ1 = 0 2.5 Gbps 0.5 1 ps tRJ2B 3.125 Gbps 0.5 1 ps tDJ1B Deterministic Jitter (Peak to Peak) Test Channel D (Note 15) VID = 350 mV VCM = 1.2V K28.5 (NRZ) EQ0 = 1, EQ1 = 0

2.5 Gbps 1 16 ps

3.125 Gbps 11 31 ps

tTJ1B Total Jitter (Peak to Peak) Test Channel D (Note 16) VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) EQ0 = 1, EQ1 = 0 2.5 Gbps 0.03 0.09 UIP-P tTJ2B 3.125 Gbps 0.06 0.14 UIP-P JITTER PERFORMANCE WITH EQ = MEDIUM (Figures 5 and 6 ) tRJ1C Random Jitter (RMS Value) Test Channel E (Note 14) VID = 350 mV VCM = 1.2V Clock (RZ) EQ0 = 0, EQ1 = 1 2.5 Gbps 0.5 1 ps tRJ2C 3.125 Gbps 0.5 1 ps tDJ1C Deterministic Jitter (Peak to Peak) Test Channel E (Note 15) VID = 350 mV VCM = 1.2V K28.5 (NRZ) EQ0 = 0, EQ1 = 1

2.5 Gbps 10 29 ps

3.125 Gbps 27 43 ps

tTJ1C Total Jitter (Peak to Peak) Test Channel E (Note 16) VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) EQ0 = 0, EQ1 = 1 2.5 Gbps 0.07 0.12 UIP-P tTJ2C 3.125 Gbps 0.12 0.17 UIP-P JITTER PERFORMANCE WITH EQ = HIGH (Figures 5 and 6) tRJ1D Random Jitter (RMS Value) Test Channel F (Note 14) VID = 350 mV VCM = 1.2V Clock (RZ) EQ0 = 1, EQ1 = 1 2.5 Gbps 1.6 2.1 ps tRJ2D 3.125 Gbps 1.7 2.3 ps tDJ1D Deterministic Jitter (Peak to Peak) Test Channel F (Note 15) VID = 350 mV VCM = 1.2V K28.5 (NRZ) EQ0 = 1, EQ1 = 1

2.5 Gbps 30 45 ps

3.125 Gbps 43 59 ps

tTJ1D Total Jitter (Peak to Peak) Test Channel F (Note 16) VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) EQ0 = 1, EQ1 = 1 2.5 Gbps 0.14 0.27 UIP-P tTJ2D 3.125 Gbps 0.19 0.28 UIP-P Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 11: Specification is guaranteed by characterization and is not tested in production. Note 12: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 13: tSKD2, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. Note 14: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically. Note 15: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted algebraically. Note 16: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted. www.national.com 6 DS25BR110

FIGURE 5. Equalization Performance Test Circuit FIGURE 6. Test Channel Description (S) = 5 mils, Height (B) = 16 mils.

500 MHz 750 MHz 1000 MHz 1250 MHz 1500 MHz 1560 MHz

The DS25BR110 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the DS25BR110 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following three figures illus- trate typical DC-coupled interface to common differential drivers. Note that the DS25BR110 inputs are internally terminated with a 100Ω resistor. 30005311 Typical LVDS Driver DC-Coupled Interface to DS25BR110 Input 30005312 Typical CML Driver DC-Coupled Interface to DS25BR110 Input 30005313 Typical LVPECL Driver DC-Coupled Interface to DS25BR110 Input 9 www.national.com DS25BR110

The DS25BR110 outputs signals compliant to the LVDS standard. It can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a common mode input range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation. 30005314 Typical DS25BR110 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver www.national.com 10 DS25BR110

Maximum Data Rate as a Function of CAT5e (Belden 1700A) Length 30005336 Maximum Data Rate as a Function of CAT7 (Siemon Tera) Length 30005338 Maximum Data Rate as a Function of CAT5e (Belden 1700A) Length DS25BR120 Used as a Driver DS25BR110 Used as a Receiver 30005335 Maximum Data Rate as a Function of CAT5e (Belden 1700A) Length 30005337 Maximum Data Rate as a Function of CAT7 (Siemon Tera) Length 30005339 Maximum Data Rate as a Function of CAT5e (Belden 1700A) Length DS25BR120 Used as a Driver DS25BR110 Used as a Receiver 11 www.national.com DS25BR110

A 2.5 Gbps NRZ PRBS-7 After 70" Differential FR-4 Stripline V:100 mV / DIV, H:75 ps / DIV 30005332 A 3.125 Gbps NRZ PRBS-7 After 70" Differential FR-4 Stripline V:100 mV / DIV, H:50 ps / DIV 30005341 Total Jitter as a Function of Data Rate 30005331 An Equalized 2.5 Gbps NRZ PRBS-7 After 70" Differential FR-4 Stripline V:100 mV / DIV, H:75 ps / DIV 30005333 An Equalized 3.125 Gbps NRZ PRBS-7 After 70" Differential FR-4 Stripline V:100 mV / DIV, H:50 ps / DIV 30005342 Total Jitter as a Function of Data Rate www.national.com 12 DS25BR110

Total Jitter as a Function of Data Rate 30005346 Total Jitter as a Function of Input Amplitude 30005348 Total Jitter as a Function of Input Amplitude 30005344 Total Jitter as a Function of Data Rate 30005345 Total Jitter as a Function of Input Amplitude 30005347 Total Jitter as a Function of Input Amplitude 13 www.national.com DS25BR110

Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS25BR110TSD (See AN-1187 for PCB Design and Assembly Recommendations) www.national.com 14 DS25BR110

15 www.national.com DS25BR110

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