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DS25BR100TSD/NOPB

Texas Instruments

3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

Manufacturer: Texas Instruments

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www.ti.com SNLS217F –MARCH 2007–REVISED APRIL 2013 DS25BR100/DS25BR1013.125GbpsLVDSBufferwithTransmitPre-Emphasisand ReceiveEqualization Check forSamples: DS25BR100 1FEATURES DESCRIPTION The DS25BR100 and DS25BR101 aresinglechannel 2• DC -3.125Gbps Low Jitter,High Noise 3.125 Gbps LVDS buffersoptimizedforhigh-speedImmunity,Low Power Operation signaltransmissionover lossyFR-4 printedcircuit• Receive EqualizationReduces ISIJitterDue to boardbackplanesand balancedmetalliccables.Fully Media Loss differentialsignalpaths ensure exceptionalsignal integrityand noiseimmunity.• TransmitPre-Emphasis DrivesLossy Backplanes and Cables The DS25BR100 and DS25BR101 featuretransmit

On-Chip 100Ω Inputand Output Termination: pre-emphasis(PE) and receiveequalization(EQ), making them idealforuse as a repeaterdevice.– MinimizesInsertionand Return Losses Other LVDS deviceswithsimilarIO characteristics– Reduces Component Count includethe followingproducts.The DS25BR120 – MinimizesBoard Space featuresfourlevelsof pre-emphasisforuse as an optimized driverdevice, while the DS25BR110• DS25BR101 EliminatesOn-Chip Input featuresfourlevelsof equalizationforuse as anTerminationforAdded Design Flexibility optimizedreceiverdevice.The DS25BR150 is a• 7 kV ESD on LVDS I/OPins ProtectsAdjoining buffer/repeaterwith the lowestpower consumptionComponents and does not featuretransmitpre-emphasis nor
Small 3 mm x 3 mm WSON-8 Space Saving receiveequalization. Package Wide inputcommon mode range allowsthereceiver to accept signalswith LVDS, CML and LVPECLAPPLICATIONS levels;the outputlevelsare LVDS. A very small package footprintrequiresminimal space on the• Clock and Data Buffering boardwhiletheflow-throughpinoutallowseasy board• MetallicCable Drivingand Equalization layout.On theDS25BR100 thedifferentialinputand
FR-4 Equalization outputisinternallyterminatedwitha 100Ω resistorto lower returnlosses,reduce component count and furtherminimize board space. For added design flexibilitythe 100Ω input terminationson the DS25BR101 have been eliminated.This elimination enables a designerto adjustthe terminationfor custom interconnecttopologiesand layout. TypicalApplication Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2007–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS217F –MARCH 2007–REVISED APRIL 2013 www.ti.com Device Information Device Function TerminationOption AvailableSignalConditioning DS25BR100 Buffer/Repeater Internal100Ω forLVDS inputs 2 Levels:PE and EQ DS25BR101 Buffer/Repeater Externalterminationrequired 2 Levels:PE and EQ DS25BR110 Receiver Internal100Ω forLVDS inputs 4 Levels:EQ DS25BR120 Driver Internal100Ω forLVDS inputs 4 Levels:PE DS25BR150 Buffer/Repeater Internal100Ω forLVDS inputs None Block Diagram DS25BR101 eliminates100Ω inputtermination. Pin Diagram PIN DESCRIPTIONS Pin Name Pin Name Pin Type Pin Description EQ 1 Input Equalizerselectpin. IN+ 2 Input Non-invertingLVDS inputpin. IN- 3 Input InvertingLVDS inputpin. PE 4 Input Pre-emphasisselectpin. NC 5 NA "NO CONNECT" pin. OUT- 6 Output InvertingLVDS outputpin. OUT+ 7 Output Non-invertingLVDS Outputpin. VCC 8 Power Power supplypin. GND DAP Power Ground pad (DAP -dieattachpad). ControlPins (PE and EQ) TruthTable EQ PE EqualizationLevel Pre-emphasis Level 0 0 Low (Approx.4 dB at1.56GHz) Off 0 1 Low (Approx.4 dB at1.56GHz) Medium (Approx.6 dB at1.56GHz) 1 0 Medium (Approx.8 dB at1.56GHz) Off 1 1 Medium (Approx.8 dB at1.56GHz) Medium (Approx.6 dB at1.56GHz)

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www.ti.com SNLS217F –MARCH 2007–REVISED APRIL 2013 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) SupplyVoltage(VCC ) −0.3Vto+4V LVCMOS InputVoltage(EQ,PE) −0.3Vto(VCC + 0.3V) LVDS InputVoltage(IN+,IN−) −0.3Vto+4V DifferentialInputVoltage|VID|(DS25BR100) 1V LVDS DifferentialInputVoltage(DS25BR101) VCC + 0.6V LVDS OutputVoltage(OUT+, OUT −) −0.3Vto(VCC + 0.3V) LVDS DifferentialOutputVoltage((OUT+)-(OUT −)) 0V to1V LVDS OutputShortCircuitCurrentDuration 5 ms JunctionTemperature +150°C StorageTemperatureRange −65°C to+150°C Lead TemperatureRange Soldering(4sec.) +260°C Maximum Package Power Dissipationat25°C DerateNGQ0008A Package 16.7mW/ °C above +25°C θJA +60.0°C/W Package ThermalResistance θJC +12.3°C/W HBM (3) ≥7 kV ESD Susceptibility MM (4) ≥250V CDM (5) ≥1250V (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. (3) Human Body Model,applicablestd.JESD22-A114C (4) Machine Model,applicablestd.JESD22-A115-A (5) FieldInducedCharge DeviceModel,applicablestd.JESD22-C101-C Recommended OperatingConditions Min Typ Max Units SupplyVoltage(VCC ) 3.0 3.3 3.6 V ReceiverDifferentialInputVoltage(VID)(DS25BR100 only) 1.0 V OperatingFreeAirTemperature(TA) −40 +25 +85 °C Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS25BR100

SNLS217F –MARCH 2007–REVISED APRIL 2013 www.ti.com DC ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified(1)(2)(3) Parameter TestConditions Min Typ Max Units LVCMOS INPUT DC SPECIFICATIONS (EQ,PE) VIH HighLevelInputVoltage 2.0 VCC V VIL Low LevelInputVoltage GND 0.8 V IIH HighLevelInputCurrent VIN = 3.6V 0 ±10 μA VCC = 3.6V IIL Low LevelInputCurrent VIN = GND 0 ±10 μA VCC = 3.6V VCL InputClamp Voltage ICL = −18 mA, VCC = 0V -0.9 −1.5 V LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-) VOD DifferentialOutputVoltage 250 350 450 mV R L = 100ΩΔVOD Change inMagnitudeofVOD forComplimentary -35 35 mVOutputStates VOS OffsetVoltage 1.05 1.2 1.375 V R L = 100ΩΔVOS Change inMagnitudeofVOS forComplimentary -35 35 mVOutputStates IOS OutputShortCircuitCurrent(4) OUT toGND, PE = 0 -35 -55 mA OUT toVCC ,PE = 0 7 55 mA C OUT OutputCapacitance Any LVDS OutputPintoGND 1.2 pF R OUT OutputTerminationResistor Between OUT+ and OUT- 100 Ω LVDS INPUT DC SPECIFICATIONS (IN+,IN-) VID InputDifferentialVoltage(5) 0 1 V VTH DifferentialInputHighThreshold VCM = +0.05V orVCC -0.05V 0 +100 mV VTL DifferentialInputLow Threshold −100 0 mV VCMR Common Mode VoltageRange VID = 100 mV 0.05 VCC - V 0.05 VIN = GND or3.6V ±1 ±10 μAIIN InputCurrent VCC = 3.6Vor0.0V C IN InputCapacitance Any LVDS InputPintoGND 1.7 pF R IN InputTerminationResistor(6) Between IN+ and IN- 100 Ω SUPPLY CURRENT ICC SupplyCurrent EQ = 0,PE = 0 35 43 mA (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Allvoltagesarereferencedtoground exceptVOD and ΔVOD . (3) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (4) Outputshortcircuitcurrent(IOS )isspecifiedas magnitudeonly,minus signindicatesdirectiononly. (5) InputDifferentialVoltage(VID)The DS25BR100 limitsinputamplitudeto1 volt.The DS25BR101 supportsany VID withinthesupply voltagetoGND range. (6) InputTerminationResistor(RIN)The DS25BR100 providesan integrated100 ohm inputterminationforthehighspeed LVDS pair.The DS25BR101 eliminatesthisinternaltermination.

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www.ti.com SNLS217F –MARCH 2007–REVISED APRIL 2013 AC ElectricalCharacteristics(1) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified(2)(3) Parameter TestConditions Min Typ Max Units LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-) tPHLD DifferentialPropagationDelayHightoLow 350 465 ps R L = 100Ω tPLHD DifferentialPropagationDelayLow toHigh 350 465 ps tSKD1 PulseSkew |tPLHD − tPHLD |(4) 45 100 ps tSKD2 ParttoPartSkew (5) 45 150 ps tLHT RiseTime 80 150 ps R L = 100Ω tHLT FallTime 80 150 ps JITTER PERFORMANCE WITH PE = OFF AND EQ = LOW (6)(7) tRJ1A VID = 350 mV 2.5Gbps 0.5 1 ps Random Jitter(RMS Value) VCM = 1.2VtRJ2A InputTestChannelD (8) Clock(RZ) 3.125Gbps 0.5 1 ps PE = 0,EQ = 0 tDJ1A VID = 350 mV 2.5Gbps 1 16 ps DeterministicJitter(PeaktoPeak) VCM = 1.2VtDJ2A InputTestChannelD (9) K28.5(NRZ) 3.125Gbps 11 31 ps PE = 0,EQ = 0 tTJ1A VID = 350 mV 2.5Gbps 0.03 0.09 UIP-P TotalJitter(PeaktoPeak) VCM = 1.2VtTJ2A InputTestChannelD (10) PRBS-23 (NRZ) 3.125Gbps 0.06 0.14 UIP-P PE = 0,EQ = 0 JITTER PERFORMANCE WITH PE = OFF AND EQ = MEDIUM (6)(7) tRJ1B VID = 350 mV 2.5Gbps 0.5 1 ps Random Jitter(RMS Value) VCM = 1.2VtRJ2B InputTestChannelE (8) Clock(RZ) 3.125Gbps 0.5 1 ps PE = 0,EQ = 1 tDJ1B VID = 350 mV 2.5Gbps 10 29 ps DeterministicJitter(PeaktoPeak) VCM = 1.2VtDJ2B InputTestChannelE (9) K28.5(NRZ) 3.125Gbps 27 43 ps PE = 0,EQ = 1 tTJ1B VID = 350 mV 2.5Gbps 0.07 0.12 UIP-P TotalJitter(PeaktoPeak) VCM = 1.2VtTJ2B InputTestChannelE (10) PRBS-23 (NRZ) 3.125Gbps 0.12 0.17 UIP-P PE = 0,EQ = 1 (1) Specificationisensuredby characterizationand isnottestedinproduction. (2) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (3) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (4) tSKD1 ,|tPLHD − tPHLD |,isthemagnitudedifferenceindifferentialpropagationdelaytimebetween thepositivegoingedge and thenegative goingedge ofthesame channel. (5) tSKD2 ,ParttoPartSkew, isdefinedas thedifferencebetween theminimum and maximum differentialpropagationdelays.This specificationappliestodevicesatthesame VCC and within5°C ofeach otherwithintheoperatingtemperaturerange. (6) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Allvoltagesarereferencedtoground exceptVOD and ΔVOD . (7) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (8) Measured on a clockedge witha histogramand an acummulationof1500 histogramhits.Inputstimulusjitterissubtracted geometrically. (9) Testedwitha combinationofthe1100000101 (K28.5+character)and 0011111010 (K28.5-character)patterns.Inputstimulusjitteris subtractedalgebraically. (10)Measured on an eye diagramwitha histogramand an acummulationof3500 histogramhits.Inputstimulusjitterissubtracted. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS25BR100

SNLS217F –MARCH 2007–REVISED APRIL 2013 www.ti.com AC ElectricalCharacteristics(1)(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified(2)(3) Parameter TestConditions Min Typ Max Units JITTER PERFORMANCE WITH PE = MEDIUM AND EQ = LOW (11)(12) PE = 1,EQ = 0 tDJ1C VID = 350 mV 2.5Gbps 29 57 psDeterministicJitter(PeaktoPeak) VCM = 1.2VtDJ2C InputTestChannelD K28.5(NRZ) 3.125Gbps 29 51 psOutputTestChannelB (14) PE = 1,EQ = 0 PE = 1,EQ = 0 JITTER PERFORMANCE WITH PE = MEDIUM AND EQ = MEDIUM (11)(12) PE = 1,EQ = 1 tDJ1D VID = 350 mV 2.5Gbps 41 77 psDeterministicJitter(PeaktoPeak) VCM = 1.2VtDJ2D InputTestChannelE K28.5(NRZ) 3.125Gbps 46 98 psOutputTestChannelB (14) PE = 1,EQ = 1 PE = 1,EQ = 1 (11)Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (12)InputDifferentialVoltage(VID)The DS25BR100 limitsinputamplitudeto1 volt.The DS25BR101 supportsany VID withinthesupply voltagetoGND range. (13)Measured on a clockedge witha histogramand an acummulationof1500 histogramhits.Inputstimulusjitterissubtracted geometrically. (14)Testedwitha combinationofthe1100000101 (K28.5+character)and 0011111010 (K28.5-character)patterns.Inputstimulusjitteris subtractedalgebraically. (15)Measured on an eye diagramwitha histogramand an acummulationof3500 histogramhits.Inputstimulusjitterissubtracted.

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4.50 3.75 3.00 2.25 1.50 0.75 0 6 12 18 24 30 VCC = 3.3V TA = 25° C NRZ PRBS-7 TJ = 0.5 UI MAXIMUM DATA RATE (Gbps) CAT5e LENGTH (m) w/ PE and/or EQ w/o PE and EQ 4.50 3.75 3.00 2.25 1.50 0.75 0 6 12 18 24 30 VCC = 3.3V TA = 25° C NRZ PRBS-7 TJ = 0.25 UI MAXIMUM DATA RATE (Gbps) CAT5e LENGTH (m) w/ PE and/or EQ w/o PE and EQ DS25BR100 www.ti.com SNLS217F –MARCH 2007–REVISED APRIL 2013 TypicalPerformance Characteristics Figure1.Maximum Data Rate as a FunctionofCAT5e Figure2.A 2.5Gbps NRZ PRBS-7 After60" (Belden1700A) Length DifferentialFR-4 Stripline V:125 mV /DIV,H:75 ps /DIV Figure3.A 3.125Gbps NRZ PRBS-7 After60" Figure4.Maximum Data Rate as a FunctionofCAT5e (Belden1700A) LengthDifferentialFR-4 Stripline V:125 mV /DIV,H:50 ps /DIV Figure5.An Equalized(withPE and EQ) 2.5Gbps NRZ Figure6.An Equalized(withPE and EQ) 3.125Gbps NRZ PRBS-7 AfterThe 40" Inputand 20" Output PRBS-7 AfterThe 40" Inputand 20" Output DifferentialStripline(Figure16) DifferentialStripline(Figure16) V:125 mV /DIV,H:75 ps /DIV V:125 mV /DIV,H:50 ps /DIV Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS25BR100

VCC = 3.3V TA = 25° C NRZ PRBS-7

3.125 Gbps

PE = Off TOTAL RESIDUAL JITTER (ps) DIFFERENTIAL INPUT VOLTAGE (V) 15" FR4, EQ = Low 30" FR4, EQ = Medium 150 125 100 VCC = 3.3V TA = 25° C NRZ PRBS-7 EQ = Medium PE = Off TOTAL RESIDUAL JITTER (ps) DATA RATE (Gbps) 30" FR4 Stripline 20" FR4 Stripline 40" FR4 Stripline VCC = 3.3V TA = 25° C SUPPLY CURRENT (mA) FREQUENCY (GHz) PE = Medium, EQ = Any PE = Off, EQ = Any 150 125 100 VCC = 3.3V TA = 25° C NRZ PRBS-7 EQ = Low PE = Off TOTAL RESIDUAL JITTER (ps) DATA RATE (Gbps) 20" FR4 Stripline 10" FR4 Stripline 150 125 100 VCC = 3.3V TA = 25° C NRZ PRBS-7

2.5 Gbps

PE = Off TOTAL RESIDUAL JITTER (ps) DIFFERENTIAL INPUT VOLTAGE (V) 15" FR4, EQ = Low 30" FR4, EQ = Medium DS25BR100 SNLS217F –MARCH 2007–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics(continued) Figure7.TotalJitteras a FunctionofData Rate Figure8.TotalJitteras a FunctionofInputAmplitude Figure9.Power Supply Currentas a FunctionofFrequency Figure10.TotalJitteras a FunctionofData Rate Figure11.TotalJitteras a FunctionofInputAmplitude

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www.ti.com SNLS217F –MARCH 2007–REVISED APRIL 2013

APPLICATION INFORMATION

Figure12. DifferentialDriverDC TestCircuit AC TestCircuitsand Timing Diagrams Figure13. DifferentialDriverAC TestCircuit NOTE DS25BR101 requiresexternal100Ω inputtermination. Figure14. PropagationDelay Timing Diagram Figure15. LVDS Output TransitionTimes Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS25BR100

50: MS 50: MS 50: MS 50: MS L=1" L=1" L=1"L=1" 100: Diff. Stripline 50: Microstrip L=4" L=4" L=4" L=4" TEST CHANNEL CHARACTERIZATION BOARD DS25BR100 PATTERN GENERATOR OSCILLOSCOPE 50: Microstrip 50: Microstrip 50: Microstrip 50: Microstrip L=4" L=4" L=4" L=4" TEST CHANNEL CHARACTERIZATION BOARD DS25BR100 PATTERN GENERATOR OSCILLOSCOPE 50: Microstrip 50: Microstrip 50: Microstrip TEST CHANNEL DS25BR100 SNLS217F –MARCH 2007–REVISED APRIL 2013 www.ti.com Pre-Emphasis and EqualizationTestCircuits Figure16. Pre-emphasis and EqualizationPerformance TestCircuit NOTE DS25BR101 requiresexternal100Ω inputtermination. Figure17. EqualizationPerformance TestCircuit NOTE DS25BR101 requiresexternal100Ω inputtermination. Figure18. TestChannel Description

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50:50: VCC CML3.3V or CML2.5V 100: Differential T-Line OUT+ OUT- DS25BR100 IN+ IN- 100: Differential T-Line LVDS DS25BR100 www.ti.com SNLS217F –MARCH 2007–REVISED APRIL 2013 TestChannel Loss Characteristics The testchannelwas fabricatedwithPolycladPCL-FR-370-Laminate/PCL-FRP-370Prepregmaterials(Dielectric constantof3.7and Loss Tangentof0.02).The edge coupleddifferentialstriplineshave thefollowinggeometries: TraceWidth(W) = 5 mils,Gap (S)= 5 mils,Height(B)= 16 mils. TestChannel Length InsertionLoss (dB) (inches) 500 MHz 750 MHz 1000 MHz 1250 MHz 1500 MHz 1560 MHz Device Operation INPUT INTERFACING The DS25BR100/101 acceptsdifferentialsignalsand allowssimpleAC or DC coupling.With a wide common mode range,theDS25BR100/101 can be DC-coupledwithallcommon differentialdrivers(i.e.LVPECL, LVDS, CML). The followingthreefiguresillustratetypicalDC-coupledinterfacetocommon differentialdrivers. The DS25BR100 inputsare internallyterminatedwitha 100Ω resistorforoptimaldeviceperformance,reduced component count,and minimum boardspace.Externalinputterminationson theDS25BR101 need tobe placed as closeas possibletothedeviceinputstoachieveequivalentAC performance.Itisrecommended touse SMT resistorssized0402 orsmallerand tokeep themountingdistancetotheDS25BR101 pinsunder200 mils. When usingtheDS25BR101 ina limitedmulti-droptopology,any transmissionlinestubsshouldbe keptvery shortto minimizeany negativeeffectson signalquality.A singleterminationresistoror resistornetworkthat matches thedifferentiallineimpedance shouldbe used.IfDS25BR101 inputpairsfromtwo separatedevicesare to be connectedto a singledifferentialoutput,itisrecommended to mount the DS25BR101 devicesdirectly oppositeofeach other.One on topofthePCB and theotherdirectlyunder thefirston thebottomofthePCB keeps thedistancebetween inputsequaltothePCB thickness. Figure19. TypicalLVDS DriverDC-Coupled InterfacetoDS25BR100 Input Figure20. TypicalCML DriverDC-Coupled InterfacetoDS25BR100 Input Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS25BR100

100: 100: Differential T-Line DS25BR100 OUT+ OUT- 150-250: 100: Differential T-Line LVDS Receiver IN+ IN- 100: LVPECL Driver 150-250: DS25BR100 SNLS217F –MARCH 2007–REVISED APRIL 2013 www.ti.com Figure21. TypicalLVPECL DriverDC-Coupled InterfacetoDS25BR100 Input NOTE DS25BR101 requiresexternal100Ω inputtermination. OUTPUT INTERFACING The DS25BR100/101 outputssignalsare compliantto the LVDS standard.Itcan be DC-coupled to most common differentialreceivers.The followingfigureillustratesthe typicalDC-coupled interfaceto common differentialreceiversand assumes thatthe receivershave high impedance inputs.While most differential receivershave a common mode inputrangethatcan accommodate LVDS compliantsignals,itisrecommended tochecktherespectivereceiver'sdatasheetpriortoimplementingthesuggestedinterfaceimplementation. Figure22. TypicalOutput DC-Coupled Interfacetoan LVDS, CML or LVPECL Receiver

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REVISION HISTORY

www.ti.com 8-Oct-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS25BR100TSD/NOPB ACTIVE WSON NGQ 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 2R100 DS25BR101TSD/NOPB ACTIVE WSON NGQ 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 2R101 DS25BR101TSDE/NOPB ACTIVE WSON NGQ 8 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 2R101 DS25BR101TSDX/NOPB ACTIVE WSON NGQ 8 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 2R101 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 8-Oct-2015 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS25BR100TSD/NOPB WSON NGQ 8 1000 213.0 191.0 55.0 DS25BR101TSD/NOPB WSON NGQ 8 1000 213.0 191.0 55.0 DS25BR101TSDE/NOPB WSON NGQ 8 250 213.0 191.0 55.0 DS25BR101TSDX/NOPB WSON NGQ 8 4500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 2

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