DS25BR100

DS25BR100_09 NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

Features

■ DC - 3.125 Gbps low jitter, high noise immunity, low power operation ■ Receive equalization reduces ISI jitter due to media loss ■ Transmit pre-emphasis drives lossy backplanes and cables ■ On-chip 100Ω input and output termination minimizes insertion and return losses, reduces component count and minimizes board space. The DS25BR101 eliminates the on-chip input termination for added design flexibility. ■ 7 kV ESD on LVDS I/O pins protects adjoining components ■ Small 3 mm x 3 mm LLP-8 space saving package

Applications

■ Clock and data buffering ■ Metallic cable driving and equalization ■ FR-4 equalization Typical Application 20179110 © 2009 National Semiconductor Corporation 201791 www.national.com DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

Device Function Termination Option Available Signal Conditioning DS25BR100 Buffer / Repeater Internal 100Ω for LVDS inputs 2 Levels: PE and EQ DS25BR101 Buffer / Repeater External termination required 2 Levels: PE and EQ DS25BR110 Receiver Internal 100Ω for LVDS inputs 4 Levels: EQ DS25BR120 Driver Internal 100Ω for LVDS inputs 4 Levels: PE DS25BR150 Buffer / Repeater Internal 100Ω for LVDS inputs None

Ordering Information

DS25BR100TSD 8 Lead LLP Package 1000 SDA08A DS25BR100TSDX 8 Lead LLP Package 4500 SDA08A DS25BR101TSD 8 Lead LLP Package 1000 SDA08A DS25BR101TSDX 8 Lead LLP Package 4500 SDA08A Block Diagram 20179101 Note: DS25BR101 eliminates 100Ω input termination. Pin Diagram 20179104 www.national.com 2 DS25BR100 / DS25BR101

Pin Name Pin Name Pin Type Pin Description EQ 1 Input Equalizer select pin. IN+ 2 Input Non-inverting LVDS input pin. IN- 3 Input Inverting LVDS input pin. PE 4 Input Pre-emphasis select pin. NC 5 NA "NO CONNECT" pin. OUT- 6 Output Inverting LVDS output pin. OUT+ 7 Output Non-inverting LVDS Output pin. VCC 8 Power Power supply pin. GND DAP Power Ground pad (DAP - die attach pad). Control Pins (PE and EQ) Truth Table EQ PE Equalization Level Pre-emphasis Level 0 0 Low (Approx. 4 dB at 1.56 GHz) Off 0 1 Low (Approx. 4 dB at 1.56 GHz) Medium (Approx. 6 dB at 1.56 GHz) 1 0 Medium (Approx. 8 dB at 1.56 GHz) Off 1 1 Medium (Approx. 8 dB at 1.56 GHz) Medium (Approx. 6 dB at 1.56 GHz) 3 www.national.com DS25BR100 / DS25BR101

Absolute Maximum Ratings (Note 4) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +4V LVCMOS Input Voltage (EQ, PE) −0.3V to (VCC + 0.3V) LVDS Input Voltage (IN+, IN−) −0.3V to +4V LVDS Differential Input Voltage (DS25BR100) 0V to 1V LVDS Differential Input Voltage (DS25BR101) VCC + 0.6V LVDS Output Voltage (OUT+, OUT−) −0.3V to (VCC + 0.3V) LVDS Differential Output Voltage ((OUT+) - (OUT−)) 0V to 1V LVDS Output Short Circuit Current Duration 5 ms Junction Temperature +150°C Storage Temperature Range −65°C to +150°C Lead Temperature Range Soldering (4 sec.) +260°C Maximum Package Power Dissipation at 25°C Derate SDA Package 16.7 mW/°C above +25°C Package Thermal Resistance θJA +60.0°C/W θJC +12.3°C/W ESD Susceptibility HBM (Note 1) ≥7 kV MM (Note 2) ≥250V CDM (Note 3) ≥1250V Note 1: Human Body Model, applicable std. JESD22-A114C Note 2: Machine Model, applicable std. JESD22-A115-A Note 3: Field Induced Charge Device Model, applicable std. JESD22-C101-C Recommended Operating Conditions Min Typ Max Units Supply Voltage (VCC) 3.0 3.3 3.6 V Receiver Differential Input Voltage (VID) (DS25BR100 only) 1.0 V Operating Free Air Temperature (TA) −40 +25 +85 °C Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7) Symbol Parameter Conditions Min Typ Max Units LVCMOS INPUT DC SPECIFICATIONS (EQ, PE) VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = 3.6V VCC = 3.6V 0 ±10 μA IIL Low Level Input Current VIN = GND VCC = 3.6V 0 ±10 μA VCL Input Clamp Voltage ICL = −18 mA, VCC = 0V -0.9 −1.5 V LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-) VOD Differential Output Voltage RL = 100Ω 250 350 450 mV ΔVOD Change in Magnitude of VOD for Complimentary Output States -35 35 mV VOS Offset Voltage RL = 100Ω 1.05 1.2 1.375 V ΔVOS Change in Magnitude of VOS for Complimentary Output States -35 35 mV IOS Output Short Circuit Current (Note 10) OUT to GND, PE = 0 -35 -55 mA OUT to VCC, PE = 0 7 55 mA COUT Output Capacitance Any LVDS Output Pin to GND 1.2 pF ROUT Output Termination Resistor Between OUT+ and OUT- 100 Ω www.national.com 4 DS25BR100 / DS25BR101

Symbol Parameter Conditions Min Typ Max Units LVDS INPUT DC SPECIFICATIONS (IN+, IN-) VID Input Differential Voltage (Note 8) 0 1 V VTH Differential Input High Threshold VCM = +0.05V or VCC-0.05V 0 +100 mV VTL Differential Input Low Threshold −100 0 mV VCMR Common Mode Voltage Range VID = 100 mV 0.05 VCC - 0.05 V IIN Input Current VIN = GND or 3.6V VCC = 3.6V or 0.0V ±1 ±10 μA CIN Input Capacitance Any LVDS Input Pin to GND 1.7 pF RIN Input Termination Resistor (Note 9) Between IN+ and IN- 100 Ω SUPPLY CURRENT ICC Supply Current EQ = 0, PE = 0 35 43 mA Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 8: Input Differential Voltage (VID) The DS25BR100 limits input amplitude to 1 volt. The DS25BR101 supports any VID within the supply voltage to GND range. Note 9: Input Termination Resistor (RIN) The DS25BR100 provides an integrated 100 ohm input termination for the high speed LVDS pair. The DS25BR101 eliminates this internal termination. Note 10: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. 5 www.national.com DS25BR100 / DS25BR101

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 11, 12) Symbol Parameter Conditions Min Typ Max Units LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-) tPHLD Differential Propagation Delay High to Low RL = 100Ω 350 465 ps tPLHD Differential Propagation Delay Low to High 350 465 ps tSKD1 Pulse Skew |tPLHD − tPHLD| (Note 14) 45 100 ps tSKD2 Part to Part Skew (Note 15) 45 150 ps tLHT Rise Time RL = 100Ω 80 150 ps tHLT Fall Time 80 150 ps JITTER PERFORMANCE WITH PE = OFF AND EQ = LOW (Figures 6, 7) tRJ1A Random Jitter (RMS Value) Input Test Channel D (Note 16) VID = 350 mV VCM = 1.2V Clock (RZ) PE = 0, EQ = 0 2.5 Gbps 0.5 1 ps tRJ2A 3.125 Gbps 0.5 1 ps tDJ1A Deterministic Jitter (Peak to Peak) Input Test Channel D (Note 17) VID = 350 mV VCM = 1.2V K28.5 (NRZ) PE = 0, EQ = 0

2.5 Gbps 1 16 ps

3.125 Gbps 11 31 ps

tTJ1A Total Jitter (Peak to Peak) Input Test Channel D (Note 18) VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) PE = 0, EQ = 0 2.5 Gbps 0.03 0.09 UIP-P tTJ2A 3.125 Gbps 0.06 0.14 UIP-P JITTER PERFORMANCE WITH PE = OFF AND EQ = MEDIUM (Figures 6, 7) tRJ1B Random Jitter (RMS Value) Input Test Channel E (Note 16) VID = 350 mV VCM = 1.2V Clock (RZ) PE = 0, EQ = 1 2.5 Gbps 0.5 1 ps tRJ2B 3.125 Gbps 0.5 1 ps tDJ1B Deterministic Jitter (Peak to Peak) Input Test Channel E (Note 17) VID = 350 mV VCM = 1.2V K28.5 (NRZ) PE = 0, EQ = 1

2.5 Gbps 10 29 ps

3.125 Gbps 27 43 ps

tTJ1B Total Jitter (Peak to Peak) Input Test Channel E (Note 18) VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) PE = 0, EQ = 1 2.5 Gbps 0.07 0.12 UIP-P tTJ2B 3.125 Gbps 0.12 0.17 UIP-P JITTER PERFORMANCE WITH PE = MEDIUM AND EQ = LOW (Figures 5, 7) tRJ1C Random Jitter (RMS Value) Input Test Channel D Output Test Channel B (Note 16) VID = 350 mV VCM = 1.2V Clock (RZ) PE = 1, EQ = 0 2.5 Gbps 0.5 1 ps tRJ2C 3.125 Gbps 0.5 1 ps tDJ1C Deterministic Jitter (Peak to Peak) Input Test Channel D Output Test Channel B (Note 17) VID = 350 mV VCM = 1.2V K28.5 (NRZ) PE = 1, EQ = 0

2.5 Gbps 29 57 ps

3.125 Gbps 29 51 ps

tTJ1C Total Jitter (Peak to Peak) Input Test Channel D Output Test Channel B (Note 18) VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) PE = 1, EQ = 0 2.5 Gbps 0.10 0.19 UIP-P tTJ2C 3.125 Gbps 0.13 0.22 UIP-P www.national.com 6 DS25BR100 / DS25BR101

Symbol Parameter Conditions Min Typ Max Units JITTER PERFORMANCE WITH PE = MEDIUM AND EQ = MEDIUM (Figures 5, 7) tRJ1D Random Jitter (RMS Value) Input Test Channel E Output Test Channel B (Note 16) VID = 350 mV VCM = 1.2V Clock (RZ) PE = 1, EQ = 1 2.5 Gbps 0.5 1.1 ps tRJ2D 3.125 Gbps 0.5 1 ps tDJ1D Deterministic Jitter (Peak to Peak) Input Test Channel E Output Test Channel B (Note 17) VID = 350 mV VCM = 1.2V K28.5 (NRZ) PE = 1, EQ = 1

2.5 Gbps 41 77 ps

3.125 Gbps 46 98 ps

tTJ1D Total Jitter (Peak to Peak) Input Test Channel E Output Test Channel B (Note 18) VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) PE = 1, EQ = 1 2.5 Gbps 0.13 0.20 UIP-P tTJ2D 3.125 Gbps 0.19 0.30 UIP-P Note 11: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 12: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 13: Specification is guaranteed by characterization and is not tested in production. Note 14: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 15: tSKD2, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. Note 16: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically. Note 17: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted algebraically. Note 18: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted. 7 www.national.com DS25BR100 / DS25BR101

Test Channel Loss Characteristics The test channel was fabricated with Polyclad PCL-FR-370- Laminate/PCL-FRP-370 Prepreg materials (Dielectric con- stant of 3.7 and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries: Trace Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils. Test Channel Length (inches) Insertion Loss (dB)

500 MHz 750 MHz 1000 MHz 1250 MHz 1500 MHz 1560 MHz

The DS25BR100/101 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the DS25BR100/101 can be DC-coupled with all common dif- ferential drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to com- mon differential drivers. The DS25BR100 inputs are internally terminated with a 100Ω resistor for optimal device performance, reduced com- ponent count, and minimum board space. External input ter- minations on the DS25BR101 need to be placed as close as possible to the device inputs to achieve equivalent AC per- formance. It is recommended that SMT resistors sized 0402 or smaller be used and the mounting distance to the DS25BR101 pins kept under 200 mils. When using the DS25BR101 in a limited multi-drop topology, any transmission line stubs should be kept very short to min- imize any negative effects on signal quality. A single termi- nation resistor or resistor network that matches the differential line impedance should be used. If DS25BR101 input pairs from two separate devices are to be connected to a single differential output, it is recommended that the DS25BR101 devices are mounted directly opposite of each other. One on top of the PCB and the other directly under the first on the bottom of the PCB, this keeps the distance between inputs equal to the PCB thickness. 20179111 Typical LVDS Driver DC-Coupled Interface to DS25BR100 Input 20179112 Typical CML Driver DC-Coupled Interface to DS25BR100 Input www.national.com 10 DS25BR100 / DS25BR101

Typical LVPECL Driver DC-Coupled Interface to DS25BR100 Input Note: DS25BR101 requires external 100Ω input termination. 11 www.national.com DS25BR100 / DS25BR101

The DS25BR100/101 outputs signals compliant to the LVDS standard. It can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers and assumes that the receivers have high impedance inputs. While most differ- ential receivers have a common mode input range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation. 20179114 Typical Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver www.national.com 12 DS25BR100 / DS25BR101

Maximum Data Rate as a Function of CAT5e (Belden 1700A) Length 20179130 A 2.5 Gbps NRZ PRBS-7 After 60" Differential FR-4 Stripline V:125 mV / DIV, H:75 ps / DIV 20179132 A 3.125 Gbps NRZ PRBS-7 After 60" Differential FR-4 Stripline V:125 mV / DIV, H:50 ps / DIV 20179135 Maximum Data Rate as a Function of CAT5e (Belden 1700A) Length 20179131 An Equalized (with PE and EQ) 2.5 Gbps NRZ PRBS-7 After The 40" Input and 20" Output Differential Stripline (Figure 5) V:125 mV / DIV, H:75 ps / DIV 20179133 An Equalized (with PE and EQ) 3.125 Gbps NRZ PRBS-7 After The 40" Input and 20" Output Differential Stripline (Figure 5) V:125 mV / DIV, H:50 ps / DIV 13 www.national.com DS25BR100 / DS25BR101

Total Jitter as a Function of Data Rate 20179139 Total Jitter as a Function of Input Amplitude 20179136 Power Supply Current as a Function of Frequency 20179138 Total Jitter as a Function of Data Rate 20179140 Total Jitter as a Function of Input Amplitude www.national.com 14 DS25BR100 / DS25BR101

Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS25BR100TSD Order Number DS25BR101TSD (See AN-1187 for PCB Design and Assembly Recommendations) 15 www.national.com DS25BR100 / DS25BR101

DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive EqualizationFor more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy PowerWise® Solutions www.national.com/powerwise Solutions www.national.com/solutions Serial Digital Interface (SDI) www.national.com/sdi Mil/Aero www.national.com/milaero Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless PowerWise® Design University www.national.com/training THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2009 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Technical Support Center Email: support@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Technical Support Center Email: europe.support@nsc.com National Semiconductor Asia Pacific Technical Support Center Email: ap.support@nsc.com National Semiconductor Japan Technical Support Center Email: jpn.feedback@nsc.com www.national.com