DS250DF230RTVR

DS250DF230_V01 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 105

Technical content

CAL_CLK_IN CAL_CLK_OUT ADDR0 ADDR1 TEST0 /RCK0 SDC(1) READ_EN_N ALL_DONE_N SDA(1) INT_N TX0P TX0N TX1P TX1N GND (1) SMBus signals need to be pulled up elsewhere in the system.

30.72 MHz or 25 MHz

7RQH[WGHYLFH¶V CAL_CLK_IN Float for SMBus Slave mode, or connect to next GHYLFH¶V5($'_EN_N for SMBus Master mode 2.5V or 3.3V To other open-drain interrupt pins VDD 0.01 F (2x) 0.1 F (2x) SMBus Slave mode SMBus Slave mode 2.5 V RX EN_SMB Address straps (pull-up, pull- down, or float) 1 NŸ To system SMBus CDR TX RX TX THR /TEST1 X CDR Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS250DF230 SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 DS250DF23025-GbpsMulti-Rate2-ChannelRetimer

1 Features

1• Dual-channel multi-rate retimer with integrated signal conditioning

• All channels lock independently from 19.6 to 25.8 Gbps (including sub-rates, such as 12.16512 Gbps, 9.8304 Gbps, 6.144 Gbps, and more)
• Ultra-low latency: <500 ps Typical for 25.78125- Gbps data rate
• Adaptive continuous time linear equalizer (CTLE)
• Continuous adaptive decision feedback equalizer (DFE), capable of compensating large channel loss variation over temperature
• Combined equalization supporting 35-dB channel loss at 12.9 GHz
• On-chip eye-opening monitor (EOM), PRBS pattern checker and generator
• Low-jitter transmitter with 3-Tap FIR filter
• Integrated 2×2 cross-point
• Recovered clock available for system clock synchronization applications on channel 0
• Single power supply, no low-jitter reference clock required
• Wide stay-in-lock temperature range

2 Applications

• Jitter cleaning for front-port optical interface in wireless and wired systems
• Backplane/mid-plane reach extension
• Active cable assemblies
• 802.3bj 100GbE, InfiniBand EDR, and OIF-CEI- 25G-LR/MR/SR/VSR electrical interfaces
• SFP28, QSFP28, CFP2/CFP4, CDFP

3 Description

The DS250DF230 is a dual-channel multi-rate retimer with integrated signal conditioning. The device is used to extend the reach and robustness of long, lossy, crosstalk-impaired high-speed serial links and while achieving a bit error rate (BER) of 10–15 or less. Each channel of the DS250DF230 independently locks to serial data rates in a continuous range from 19.6 Gbps to 25.8 Gbps or to any supported sub-rate (÷2 and ÷4), including key data rates such as 12.16512 Gbps, 9.8304 Gbps, 6.144 Gbps. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DS250DF230 NFBGA (36) 5.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic

SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 www.ti.com Product Folder Links: DS250DF230 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Table of Contents

12.3 Receiving Notification of Documentation Updates 94

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2018) to Revision B Page

www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated

5 Description (continued)

The DS250DF230 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and BOM cost. The advanced equalization features of the DS250DF230 include a low-jitter 3-tap transmit finite impulse response (FIR) filter, an adaptive continuous-time linear equalizer (CTLE), and an adaptive decision feedback equalizer (DFE). This enables reach extension for lossy interconnect and backplanes with multiple connectors and crosstalk. The integrated CDR function is available for front-port optical module applications to reset the jitter budget and retime the high-speed serial data. The DS250DF230 supplies 2x2 cross-point that gives the host lane crossing, fanout, and multiplexing options. The DS250DF230 can be configured either through the SMBus or through an external EEPROM. Up to 16 devices can share an EEPROM using common-channel configuration. A non-disruptive on-chip eye monitor and a PRBS generator and checker is available for in-system diagnostics.

SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 www.ti.com Product Folder Links: DS250DF230 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

6 Pin Configuration and Functions

DESCRIPTION

NO. NAME HIGH-SPEED DIFFERENTIAL I/Os A6 RX0P Input None Inverting and noninverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects RXP to RXN. These inputs must be AC-coupled.A5 RX0N Input None A2 RX1P Input None Inverting and noninverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects RXP to RXN. These inputs must be AC-coupled.A1 RX1N Input None F6 TX0P Output None Inverting and noninverting 50Ω driver outputs. These outputs must be AC- coupled.F5 TX0N Output None F2 TX1P Output None Inverting and noninverting 50Ω driver outputs. These outputs must be AC- coupled.F1 TX1N Output None CALIBRATION CLOCK PINS D6 CAL_CLK_IN Input, 2.5V LVCMOS None 30.72-MHz (±100 PPM), 2.5-V single-ended clock from external oscillator. No stringent phase noise or jitter requirements on this clock. Also supports 25-MHZ (±100 PPM) clock by programming the corresponding registers. D1 CAL_CLK_OUT Output, 2.5V LVCMOS None 2.5-V buffered replica of calibration clock input (CAL_CLK_IN) for connecting multiple (up to 20 or more) devices in a daisy-chained fashion.

www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE INTERNAL PULL-UP/ PULL- DOWN NO. NAME SYSTEM MANAGEMENT BUS (SMBus) PINS C1 ADDR0 Input, 4-level None 4-level strap pins used to set the SMBus address of the device. The pin state is read on power-up. The multi-level nature of these pins allows for 16 unique device addresses. The four strap options include: 0: 1 kΩ to GND R: 10 kΩ to GND F: Float 1: 1 kΩ to VDD Refer to Device SMBus Address for more information. B4 ADDR1 Input, 4-level None C6 EN_SMB Input, 4-level None Four-level, 2.5-V input used to select between SMBus master mode (float) and SMBus slave mode (high). The three defined levels are: R: 10 kΩ to GND - RESERVED, TI test mode F: Float - SMBus Master Mode (2.5-V/3.3-V SMBUS interface only) 1: 1 kΩ to VDD - SMBus Slave Mode D5 THR /TEST1 Input, 4-level None Select the electrical voltage of SMBus interface. 2.5-V/3.3-V or 1.8-V: 1: 1 kΩ to VDD - 1.8-V SMBus interface F: Float - 1.8-V SMBus interface 0: 1 kΩ to GND - 2.5-V/3.3-V SMBus interface In TI test mode (EN_SMB = 10k Ohm to GND), this is reserved TI test pin. D2 SDA I/O, Open Drain None SMBus data input / open-drain output. External 2-kΩ to 5-kΩ pullup resistor is required as per SMBus interface standard. This pin is 3.3-V tolerant. C2 SDC I/O, Open Drain None SMBus clock input / open-drain clock output. External 2-kΩ to 5-kΩ pullup resistor is required as per SMBus interface standard. This pin is 3.3-V tolerant. SMBus MASTER MODE PINS E3 ALL_DONE_N Output, 2.5-V LVCMOS None Indicates the completion of a valid EEPROM register load operation when in SMBus Master Mode (EN_SMB=Float): High = External EEPROM load failed or incomplete Low = External EEPROM load successful and complete When in SMBus slave mode (EN_SMB=1), this output reflects the status of the READ_EN_N input. E4 READ_EN_N Input, 3.3-V LVCMOS Weak pullup to VDD SMBus Master Mode (EN_SMB=Float): When asserted low, initiates the SMBus master mode EEPROM read function. Once EEPROM read is complete (indicated by assertion of ALL_DONE_N low), this pin can be held low for normal device operation. SMBus Slave Mode (EN_SMB=1): When asserted low, this causes the device to be held in reset (SMBus state machine reset and register reset). This pin must be pulled high or left floating for normal operation in SMBus Slave Mode. This pin is 3.3-V tolerant. MISCELLANEOUS PINS B3 INT_N Output, Open- Drain None Open-drain, 3.3-V tolerant active-low interrupt output. It pulls low when an interrupt occurs. The events which trigger an interrupt are programmable through SMBus registers. This pin can be connected in a wired-OR fashion with other device's interrupt pin. A single pullup resistor in the 2-kΩ to 5-kΩ range is adequate for the entire INT_N net. C5 TEST0 /RCK0 I/O, 2.5-V LVCMOS None In TI test mode (EN_SMB = 10k Ohm to GND), this is reserved TI test pin. During normal (non-test-mode) operation, this pin is configured as input by default and therefore is not affected by the presence of a signal. This pin may be left floating, tied to GND, or connected to a 2.5-V (max) output. This pin can be configured to offer the recovered clock for CH0 by programming the corresponding registers. The signal is 2.5-V LVCMOS. POWER C3,C4, D3,D4 VDD Power None Power supply, VDD = 2.5 V ±5%. TI recommends connecting at least four de-coupling capacitors between the Retimer VDD plane and GND as close to the Retimer as possible. For example, two 0.1-µF capacitors, and two 0.01-µF capacitors directly beneath the device or as close to the VDD pins as possible. The VDD pins on this device must be connected through a low- resistance path to the board VDD plane.

SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 www.ti.com Product Folder Links: DS250DF230 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE INTERNAL PULL-UP/ PULL- DOWN NO. NAME A3,A4, B1,B2, B5,B6, E1,E2, E5,E6,F 3,F4 GND Power None Ground reference. The GND pins on this device must be connected through a low-resistance path to the board GND plane.

www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDDABSMAX Supply Voltage, VDD to GND –0.5 2.75 V VIO2.5V-ABSMAX 2.5V I/O voltage (LVCMOS and Analog) –0.5 2.75 V VIO3.3V-ABSMAX 3.3V I/O Voltage (SDA, SDC, INT_N, READ_EN) –0.5 4 V VINABSMAX Signal Input voltage(RXnP, RXnN) –0.5 2.75 V VOUTABSMAX Signal Output voltage(TXnP, TXnN) –0.5 2.75 V TJABSMAX Junction Temperature 150 °C Tstg Storage Temperature range –40 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000 (1) Steps must be taken to ensure the combined AC plus DC noise meets the VDD supply voltage limits. (2) Steps must be taken to ensure the operating junction temperature range and stay-in-lock range (TEMPLOCK+ ,TEMPLOCK-) are met. Refer to the Electrical Characteristics for more details concerning TEMPLOCK+ and TEMPLOCK-. (3) Set THR pin to select SMBUS electrical voltage

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage, VDD to GND.DC plus AC power should not exceed these limits. 2.375 2.5 2.625 V NVDD Supply noise, DC to <50 Hz, sinusoidal(1) 250 mVpp NVDD Supply noise, 50 Hz to 10 MHz, sinusoidal(1) 20 mVpp NVDD Supply noise, >10 MHz, sinusoidal(1) 10 mVpp Tramp VDD supply ramp time, from 0 V to 2.375 V 150 us TJ Operating junction temperature –40 110 °C TA Operating ambient temperature –40 85(2) °C VIO3.3V,INT_N Open Drain I/O voltage(INT_N) 3.6 V VIO3.3V Open Drain I/O voltage(SDA,SDC)(3) 3.6 V

SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 www.ti.com Product Folder Links: DS250DF230 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) No heat sink or airflow was assumed for these estimations. Depending on the application, a heat sink, faster airflow, and/or reduced ambient temperature (<85 C) may be required in order to meet the maximum junction temperature specification per the Recommended Operating Conditions.

7.4 Thermal Information

THERMAL METRIC(1) CONDITIONS(2) DS250DF230 UNITZLS (NFBGA)

36 PINS

RθJA Junction-to-ambient thermal resistance 4-layer JEDEC board 49.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 4-layer JEDEC board 20.7 °C/W RθJB Junction-to-board thermal resistance 4-layer JEDEC board 24.5 °C/W ΨJT Junction-to-top characterization parameter 4-layer JEDEC board 0.5 °C/W ΨJB Junction-to-board characterization parameter 4-layer JEDEC board 24.7 °C/W

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER CONSUMPTION WChannel Power Consumption Per Active Channel Active mode with CTLE, Tx FIR, full DFE and Crosspoint enabled. Idle power consumption not included. 256 347 mW Active mode with CTLE, Tx FIR, and full DFE enabled. Crosspoint disabled. Idle power consumption not included. 248 mW Active mode with CTLE, Tx FIR, and partial DFE enabled(taps 1-2 only). Crosspoint and DFE taps 3-5 disabled. Idle power consumption not included. 235 mW Active mode with CTLE, and Tx FIR enabled. DFE and crosspoint disabled. Idle power consumption not included. 226 mW Assuming CDR acquiring lock with CTLE, full DFE, Tx FIR, Driver, and Crosspoint enabled. Idle power consumption not included. 380 445 mW Assuming CDR acquiring lock with CTLE, full DFE, Tx FIR, Driver, and Crosspoint disabled. Idle power consumption not included. 333 mW WPRBS PRBS Checker Power Consumption only Per Channel 200 mW PRBS Generator Power Consumption only Per Channel 190 mW WStatic_Total Total Idle Power Consumption Idle/Static mode. Power supplied, no high- speed data present at inputs, channel automatically powered down. 165 mW IStatic_Total Idle mode total device supply current consumption Idle/Static mode. Power supplied, no high- speed data present at inputs, channel automatically powered down. 66 100 mA ITotal Active Mode Total Device Supply Current Consumption Active mode with CTLE, Tx FIR, full DFE and Crosspoint enabled. 271 361 mA Active mode with CTLE, Tx FIR, and full DFE enabled. Crosspoint disabled. 265 mA Active mode with CTLE, Tx FIR, and partial DFE enabled(taps 1-2 only). Crosspoint and DFE taps 3-5 disabled. 255 mA Active mode with CTLE, and Tx FIR enabled. DFE and crosspoint disabled. 247 mA

www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) From low assertion of READ_EN_N to low_assertion of ALL_DONE_N. Does not include Power-On Reset time GENERAL DEVICE-LEVEL SPECIFICATIONS Rbaud Supported input data rate Full-rate (divide-by-1) mode of operation. 19.6 25.8 Gbps Half-rate (divide-by-2) mode of operation. 9.8 12.9 Gbps Quarter-rate (divide-by-4) mode of operation. 4.9 6.45 Gbps tEEPROM EEPROM configuration load time Single device reading its configuration from an EEPROM. Common channel configuration. This time scales with the number of devices reading from the same EEPROM. 15(1) ms EEPROM configuration load time Single device reading its configuration from an EEPROM. Unique-channel configuration. This time scales with the number of devices reading from the same EEPROM. 40(1) ms tPOR Power-on reset assertion-time Internal power-on reset (PoR) stretch between stable power supply and de- assertion of internal PoR. The SMBus address is latched on the completion of the PoR stretch, and SMBus accesses are permitted. 50 ms HIGH-SPEED DIFFERENTIAL OUTPUTS (TXnP, TXnN) VOD Output differential voltage amplitude Measured with c(0)=4 setting (REG_0x3D[6:0]=0x04, REG_0x3E[6:0]=0x40, REG_0x3F[6:0]=0x40). Differential measurement using an 8T pattern (eight 1s followed by eight 0s) at 25.78125 Gbps with TXPn and TXNn terminated by 50 Ohms to GND. 392 mVppd Output differential voltage amplitude Measured with c(0)=31 setting (REG_0x3D[6:0]=0x1F, REG_0x3E[6:0]=0x40, REG_0x3F[6:0]=0x40). Differential measurement using an 8T pattern (eight 1s followed by eight 0s) at 25.78125 Gbps with TXPn and TXNn terminated by 50 Ohms to GND. 1195 mVppd VOD_Raw_L Output differential voltage amplitude under Raw Mode, low swing setting Raw Mode(CDR Bypassed), low swing setting(REG_0xD[0]=0), differential measurement using 8T pattern(eight 1s followed by eight 0s) at 25.78125Gbps and 9.8304Gbps with TXPn and TXNn terminated by 50 Ohms to GND. RPH=REG_0x1A[7:6]=0 602 mVppd VOD_Raw_H Output differential voltage amplitude under Raw Mode, high swing setting Raw Mode(CDR Bypassed), high swing setting(REG_0xD[0]=1),,differential measurement using 8T pattern(eight 1s followed by eight 0s) at 25.78125Gbps and 9.8304Gbps with TXPn and TXNn terminated by 50 Ohms to GND. RPH=REG_0x1A[7:6]=0x3 919 mVppd VOD_Idle Differential output amplitude with TX disabled 6.1 mVppd

SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 www.ti.com Product Folder Links: DS250DF230 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) Measured with an evaluation board which uses microstrip traces and low-loss dielectric with approximately 4 dB insertion loss at 12.9 GHZ between DS250DF230 and the measurement instrument. Vcm_TX DC common-mode output voltage With respect to signal ground. Measured using an 8T pattern (eight 1s followed by eight 0s) at 25.78125 Gbps with TXPn and TXNn terminated by 50 Ohms to GND. Measured for c(-1)=c(1)=0 and VOD settings in the range of 600 mVppd to 1200 mVppd. 1.01 V Vcm_TX_AC Common-mode AC output noise With respect to signal ground. Measured with PRBS9 data pattern. Measured with a 33GHz (-3dB) low-pass filter. 7.4 mV, RMS tr, tf Output transition-time 20%-to-80% rise time and 80%-to-20% fall time on a clock-like {11111 00000} data pattern at 25.78125 Gbps. Measured for ~750 mVppd output amplitude and no equalization: REG_0x3D=+13, REG_0x3E=0, REG_0x3F=0 17.5 ps Output transition-time, Low slew rate setting Slow slew rate setting(REG_0x3D[5]=1), 20%-to-80% rise time and 80%-to-20% fall time on a clock-like {11111 00000} data pattern at 9.8304 Gbps. Measured for ~750 mVppd output amplitude and no equalization: REG_0x3D=+13, REG_0x3E=0, REG_0x3F=0 24 ps RLSDD22 Differential output return loss, SDD22(2) Between 50 MHz and 5 GHz -15.9 dB Differential output return loss, SDD22(2) Between 5 GHz and 12.9 GHz -13 dB RLSCD22 Differential to common-mode output return loss, SCD22(2) Between 50 MHz and 12.9 GHz -24 dB RLSDC22 Common-mode to differential output return loss, SDC22(2) Between 50 MHz and 12.9 GHz -24 dB RLSCC22 Common-mode output return loss, SCC22(2) Between 50 MHz and 10 GHz -8 dB Common-mode output return loss, SCC22(2) Between 10 GHz and 12.9 GHz -8.5 dB RETIMER TIMING SPECIFICATIONS tD Input-to-output latency (propagation delay) through a channel No Crosspoint; CDR enabled and locked. 4.5 UI + 175 ps ps Crosspoint enabled; CDR enabled and locked.

4.5 UI +

No crosspoint; CDR in raw mode. 140 ps tD_V Variation of Input-to-output latency Crosspoint enabled; CDR enabled and locked. ± 50 ps tSK Channel-to-channel interpair skew Latency difference between channels at full-rate. 30 ps tLock CDR lock acquisition-time Measured at 25.78125 Gbps, Adapt mode 2(REG_0x31[6:5]=0x2) <100 ms CDR lock acquisition-time, Fast Lock Mode Measured at 25.78125 Gbps, Adapt mode 2(REG_0x31[6:5]=0x2). Fast Lock Mode Enabled(REG_0xAC[7] = 1). Adaptation process still runs to find the best CTLE/DFE values after CDR lock declares <10 ms CDR lock acquisition-time, Fast Lock Mode Measured at 25.78125 Gbps, Adapt mode 0(Reg_0x31[6:5]=0x0), Fast Lock Mode Enabled(REG_0xAC[7] = 1) <2 ms

www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (3) Measured with an evaluation board which uses microstrip traces and low-loss dielectric with approximately 4 dB insertion loss at 12.9 GHZ between DS250DF230 and the measurement instrument. RETIMER JITTER SPECIFICATIONS JTJ Output Total jitter (TJ) Measured at 25.78125 Gbps to a probability level of 1E-12 with PRBS11 data pattern an evaluation board traces de-embedded

0.16 UIpp @

JRJ Output Random Jitter (RJ) Measured at 25.78125 Gbps to a probability level of 1E-12 with PRBS11 data pattern an evaluation board traces de-embedded 6.8 mUI RMS JDCD Output Duty Cycle Distortion (DCD) Measured at 25.78125 Gbps to a probability level of 1E-12 with PRBS11 data pattern an evaluation board traces de-embedded 3.7 mUIpp HIGH-SPEED DIFFERENTIAL INPUTS (RXnP, RXnN) VIDMax Maximum tolerable input differential voltage For normal operation 1200 mVppd Vcm-Self Self-generated input common mode 1.79 V RLSDD11 Differential input return loss, SDD11(3) Between 50 MHz and 3.69 GHz -20 dB Differential input return loss, SDD11(3) Between 3.69 GHz and 12.9 GHz -13 dB RLSDC11 Common-mode to differential input return loss, SDC11(3) Between 50 MHz and 12.9 GHz -23 dB RLSCD11 Differential to common-mode input return loss, SCD11(3) Between 50 MHz and 12.9 GHz -23 dB RLSCC11 Common-mode input return loss, SCC11(3) Between 150 MHz and 10 GHz -11 dB Common-mode input return loss, SCC11(3) Between 10 GHz and 12.9 GHz -8 dB VSDAT AC signal detect assert (ON) threshold level Minimum input peak-to-peak amplitude level at device pins required to assert signal detect. Assumes default assert threshold setting. Measured at 25.78125 Gbps with PRBS7. 145 mVppd VSDDT AC signal detect de-assert (OFF) threshold level Maximum input peak-to-peak amplitude level at device pins which causes signal detect to de-assert. Assumes default de- assert threshold setting . Measured at 25.78125 Gbps with PRBS7. 84 mVppd RETIMER CLOCK AND DATA RECOVERY SPECIFICATIONS BWPLL PLL bandwidth Measured at 9.8304 Gbps with PRBS7 data pattern 4 MHz PLL bandwidth Measured at 25.78125 Gbps with PRBS7 data pattern 4.7 MHz JPEAK Jitter peaking Measured at 9.8304 Gbps with PRBS7 data pattern. 0.5 dB Jitter peaking Measured at 25.78125 Gbps with PRBS7 data pattern. 0.5 dB

SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 www.ti.com Product Folder Links: DS250DF230 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (4) Measured with input data from DS280DF810 evaluation board, at 24.33024 Gbps or 10.1376 Gbps or 25.78125Gbps or 10.3125 Gbps JTOL Input jitter tolerance Measured at 25.78125 Gbps with SJ frequency = 190 KHz, 30dB input channel loss, PRBS31 data pattern, ~800 mVppd launch amplitude, and 0.18 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12.

9 UIpp

Measured at 25.78125 Gbps with SJ frequency = 940 KHz, 30dB input channel loss, PRBS31 data pattern, ~800 mVppd launch amplitude, and 0.18 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12.

1 UIpp

Measured at 25.78125 Gbps with SJ frequency > 15MHz, 30dB input channel loss, PRBS31 data pattern, ~800 mVppd launch amplitude, and 0.18 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12.

0.33 UIpp

temperature range, negative ramp. Maximum junction temperature change below initial CDR lock acquisition temperature 110 °C junction temperature starting, ramp rate -3°C/minute, 12 layer PCB 150 °C TEMPLOCK+ CDR stay-in-lock junction temperature range, positive ramp. Maximum junction temperature change above initial CDR lock acquisition temperature -40 °C junction temperature starting, ramp rate +3°C/minute, 12 layer PCB 150 °C RECOVERED CLOCK SPECIFICATIONS RCKf Recovered Clock frequency on RCK0 pin Measured with input data rate as 24.33024 Gbps or 12.16512 Gbps or 10.1376 Gbps 9.8304 Gbps or 6.144 Gbps or 4.9152 Gbps

30.72 MHz

Recovered Clock frequency on RCK0 pin Measured with input data rate as 25.78125Gbps or 10.3125Gbps 32.2265625 MHz RCKPhase RCKf Phase Noise Performance(4) <=100 Hz < -59 dBc/Hz Between 100 Hz and 1 kHz < -84 dBc/Hz Between 1 kHz and 10 kHz < -103 dBc/Hz >10 kHz < -122 dBc/Hz CALIBRATION CLOCK SPECIFICATIONS CLKf Calibration clock frequency Option 1: 30.72 MHZ 30.72 MHz Calibration clock frequency Option 2: 25 MHZ 25 MHz CLKppm Calibration clock PPM tolerance -100 100 PPM CLKIDC Calibration clock input duty cycle 40 50 60 Percent CLKODC Intrinsic calibration clock duty cycle distortion Intrinsic duty cycle distortion of chip calibration clock output at the CAL_CLK_OUT pin, assuming 50% duty cycle on CAL_CLK_IN pin. 45 50 55 Percent CLKnum Number of devices which can be cascaded from CAL_CLK_OUT to CAL_CLK_IN Assumes worst-case 60%/40% input duty cycle on the first device. CAL_CLK_OUT from first device connects to CAL_CLK_IN of second device, and so on until the last device.

20 N/A

www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVCMOS DC SPECIFICATIONS VIH Input high-level voltage 2.5 V LVCMOS pins 1.75 VDD V 3.3 V LVCMOS pin (READ_EN_N) 1.75 3.6 V VIL Input low-level voltage 2.5 V LVCMOS pins GND 0.7 V 3.3 V LVCMOS pin (READ_EN_N) GND 0.8 V Vth High-level(1) input voltage 4-level pins ADDR0, ADDR1, EN_SMB and THR 0.98 x VDD V Float level input voltage 4-level pins ADDR0, ADDR1, EN_SMB and THR 0.69 x VDD V 10K to GND input voltage 4-level pins ADDR0, ADDR1, EN_SMB and THR 0.25 x VDD V Low-level (0) input voltage 4-level pins ADDR0, ADDR1, EN_SMB and THR 0.1 V VOH High-level output voltage IOH = 4mA 2 V VOL Low-level output voltage IOL = -4mA 0.4 V IIH Input high leakage current Vinput = VDD, Open drain pins 70 uA Input high leakage current Vinput = VDD and CAL_CLK_IN pins 65 uA Input high leakage current Vinput = VDD, ADDR[1:0] and EN_SMB pins 65 uA Input high leakage current Vinput = VDD, READ_EN_N 15 uA IIL Input low leakage current Vinput = 0V, Open drain pins –15 uA Input low leakage current Vinput = 0V, CAL_CLK_IN pins –15 uA Input low leakage current Vinput = 0V, ADDR[1:0], READ_EN_N, and EN_SMB pins –115 uA

7.6 Timing Requirements

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT SMBus ELECTRICAL CHARACTERISTICS (SLAVE MODE) VIH Input high-level voltage 1.8 V SMBUS Interface SDA and SDC 1.35 3.6 V VIH Input high-level voltage 2.5 V/3.3 V SMBUS Interface SDA and SDC 1.75 3.6 V VIL Input low-level voltage SDA and SDC GND 0.8 V CIN Input pin capacitance 2 pF VOL Low-level output voltage SDA or SDC or INT, IOL = 1.25 mA 0.4 V IIN Input current SDA or SDC, VINPUT = VIN, VDD, GND –15 15 uA TR SDA rise time, read operation Pull up resistor = 1 kΩ, Cb = 50pF 150 ns TF SDA fall time, read operation Pull up resistor = 1 kΩ, Cb = 50pF 4.5 ns RECOMMENDED SMBus SWITCHING CHARACTERISTICS (SLAVE MODE) fSDC SDC clock frequency 10 100 400 kHz tHD_DAT Data hold time 0.75 ns tSU_DAT Data setup time 100 ns

SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 www.ti.com Product Folder Links: DS250DF230 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

7.7 Switching Characteristics

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT SMBus SWITCHING CHARACTERISTICS (2.5 V and 3.3 V MASTER MODE) fSDC SDC clock frequency 260 303 346 kHz TLOW SDC low period 1.90 µs THIGH SDC high period 1.40 µs THD_STA Hold time start operation 1.3 µs TSU_STA Setup time start operation 1.3 µs THD_DAT Data hold time 0.5 µs TSD-DAT Data setup time 1.3 µs TSU_STO Stop condition setup time 1.4 µs TBUF Bus free time between Stop-Start 1.8 µs TR SDC rise time Pull up resistor = 1 kΩ 70 ns TF SDC fall time Pull up resistor = 1 kΩ 8 ns

7.8 Typical Characteristics

Figure 1. Output Transition-time vs Ambient Temperature Figure 2. Typical VOD vs Ambient Temperature Figure 3. Typical VOD vs FIR Main-Cursor Figure 4. Typical Output Jitter vs Ambient Temperature Figure 5. Typical Sinusoidal Input Jitter Tolerance for Figure 6. Typical Input Jitter Tolerance for

PFD, CDR, and Divider VCO PRBS Driver TXnP TXnN Channel Digital Core CAL_CLK_IN CAL_CLK_OUT Shared Digital Core Power-On Reset Always-On 10MHz PRBS Checker Eye Monitor Signal Detect SCL SDA READ_EN_N ALL_DONE_N INT_N Voltage Regulator Voltage Regulator EN_SMB One of two channels ADDRn Buffer point To adjacent channel Shared Digital Core Term DS250DF230 SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 www.ti.com Product Folder Links: DS250DF230 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The DS250DF230 is a dual-channel multi-rate retimer with integrated signal conditioning. Each of the two channels operates independently. Each channel includes a continuous-time linear equalizer (CTLE) and a Decision Feedback Equalizer (DFE), which together compensate for the presence of a dispersive transmission channel between the source transmitter and the DS250DF230 receiver. The CTLE and DFE are self-adaptive. Each channel includes an independent voltage-controlled oscillator (VCO) and phase-locked loop (PLL) which produce a clean clock that is frequency-locked to the clock embedded in the input data stream. The high- frequency jitter on the incoming data is attenuated by the PLL, producing a clean clock with substantially reduced jitter. This clean clock is used to re-time the incoming data, removing high-frequency jitter from the data stream and reproducing the data on the output with significantly reduced jitter. Each channel of the DS250DF230 features an output driver with adjustable differential output voltage and output equalization in the form of a three-tap finite impulse response (FIR) filter. The output FIR compensates for dispersion in the transmission channel at the output of the DS250DF230. A full 2x2 cross-point switch is integrated inside. This allows multiplexing and de-multiplexing/fanout applications for fail-over redundancy, as well as cross-over applications to aid PCB routing. Each channel also includes diagnostic features such as a Pseudo-Random Bit Sequence (PRBS) pattern generator and checker, as well as a non-destructive, eye-opening monitor (EOM). The EOM can be used to plot the post-equalized eye at the input to the decision slicer or simply to read the horizontal eye opening (HEO) and vertical eye opening (VEO). The DS250DF230 is configurable through a single SMBus port. The DS250DF230 can also act as an SMBus master to configure itself from an external EEPROM. Up to sixteen DS250DF230 devices can share a single SMBus. The sections which follow describe the functionality of various circuits and features within the DS250DF230. For more information about how to program or operate these features, consult the DS250DF230 Programmer's Guide (SNLU182).

8.2 Functional Block Diagram

www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Device Data Path Operation

The DS250DF230 data path consists of several key blocks as shown in the functional block diagram. These key circuits are:

• Signal Detect
• Continuous Time Linear Equalizer (CTLE)
• Variable Gain Amplifier (VGA)
• Cross-Point Switch
• Decision Feedback Equalizer (DFE)
• Clock and Data Recovery (CDR)
• Calibration Clock
• Differential Driver With FIR Filter

8.3.2 Signal Detect

The DS250DF230 receiver contains a signal detect circuit. The signal detect circuit monitors the energy level on the receiver inputs and powers on or off the rest of the high-speed data path if a signal is detected or not. By default, each channel allows the signal detect circuit to automatically power on or off the rest of the high-speed data path depending on the presence of an input signal. The signal detect block can be manually controlled in the SMBus channel registers. This can be useful if it is desired to manually force channels to be disabled. For information on how to manually operate the signal detect circuit, refer to the DS250DF230 Programmer's Guide (SNLU182).

8.3.3 Continuous Time Linear Equalizer (CTLE)

The CTLE in the DS250DF230 is a fully-adaptive equalizer. The CTLE adapts according to a Figure of Merit (FOM) calculation during the lock acquisition process. The FOM calculation is based upon the horizontal eye opening (HEO) and vertical eye opening (VEO). Once the CDR locks and the CTLE adapts, the CTLE boost level is frozen until a manual re-adapt command is issued or until the CDR re-enters the lock acquisition state. The CTLE can be re-adapted by resetting the CDR. The CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for many boost combinations, including bypassing the first three stages EQs. The CTLE adaption algorithm allows the CTLE to adapt through 20 of these boost combinations. These 20 boost combinations comprise the EQ Table in the channel registers. See channel registers 0x40 through 0x53. The boost levels can be set between approximately 0 dB and 25 dB (at 12.89 GHz.)

8.3.4 Variable Gain Amplifier (VGA)

The DS250DF230 receiver implements a VGA. The VGA assists in the recovery of extremely small signals, working in conjunction with the CTLE to equalize and scale amplitude. The VGA has 1-bit control through Reg_0x8E[0], and the VGA is in the low-gain state (Reg_0x8E[0]=0) by default. In addition to the VGA, the CTLE implements its own gain control through Reg_0x13[5] to adjust the DC amplitude similar to the VGA. For more information on how to configure the VGA and EQ gain, refer to the DS250DF230 Programmer's Guide (SNLU182).

8.3.5 Cross-Point Switch

DS250DF230 has a 2×2 cross-point that may be enabled to implement a 2-to-1 mux, a 1-to-2 fanout, or an A-to- B/B-to-A lane cross.

8.3.6 Decision Feedback Equalizer (DFE)

adapt continuously. The DFE can also be manually configured to specified tap polarities and tap weights. Table 1. DFE Tap Weights for positive-sign, post-cursor ISI.

8.3.7 Clock and Data Recovery (CDR)

that allow for retimed data, non-retimed data, a PRBS generator, and output muted modes. (typical) in full-rate (divide-by-1) mode and 4 MHz (typical) in sub-rate mode. The CDR bandwidth is adjustable.

• A 30.72-MHZ or 25-MHz calibration clock to run the PPM counter (CAL_CLK_IN).
• Expected data rates must be programmed into the CDR either through the rate table or entered manually with the corrected divider settings. Refer to the DS250DF230 Programmer's Guide (SNLU182) for more information on configuring the CDR for different data rates. The DS250DF230 offers a low-speed recovered clock for channel 0. This feature is useful for the cases when recovered clock from FPGA or ASIC has in-band spurs on the phase noise plot because of the digital switching noise. See the Table 6 for the recovered clock frequency versus input data rate. The DS250DF230 offers fast lock option, so that the CDR Lock time can be as fast as 2 ms. See CDR lock time parameter in Electrical Characteristics When DS250DF230 is configured to Raw mode(CDR bypassed), the output differential voltage amplitude of the transmitter is adjustable. See the VOD_Raw_L and VOD_Raw_H parameters from Electrical Characteristics. When switching from Raw mode to Retimed mode(CDR Enabled), REG_0x1A[7:6] and REG_0x0D[0] values need to be changed back to default. Refer to the DS250DF230 Programmer's Guide (SNLU182) for more information.

8.3.8 Calibration Clock

lock ranges of the CDR according to the programmed values in the rate table or the manually entered data rates. used for clock and data recovery, thus there are no stringent jitter requirements placed on this calibration clock.

8.3.9 Differential Driver With FIR Filter

and C[+1] can take on values in the range [-15, 15]. Figure 7. FIR Filter Functional model

• |C[-1]| + |C[0]| + |C[+1]| ≤ 31; the FIR tap coefficients absolute sum must be less or equal to 31
• sgn(C[-1]) = sgn(C[+1]) ≠ sgn(C[0]), for high-pass filter effect; the sign for the pre-cursor and/or post-cursor tap must be different from main-cursor tap to realize boost effect
• sgn(C[-1]) = sgn(C[+1]) = sgn(C[0]), for low-pass filter effect; the sign for the pre-cursor and/or post-cursor tap must be equal to the main-cursor tap to realize attenuation effect The FIR filter is used to pre-distort the transmitted waveform to compensate for frequency-dependant loss in the output channel. The most common way of pre-distorting the signal is to accentuate the transitions and de- emphasize the non-transitions. The bit before a transition is accentuated through the pre-cursor tap, and the bit after the transition is accentuated through the post-cursor tap. The waveforms in Figure 8 through Figure 10 give a conceptual illustration of how the FIR filter affects the output waveform. These characteristics can be derived from the example waveforms:
• VODpk-pk= v7 – v8
• VODlow-frequency = v2 – v5
• RpredB = 20 × log10 (v3 ⁄v2 )
• RpstdB = 20 × log10 (v1 ⁄v2 )

8.3.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization

Table 2. Typical VOD and FIR Values

Table 2. Typical VOD and FIR Values (continued) the link partner transmitter and the DS250DF230 receiver.

Figure 13. Guideline for Link Partner FIR Settings When IL ≤ 35 dB

8.3.9.2 Output Driver Polarity Inversion

8.3.9.3 Slow Slew Rate

retimer. DS250DF230 does offer this option. See output transition-time parameter from Electrical Characteristics. It is not recommended to use the slow rate setting for divide-by-1 data rate applications.

8.3.10 Debug Features

8.3.10.1 Pattern Generator

• PRBS – 27 – 1
• PRBS – 29 – 1
• PRBS – 211 – 1
• PRBS – 215 – 1
• PRBS – 223 – 1
• PRBS – 231 – 1

www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated

8.3.10.2 Pattern Checker

The pattern checker can be manually set to look for specific PRBS sequences and polarities or it can be set to automatically detect the incoming pattern and polarity. The PRBS checker supports the same set of PRBS patterns as the PRBS generator. The pattern checker consists of an 11-bit error counter. The pattern checker uses 32-bit words, but every bit in the word is checked for error, so the error count represents the count of single bit errors. To read out the bit and error counters, the pattern checker must first be frozen. Continuous operation with simultaneous read out of the bit and error counters is not supported in this implementation. Once the bit and error counter is read, they can be unfrozen to continue counting.

8.3.10.3 Eye-Opening Monitor

The DS250DF230’s Eye-Opening Monitor (EOM) measures the internal data eye at the input of the decision slicer and can be used for 2 functions: 1. Horizontal Eye Opening (HEO) and Vertical Eye Opening (VEO) measurement 2. Full Eye Diagram Capture The HEO measurement is made at the 0 V crossing and is read in channel register 0x27. The VEO measurement is made at the 0.5 UI mark and is read in channel register 0x28. The HEO and VEO registers can be read from channel registers 0x27 and 0x28 at any time while the CDR is locked. The following equations are used to convert the contents of channel registers 0x27 and 0x28 into their appropriate units:

• HEO [UI] = Reg_0x27 ÷ 32
• VEO [mV] = Reg_0x28 × 3.125 A full eye diagram capture can be performed when the CDR is locked. The eye diagram is constructed within a 64 × 64 array, where each cell in the matrix consists of an 16-bit word representing the total number of hits recorded at that particular phase and voltage offset. Users can manually adjust the vertical scaling of the EOM or allow the state machine to control the scaling which is the default option. The horizontal scaling controlled by the state machine is always directly proportional to the data rate. When a full eye diagram plot is captured, the retimer will shift out four 16-bit words of residual data that must be discarded followed by 4096 16-bit words that make up the 64 × 64 eye plot. The first actual word of the eye plot from the retimer is for (X, Y) position (0,0), which is the earliest position in time and the most negative position in voltage. Each time the eye plot data is read out, the voltage position is incremented. Once the voltage position has incremented to position 63 (the most positive voltage), the next read will cause the voltage position to reset to 0 (the most negative voltage) and the phase position to increment. This process will continue until the entire 64 × 64 matrix is read out. Figure 14 shows the EOM read out sequence overlaid on top of a simple eye opening plot. In this plot any hits are shown in green. This type of plot is helpful for quickly visualizing the HEO and VEO. Users can apply different algorithms to the output data to plot density or color gradients to the output data.

Figure 14. EOM Full Eye Capture Readout

Channel Reg 0x2C[6] → 0 (see Table 3). Table 3. Eye-Opening Monitor Vertical Range Settings

• Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.
• With single byte reads, the MSB are located in register 0x25 and the LSB are located in register 0x26. In this mode, the device must be addressed each time a new byte is read. To perform a full eye capture with the EOM, follow the steps listed in Table 4 within the desired channel register set:

Table 4. Eye-Opening Monitor Full Eye Capture Instructions Ch reg 0x24[0] is self-clearing.

8.3.11 Interrupt Signals

output that will pull the line low when an interrupt signal is triggered.

• CDR loss of lock
• CDR locked
• Signal detect loss
• Signal detected
• PRBS pattern checker bit error detected
• HEO/VEO threshold violation When an interrupt occurs, share register 0x08 reports which channel generated the interrupt request. Users can then select the channel(s) that generated the interrupt request and service the interrupt by reading the appropriate interrupt status bits in the corresponding channel registers. For more information on reading interrupt status, refer to the DS250DF230 Programmer's Guide (SNLU182).

8.4 Device Functional Modes

8.4.1 Supported Data Rates

supported data rates are listed in Table 5. Table 5. Supported Data Rates

12.9 Gbps <19.6 Gbps N/A Bypassed Output jitter will be higher with CDR bypassed.

6.45 Gbps < 9.8 Gbps N/A Bypassed Output jitter will be higher with CDR bypassed.

< 4.9 Gbps N/A Bypassed Output jitter will be higher with CDR bypassed. Table 6. Rate/Sub-Rate Table(1)

www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated

8.4.2 SMBus Master Mode

SMBus master mode allows the DS250DF230 to program itself by reading directly from an external EEPROM. When using the SMBus master mode, the DS250DF230 will read directly from specific location in the external EEPROM. When designing a system for using the external EEPROM, the user must follow these specific guidelines:

• Maximum EEPROM size is 2048 Bytes
• Minimum EEPROM size for a single DS250DF230 with individual channel configuration is 161 Bytes (3 base header bytes + 12 address map bytes + 2 × 72 channel register bytes + 2 share register bytes; bytes are defined to be 8-bits)
• Set ENSMB = Float, for SMBus master mode
• The external EEPROM device address byte must be 0xA0
• The external EEPROM device must support 400kHz operation at 2.5-V or 3.3-V supply
• THR pin is pulled low by 1 kΩ to GND, so that DS250DF230 is working under 2.5-V/3.3-V SMBus interface mode
• Set the SMBus address of the DS250DF230 by configuring the ADDR0 and ADDR1 pins When loading multiple DS250DF230 devices from the same EEPROM, use these guidelines to configure the devices:
• Configure the SMBus addresses for each DS250DF230 to be sequential. The first device in the sequence must have an address of 0x30
• Daisy chain READ_EN_N and ALL_DONE_N from one device to the next device in the sequence so that they do not compete for the EEPROM at the same time.
• If all of the DS250DF230 devices share the same EEPROM channel and share register settings, configure the common channel bit in the base header to 1. With common channel configuration enabled, each DS250DF230 device will configure all 2 channels with the same settings. When loading a single DS250DF230 from an EEPROM, use these guidelines to configure the device:
• Set the common channel bit to 0 to allow for individual channel configuration, or set the common channel bit to 1 to load the same configuration settings to all channels.
• When configuring individual channels, a 512, 1024 or 2048 Byte EEPROM must be used.
• If there are more than three DS250DF230 devices on a PCB that require individual channel configuration, then each device must have its own EEPROM.

8.4.3 Device SMBus Address

• 0: 1 kΩ to GND
• R: 10 kΩ to GND (20 kΩ also acceptable)
• F: Float
• 1: 1 kΩ to VDD

Table 7. SMBus Address Map

8.5 Programming

8.5.1 Bit Fields in the Register Set

procedure described above must be used.

• R - Read only
• RW - Read/Write
• RWSC - Read/Write, self-clearing

www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated Programming (continued)

8.5.2 Writing to and Reading from the Global/Shared/Channel Registers

The DS250DF230 has 3 types of registers: 1. Global Registers – These registers can be accessed at any time and are used to select individual channel registers, the shared registers or to read back the TI ID and version information. 2. Shared Registers – These registers are used for device-level configuration, status read back or control. 3. Channel Registers – These registers are used to control and configure specific features for each individual channel. All channels have the same channel register set and can be configured independent of each other. The global registers can be accessed at any time, regardless of whether the shared or channel register set is selected. The DS250DF230 global registers are located on addresses 0xEF-0xFF. The function of the global registers falls into the following categories:

• Channel selection and share enabling – Registers 0xFC and 0xFF
• Device and version information – Registers 0xEF-0xF3
• Reserved/unused registers – all other addresses Register 0xFC is used to select the channel registers to be written to. To select a channel, write a 1 to its corresponding bit in register 0xFC. Note that more than one channel may be written to by setting multiple bits in register 0xFC. However, when performing an SMBus read transaction only one channel can be selected at a time. If multiple channels are selected in register 0xFC when attempting to perform an SMBus read, the device will return 0xFF. Register 0xFF bit 1 can be used to perform broadcast register writes to all channels. A single channel read- modify broadcast write type commands can be accomplished by setting register 0xFF to 0x03 and selecting a single channel in register 0xFC. This type of configuration allows for the reading of a single channel's register information and then writing to all channels with the modified value. Register 0xFF bit 0 is used to select the shared register page or the channel register page for the channels selected in register 0xFC. TI repeaters/retimers have a vendor ID register (0xFE) which will always read back 0x03. In addition, there are three device ID registers (0xF0, 0xF1, and 0xF3). These are useful to verify that there is a good SMBus connection between the SMBus master and the DS250DF230.

8.6 Register Maps

Table 8. Global Registers 3 1 R N CHAN_CONFIG_ID[3] TI device ID (Quad count).

Table 8. Global Registers (continued) else this function is invalid.

Table 9. Shared Registers

Table 9. Shared Registers (continued)

Table 10. Channel Registers, 0 to 39 3 0 RW N RST_CORE 1: Reset the 10M core clock domain. includes PPM counter, EOM counter. not work if 25MHz clock is not present. having acquired it. Bit clears on read.

Table 10. Channel Registers, 0 to 39 (continued)

5 0 RW Y REG_BYPASS_PFD_OV 0: Normal operation.

4 0 RW Y DFE_WT1[4] These bits force DFE tap 1 weight.

6 0 RW Y EQ_PD_SD 1: Power down signal detect. 4 1 RW Y EQ_EN_DC_OFF 1: Normal operation. 0: Disable DC offset compensation. equalizer to be a limiting stage.

All other values are reserved.

1C 7 1 RW Y EN_IDAC_PD_CP2 Phase detector charge pump setting. 0: Normal operation. Disable serializer. be functional in any adapt mode. 2 0 RW Y PFD_PD_PD 1: Power down PFD phase detector. 0: (Default) Disable DFE taps 3-5. 0: Disable PFD frequency detector.

Monitor samples each point in the eye.

3 0 RW Y DFE_ADAPT_COUNTER[3] DFE look-beyond count.

used as the starting point for adaption.

the "Fixed Pattern" generator option. pattern generator and PRBS checker. 2 0 RW N PRBS_PROGPATT_EN Enable a fixed data pattern output. set by Reg_0x7C and Reg_0x97.

takes precedence over EQ_SM_FOM. 1 0 RW Y CDR_LOCK_LOSS_INT_EN Enable for CDR Lock Loss Interrupt. adaption. This can be a max of 15.

the counter is reset back to zero. 4 0 RW Y DFE_MAX_TAP1[4] Limits DFE tap 1 maximum magnitude.

Table 11. Channel Registers, 3A to A9 from this register will be used.

Table 11. Channel Registers, 3A to A9 (continued)

PPM counter lock check for group 0. PPM counter lock check for group 1.

HEO/VEO for lock qualification. monitoring for lock qualification.

6 1 RW Y FOM_A[6] Alternate Figure of Merit variable A. channel Reg_0x6B, 0x6C, and 0x6D. register value divided by 128. channel Reg_0x6B, 0x6C, and 0x6D.

setting, from Reg_0x3A will be used. HI if a PRBS stream is detected.

has been cleared by reading. 6 0 RW N PRBS_CHKR_EN 1: Enable the PRBS checker.

continuous DFE adaption is enabled.

6 0 RW N RST_PRBS_CNTS 1: Reset the PRBS error counter. defined in bit 0 of this register.

2 0 RW Y EQ_EN_FANOUT 1: Enable the ebuf for the fanout. local. 1-indicates from the cross.

setting, when override is enabled.

0 Only)

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

associated design considerations.

9.2 Typical Applications

1. Front-Port Jitter Cleaning Applications
2. Active Cable Applications
3. Backplane and Mid-Plane Applications

Figure 15. Typical Uses for the DS250DF230 in a System

9.2.1 Front-Port Jitter Cleaning Applications

for Figure 16, where one single device supports both egress and ingress channels. Figure 16. Bidirectional Application linear repeater device such as the DS280BR820 (or similar) is recommended. Figure 17. Front-Port Application Block Diagram

2.5 V or

(1) SMBus signals need to be pulled up elsewhere in the system. Figure 18. Front-Port Application Schematic

9.2.1.1 Design Requirements

For this design example, the following guidelines outlined in Table 12 apply. Table 12. Front-Port Application Design Guidelines required for the TX outputs. host channel requirements (approximately 7 dB at 12.9 GHz). with 3-tap FIR filter for equalizing a portion of the output channel. Host ASIC TX launch amplitude 800 mVppd to 1200 mVppd. Cursor, and Post-Cursor Equalization section.

9.2.1.2 Detailed Design Procedure

1. Determine the total number of channels on the board which require a DS250DF230 for signal conditioning.
2. Determine the maximum current draw required for all DS250DF230 retimers. This may impact the selection

transient power supply current by the total number of DS250DF230 devices.

1. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two

case power consumption in mission mode by the total number of DS250DF230 devices. total number of DS250DF230 devices.

1. Determine the SMBus address scheme needed to uniquely address each DS250DF230 device on the board,

I2C/SMBus switches and multiplexers to split up the SMBus into multiple busses.

1. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus

b. If SMBus Slave Mode will be used for all device configurations, an EEPROM is not needed.

1. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD

supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details.

1. Make provisions in the schematic and layout for a 30.72 MHZ (±100 ppm) or 25 MHz (±100 ppm) single-

and the next retimer’s CAL_CLK_IN input. The final retimer’s CAL_CLK_OUT output can be left floating.

1. Connect the INT_N open-drain output to an FPGA or CPU if interrupt monitoring is desired. Note that

common INT_N net must be pulled high.

1. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in

require the ambient temperature surrounding the DS250DF230 to be kept above (110ºC – TEMPLOCK–).

9.2.1.3 Application Curves

to evaluate the FIR filter, which consists of 0xFF00. All other device settings are left at default. Figure 19. DS250DF230 Operating at 25.78125 Gbps Figure 20. DS250DF230 FIR Transmit Equalization While

9.2.2 Active Cable Applications

application, and Figure 23 shows an example simplified schematic for a full-active cable application. Figure 21. Active Cable Application Block Diagram

(1) SMBus signals need to be pulled up elsewhere in the system. Figure 22. Half-Active Cable Application Schematic

(1) SMBus signals need to be pulled up elsewhere in the system. Figure 23. Full-Active Cable Application Schematic

9.2.2.1 Design Requirements

For this design example, the following guidelines outlined in Table 13 and Table 14 apply. Table 13. Half-Active Cable Application Design Guidelines loss allocated for the raw cable and paddle cards is 27 dB. Table 14. Full-Active Cable Application Design Guidelines for the RX inputs and the TX outputs.

9.2.2.2 Detailed Design Procedure

1. Determine the maximum current draw required for the DS250DF230 retimer(s) on the paddle card. This may

multiply the maximum transient power supply current by the total number of DS250DF230 devices.

1. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two

case power consumption in mission mode by the total number of DS250DF230 devices. total number of DS250DF230 devices.

1. Determine the SMBus address for the DS250DF230 Retimer(s). The ADDR[1:0] pins can be left floating for

SMBus slave address will be 0x34.

www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated 4. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus (SMBus Slave Mode). a. If SMBus Master Mode will be used, provisions must be made for an EEPROM on the board with 8-bit SMBus address 0xA0. Refer to SMBus Master Mode for more details on SMBus Master Mode including EEPROM size requirements. b. If SMBus Slave Mode will be used for all device configurations, for example when the Retimer(s) is configured with a microcontroller, an EEPROM is not needed. 5. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details. 6. Make provisions in the schematic and layout for a 30.72-MHz (±100 ppm) or 25-MHz (±100 ppm) single- ended CMOS clock. The DS250DF230 retimer buffers the clock on the CAL_CLK_IN pin and presents the buffered clock on the CAL_CLK_OUT pin. When using two Retimers on a paddle card, only one 30.72-MHZ or 25-MHz clock is required. The CAL_CLK_OUT pin of one retimer can be connected to the CAL_CLK_IN pin of the other retimer. 7. Connect the INT_N open-drain output to the paddle card MCU if interrupt monitoring is desired, otherwise leave it floating. Note that multiple retimers’INT_N outputs can be connected together because this is an open-drain output. The common INT_N net should be pulled high. 8. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in Recommended Operating Conditions, take care to ensure the operating junction temperature is met as well as the CDR stay-in-lock junction temperature range defined in Electrical Characteristics. For example, if initial CDR lock acquisition occurs at an junction temperature of 110ºC, then maintaining CDR lock would require the junction temperature on DS250DF230 to be kept above (110ºC – TEMPLOCK–).

9.2.2.3 Application Curves

See Application Curves in section Front-Port Jitter Cleaning Applications.

9.2.3 Backplane and Mid-Plane Applications

Figure 24. Backplane/Mid-Plane Application Block Diagram

(1) SMBus signals need to be pulled up elsewhere in the system. Figure 25. Backplane/Mid-Plane Application Schematic

9.2.3.1 Design Requirements

For this design example, the following guidelines outlined in Table 15 apply. Table 15. Backplane/Mid-Plane Application Design Guidelines for the RX inputs and TX outputs. equalizing a portion of the output channel. Cursor, and Post-Cursor Equalization section.

9.2.3.2 Detailed Design Procedure

1. Determine the total number of channels on the board which require a DS250DF230 for signal conditioning.
2. Determine the maximum current draw required for all DS250DF230 retimers. This may impact the selection

transient power supply current by the total number of DS250DF230 devices.

1. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two

case power consumption in mission mode by the total number of DS250DF230 devices. total number of DS250DF230 devices.

1. Determine the SMBus address scheme needed to uniquely address each DS250DF230 device on the board,

I2C/SMBus switches and multiplexers to split up the SMBus into multiple busses.

1. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus

b. If SMBus Slave Mode will be used for all device configurations, an EEPROM is not needed.

1. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD

supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details.

1. Make provisions in the schematic and layout for a 30.72-MHz (±100 ppm) or 25-MHz (±100 ppm) single-

and the next retimer’s CAL_CLK_IN input. The final retimer’s CAL_CLK_OUT output can be left floating.

www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated 8. Connect the INT_N open-drain output to an FPGA or CPU if interrupt monitoring is desired. Note that multiple retimers’ INT_N outputs can be connected together because this is an open-drain output. The common INT_N net must be pulled high. 9. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in Recommended Operating Conditions, take care to ensure the operating junction temperature is met as well as the CDR stay-in-lock junction temperature range defined in Electrical Characteristics. For example, if initial CDR lock acquisition occurs at an junction temperature of 110 ºC, then maintaining CDR lock would require the junction temperature on DS250DF230 to be kept above (110ºC - TEMPLOCK-).

9.2.3.3 Application Curves

See Application Curves in section Front-Port Jitter Cleaning Applications.

10 Power Supply Recommendations

Follow these general guidelines when designing the power supply: 1. The power supply must be designed to provide the recommended operating conditions outlined in Specifications in terms of DC voltage, AC noise, and start-up ramp time. 2. The maximum current draw for the DS250DF230 is provided in Specifications. This figure can be used to calculate the maximum current the power supply must provide. Typical mission-mode current draw can be inferred from the typical power consumption in Specifications. 3. The DS250DF230 does not require any special power supply filtering (that is, ferrite bead), provided the recommended operating conditions are met. Only standard supply decoupling is required. Refer to the Pin Configuration and Functions section for details concerning the recommended supply decoupling.

11 Layout

11.1 Layout Guidelines

1. Decoupling capacitors must be placed as close to the VDD pins as possible. Placing them directly

underneath the device is one option if the board design permits.

1. High-speed differential signals TXnP/TXnN and RXnP/RXnN must be tightly coupled, skew matched, and
2. Vias must be avoided when possible on the high-speed differential signals. When vias must be used, take

care to minimize the via stub, either by transitioning through most or all layers, or by back drilling.

1. GND relief can be used beneath the high-speed differential signal pads to improve signal integrity by

counteracting the pad capacitance.

1. GND relief can be used beneath the AC-coupling capacitor pads to improve signal integrity by counteracting
2. GND vias must be placed directly beneath the device connecting the GND plane attached to the device to
3. If vias are used for the high-speed signals, the ground via must be implemented adjacent to the signal via to

11.2 Layout Examples

array using microstrip routing on a generic multi-layer stackup. Figure 26. Top Layer Figure 27. Layer 1 GND

SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 www.ti.com Product Folder Links: DS250DF230 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

For additional information, see TI’s Surface Mount Technology (SMT) References at: http://focus.ti.com/quality/docs under the Quality & Lead (Pb)-Free Data menu. For device and channel model simulation, refer to the DS250DF230 IBIS-AMI Model:

• DS250DF230 IBIS-AMI Model (SNLM215) Click here to request access to the DS250DF230 IBIS-AMI Model (SNLM215) in the DS250DF230 MySecure folder.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation, see the following:

• DS2x0DF810, DS250DFx10, DS250DF230 Programmer's Guide (SNLU182) Click here to request access to the DS250DF230 Programming Guide in the DS250DF230 MySecure folder.

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

E2E is a trademark of Texas Instruments.

12.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. space (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) space (3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. space (4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. space (5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device space (6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

13.1 Package Option Addendum

13.1.1 Packaging Information

Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish(3) MSL Peak Temp (4) Op Temp (°C) Device Marking(5)(6) DS250DF230ZLSR PREVIEW DSBGA ZLS 36 3000 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 H -40 to 85 D250DF230 DS250DF230ZLST PREVIEW DSBGA ZLS 36 250 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 H -40 to 85 D250DF230

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed DS250DF230 SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 www.ti.com Product Folder Links: DS250DF230 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

13.1.2 Tape and Reel Information

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DS250DF230ZLSR DSBGA ZLS 36 3000 330 12.4 5.3 5.3 1.65 8 12 TBD DS250DF230ZLST DSBGA ZLS 36 250 TBD 12.4 5.3 5.3 1.65 8 12 TBD

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H DS250DF230 www.ti.com SNLS590B – AUGUST 2018– REVISED OCTOBER 2019 Product Folder Links: DS250DF230 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS250DF230ZLSR DSBGA ZLS 36 3000 TBD TBD TBD DS250DF230ZLST DSBGA ZLS 36 250 TBD TBD TBD

www.ti.com 10-Dec-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS250DF230RTVR PREVIEW WQFN RTV 32 3000 RoHS (In work) & Non-Green Call TI Call TI -40 to 85 DS250DF230RTVT PREVIEW WQFN RTV 32 3000 RoHS (In work) & Non-Green Call TI Call TI -40 to 85 DS250DF230ZLSR ACTIVE NFBGA ZLS 36 3000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 D250DF230 DS250DF230ZLST ACTIVE NFBGA ZLS 36 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 D250DF230 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 10-Dec-2020 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS250DF230ZLSR NFBGA ZLS 36 3000 336.6 336.6 31.8 DS250DF230ZLST NFBGA ZLS 36 250 336.6 336.6 31.8 PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C1.41 MAX TYP0.35 0.23

0.8 TYP

4 TYP

36X -0.45 0.35 B 5.1 4.9 A 5.1 4.9 NFBGA - 1.41 mm max heightZLS0036A BALL GRID ARRAY 4220412/A 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.1 C SCALE 2.500 B A 1 2 3

0.15 C A B

0.08 C SYMM SYMM BALL A1 CORNER 5 6 E D C F

www.ti.com EXAMPLE BOARD LAYOUT 36X ( 0.35) (0.8) TYP (0.8) TYP ( 0.35) METAL

0.05 MAX

( 0.35) SOLDER MASK OPENING

0.05 MIN

NFBGA - 1.41 mm max heightZLS0036A BALL GRID ARRAY 4220412/A 04/2017 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments Literature number SPRAA99 (www.ti.com/lit/spraa99). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 1 2 3 4 F E D C B A 5 6 NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE EXPOSED METAL SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (0.8) TYP NFBGA - 1.41 mm max heightZLS0036A BALL GRID ARRAY 4220412/A 04/2017 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.15 mm THICK STENCIL SCALE:15X 1 2 3 4 F E D C B A 5 6

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated