DS2430AP+

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19-5236; 4/10 DS2430A 256-Bit 1-Wire EEPROM www.maxim-ic.com

FEATURES

 256-bit Electrically Erasable Programmable Read Only Memory (EEPROM) plus 64-bit one-time programmable application register  Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) assures absolute identity because no two parts are alike  Built-in multidrop controller ensures compatibility with other MicroLAN products  EEPROM organized as one page of 32 bytes for random access  Reduces control, address, data, and power to a single data pin  Directly connects to a single port pin of a microprocessor and communicates at up to 15.3kbits per second  8-bit family code specifies DS2430A communication requirements to reader  Presence detector acknowledges when reader first applies voltage  Low cost TO-92 or 6-pin TSOC and UCSP surface mount package  Reads and writes over a wide voltage range of 2.8V to 5.25V from -40°C to +85°C

ORDERING INFORMATION

DS2430AP+ 6-pin TSOC Package DS2430A+T&R TO-92 Package, Tape & Reel DS2430AP+T&R TSOC Package, Tape & Reel +Denotes a lead(Pb)-free/RoHS-compliant package. Contact factory for availability of the UCSP version. PIN ASSIGNMENT TO-92 NOTE: The leads of TO-92 packages on tape- and-reel are formed to approximately 100 mil (2.54 mm) spacing. For details see Package Information. PIN DESCRIPTION TO-92 TSOC Pin 1 Ground Ground Pin 2 Data Data Pin 3 NC NC Pin 4 –––– NC Pin 5 –––– NC Pin 6 –––– NC SIDE VIEW TOP VIEW 3.7mm x 4.0mm x 1.5mm TSOC PACKAGE DALLAS DS2430A 1 2 3 BOTTOM VIEW See Mech. Draw ings Section 1 2 3 NOT RECOMMENDED FOR NEW DESIGNS

DESCRIPTION

The DS2430A 256-bit 1-Wire EEPROM identifies and st ores relevant information about the product to which it is associated. This lot or product specific information can be accessed with minimal interface, for example a single port pin of a microcontroller. The DS 2430A consists of a factory-lasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (14h) plus 256 bits of user-programmable EE PROM and a 64-bit one-time progra mmable application register. The power to read and write the DS2430A is derived entirely from the 1-Wire ® communication line. Data is transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return. The 48-bit serial number that is factory-lasered into each DS2430A provides a guaranteed unique identity that allows for absolute traceability. The TO-92 a nd TSOC packages provide a compact enclosure that allows standard assembly equipment to handle the de vice easily for attachment to printed circuit boards or wiring. Typical applications incl ude storage of calibrati on constants, board id entification, and product revision status. OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2430A. The DS2430A has four main data components: 1) 64-bit lasered ROM, 2) 256-bit EEPROM data memory with scratchpad, 3) 64-bit one -time programmable applic ation register with scratchpad and 4) 8-bit stat us memory. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the four ROM Function Commands: 1) Read ROM, 2) functions become accessible and the master can provide any one of the four memory function commands. least significant bit first. of CRC should return the shift register to all 0s. 1-Wire and iButton are registered trademarks of Maxim Integrated Products, Inc.

DS2430A BLOCK DIAGRAM Figure 1 3 of 19 NOT RECOMMENDED FOR NEW DESIGNS

HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 64-BIT LASERED ROM Figure 3 8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code (14H) MSB LSB MSB LSB MSB LSB 1-WIRE CRC GENERATOR Figure 4 Polynomial = X8 + X5 + X4 + 1 4 of 19 NOT RECOMMENDED FOR NEW DESIGNS

The memory of the DS2430A consists of three separate sections, called data memory, application register, and status register (Figur e 5). The data memory and the appl ication register each have its own intermediate storage area called scratchpad that act s as a buffer when writing to the device. The data memory can be read and written as often as desired. The applica tion register, howev er, is one-time programmable only. Once the application register is programmed, it is automatically write protected. The status register indicates whether the application register is already lock ed or whether it is still available for storing data. As long as the a pplication register is unprogrammed, the status register reads FFh. Copying data from the register scratchpad to the application re gister clears the 2 least significant bits of the status register, yielding an FCh the next time one reads the status register. DS2430A MEMORY MAP Figure 5 MEMORY FUNCTION COMMANDS The Memory Function Flow Chart (Figure 6) describes the protocols necessary for accessing the different memory sections of the DS2430A. An example is shown later in this document. WRITE SCRATCHPAD [0Fh] After issuing the Write Scratchpad command, the master must first provide a 1-byte address, followed by the data to be written to the sc ratchpad for the data memory. The DS2430A automatically increments the address after every byte it receives. After having received a data byte for address 1Fh, the address counter wraps around to 00h for the next byte and writing continues until the master sends a Reset Pulse. READ SCRATCHPAD [AAh] This command is used to verify data previously written to the scratchpad before it is copied into the final storage EEPROM memory. After issuing the Read Scra tchpad command, the master must provide the 1- byte starting address from where data is to be re ad. The DS2430A automatically increments the address after every byte read by the master. After the data at address 1Fh has been read, the address counter wraps around to 00h for the next byte and reading continues until the master sends a Reset Pulse. 5 of 19 NOT RECOMMENDED FOR NEW DESIGNS

MEMORY FUNCTION FLOW CHART Figure 6 COPY SCRATCHPAD [55h] After the data stored in the sc ratchpad has been verified the ma ster may send the Copy Scratchpad command followed by a validation key of A5h to tran sfer data from the scratchpad to the EEPROM memory. This command always copies the data of th e entire scratchpad. Theref ore, if one desires to change only a few bytes of the EEPROM data, th e scratchpad should contai n a copy of the latest EEPROM data before the Write Scratchpad and C opy Scratchpad commands are issued. After this command and the validation key are issued, the data line must be held above VPUPmin for at least tPROG. READ MEMORY [F0h] The Read Memory command is used to read a portion or all of the EEPROM data memory and to copy the entire data memory into the scratchpad to prepare for changing a few bytes. To copy data from the data memory to the scratchpad and to read it, the master must issue the read memory command followed by the 1-byte starting address of th e data to be read from the sc ratchpad. The DS2430A automatically increments the address after every byte read by the ma ster. After the data of a ddress 1Fh has been read, the address counter wraps around to 00h for the next byt e and reading continues until the master sends a Reset Pulse. If one intends to copy the entire data memory to the scratchpa d without reading data, a starting address is not required; the master may send a Reset Pulse immediately following the command code. 6 of 19 NOT RECOMMENDED FOR NEW DESIGNS

MEMORY FUNCTION FLOW CHART Figure 6 (cont’d) WRITE APPLICATION REGISTER [99h] This command is essentially the same as the Write Scratchpad co mmand, but it addresses the 64-bit register scratchpad. After issuing th e command code, the master must provide a 1-byte address, followed by the data to be written. The DS2430A automatically increments the address after every byte it receives. After receiving the data byte for address 07h, the a ddress counter wraps around to 00h for the next byte and writing continues until the master sends a Reset Pu lse. The Write Application Register command can be used as long as the application register has not yet been locked. If issued for a device with the application register locked, the data written to the register scratchpad will be lost. READ STATUS REGISTER [66h] The status register is a means for the master to find out whether the application register has been programmed and locked. After issui ng the read status register comm and, the master must provide the validation key 00h before receiving status information. The two least significant bits of the 8-bit status register are 0 if the application re gister was programmed and locked; all other bits always read 1. The master may finish the read status command by sending a Reset Pulse at any time. 7 of 19 NOT RECOMMENDED FOR NEW DESIGNS

MEMORY FUNCTION FLOW CHART Figure 6 (cont’d) READ APPLICATION REGISTER [C3h] This command is used to read th e application register or the re gister scratchpad. As long as the application register is not yet locked, the DS2430A tran smits data from the regist er scratchpad. After the application register is locked the DS2430A transmits data from the application register, making the register scratchpad inaccessible for reading. The contents of the status register indicate where the data received with this command came from. After issuing the Read Applica tion Register command, the master must provide the 1-byte starting address from where data is to be read. The DS2430A automatically increments the addres s after every byte read by the master . After the data at address 07h has been read, the address counter wraps around to 00h for the next byte and reading continues until the master sends a Reset Pulse. COPY & LOCK APPLICATION REGISTER [5Ah] After the data stored in the register scratchpad has been verified the master may send the Copy & Lock Application Register command followed by a validation key of A5h to transf er the contents of the entire register scratchpad to the applicat ion register and to simultaneously write-protect it. The master may cancel this command by sending a Rese t Pulse instead of the validation key. After the validation key is transmitted, the data line must be held above V PUPmin for at least t PROG. Once t PROG has expired, the application register will contai n the data of the register scra tchpad. Further write accesses to the application register will be denied. The Copy & Lock Application Register command can only be executed once. 8 of 19 NOT RECOMMENDED FOR NEW DESIGNS

The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances, the DS2430A is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware conf iguration, transaction sequence, and 1-Wire signaling (signal type and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. Hardware Configuration The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain connection or three-state outp uts. The 1-Wire port of the DS2430A is open drain with an internal circuit equivalent to that shown in Figure 7. A mu ltidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS2430A communicates at regular 1-Wire speed, 15.3kbits per second, and requires a pullup resistor as shown in Figure 7. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120µs, one or more of the devices on the bus may be reset. HARDWARE CONFIGURATION Figure 7 RPU IL RPU Note: Depending on the 1-Wire communication speed an d the bus characteristics, the optimal pullup resistor value will be in the 0.3k  to 2.2k range. To write to a single device, a R PUPmax resistor and VPUP of at least 4.0V is sufficient. For writing multiple DS2430As simu ltaneously or operation at low VPUP, the resistor should be bypassed by a low-impedance pullup to V PUP while the device copies the scratchpad to EEPROM. 9 of 19 NOT RECOMMENDED FOR NEW DESIGNS

ROM FUNCTIONS FLOW CHART Figure 8 10 of 19 NOT RECOMMENDED FOR NEW DESIGNS

The sequence for accessing the DS2430A via the 1-Wire port is as follows:  Initialization  ROM Function Command  Memory Function Command  Transaction/Data INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a Reset Pulse transmitted by the bus master followed by a Presence Pulse(s) transmitted by the slave(s). The Presence Pulse lets the bus master know that the DS2430A is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence pulse, it can issue one of the four ROM function commands. All ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure 8): Read ROM [33h] This command allows the bus master to read the DS 2430A’s 8-bit family code, 48-bit serial number, and 8-bit CRC. This command can be used only if there is a single DS2430A on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain produces a wire d-AND result). The resultant family c ode and 48-bit serial number usually result in a mismatch of the CRC. Match ROM [55h] The Match ROM command, followed by a 64-bit ROM se quence, allows the bus master to address a specific DS2430A on a multidrop bus. Only the DS2430A that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function co mmand. All slaves that do not match the 64-bit ROM sequence will wait for a Reset Pulse. This command can be used with a single or multiple devices on the bus. Skip ROM [CCh] This command can save time in a single-drop bus sy stem by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip RO M command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns produces a wired-AND result). Search ROM [F0h] When a system is initially brought up, the bus mast er might not know the number of devices on the 1- Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The Search ROM process is the repetition of a simple, three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM. NOT RECOMMENDED FOR NEW DESIGNS

For a Write-1 time slot, the voltage on the data line must have crossed the V TH threshold before the Write-1 low time tW1LMAX is expired. For a Write-0 time slot, the voltage on the data line must stay below the VTH threshold until the Write-0 low time t W0LMIN is expired. For the most reliable communication, the voltage on the data line should not exceed V ILMAX during the entire t W0L or t W1L window. After the V TH threshold has been crossed, the DS2430A needs a recovery time t REC before it is ready for the next time slot. READ/WRITE TIMING DIAGRAM Figure 10 Write-1 Time Slot 13 of 19 Write-0 Time Slot Read-data Time Slot RESISTOR MASTER tREC VPUP VIHMASTER VTH VTL VILMAX tF tSLOT tW0L RESISTOR MASTER VPUP VIHMASTER VTH VTL tW1L VILMAX tF  tSLOT RESISTOR MASTER DS2430A tREC VPUP VIHMASTER VTH VTL VILMAX Master Sampling Window  tF tSLOT tRL tMSR NOT RECOMMENDED FOR NEW DESIGNS

A Read-data time slot begins like a Write-1 time slot. The voltage on the data line must remain below VTL until the read low time t RL is expired. During the t RL window, when responding with a 0, the DS2430A starts pulling the data line low; its intern al timing generator determines when this pulldown ends and the voltage starts rising again. When re sponding with a 1, the DS2430A does not hold the data line low at all, and the voltage starts rising as soon as tRL is over. The sum of tRL +  (rise time) on one side and the internal timing generator of the DS2430A on the other side define the master sampling window (t MSRMIN to t MSRMAX) in which the master must perform a read from the data line. For the most reliable communication, t RL should be as short as permissible, and the master should read close to but no later than t MSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This guarantees sufficient recovery time t REC for the DS2430A to get ready for the next time slot. Note that t REC specified herein applies only to a single DS2430A attached to a 1-Wire line. For multidevice configurations, tREC must be extended to accommodate the additional 1-Wire device input capacitance. Alternatively, an interface that performs active pullup during the 1-Wire recovery time such as the DS2482-x00 or DS2480B 1-Wire line drivers can be used. IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS) In a 1-Wire environment, line termination is possibl e only during transients c ontrolled by the bus master (1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and topology of the network, reflections from end points and branch points can add up, or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the 1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the master and, consequently, result in a S earch ROM command coming to a dead end or cause a device-specific function command to abort. For better performan ce in network applications, the DS2430A uses a new 1-Wire front end, which makes it less sensitive to noise. The 1-Wire front end of the DS2430A differs from traditional slave devices in three characteristics. 1) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot. This reduces the sensitivity to high-frequency noise. 2) There is a hysteresis at the low-to-high switching threshold V TH. If a negative glitch crosses V TH but does not go below VTH - VHY, it will not be recognized (Figure 11, Case A).. 3) There is a time window specified by the rising edge hold-off time t REH during which glitches are ignored, even if they extend below V TH - VHY threshold (Figure 11, Case B, t GL < tREH). Deep voltage droops or glitches that app ear late after crossing the V TH threshold and extend beyond the t REH window cannot be filtered out and are taken as the beginning of a new time slot (Figure 11, Case C, tGL  tREH). Devices that have the parameters V HY, and t REH specified in their electri cal characteristics use the improved 1-Wire front end. NOISE SUPPRESSION SCHEME Figure 11 VPUP VTH VHY tREH tGL Case A Case C Case B tGL tREH 14 of 19 NOT RECOMMENDED FOR NEW DESIGNS

Example: Write 2 data bytes to data memory locations 0006h and 0007h. Read entire data memory. MASTER MODE DATA (LSB FIRST) COMMENTS TX Reset Reset pulse (480µs to 960µs) RX Presence Presence pulse TX CCh Issue “Skip ROM” command TX 0Fh Issue “Write Scratchpad” command TX 06h Start address = 06h TX <2 Data Bytes> Write 2 bytes of data to scratchpad TX Reset Reset pulse RX Presence Presence pulse TX CCh Issue “Skip ROM” command TX AAh Issue “Read Scratchpad” command TX 06h Start address = 06h RX <2 Data Bytes> Read scratchpad data and verify TX Reset Reset pulse RX Presence Presence pulse TX CCh Issue “Skip ROM” command TX 55h Issue “Copy Scratchpad” command TX A5h Validation key TX <Data Line High> Data line must be above VPUPmin for tPROG. TX Reset Reset pulse RX Presence Presence pulse TX CCh Issue “Skip ROM” command TX F0h Issue “Read Memory” command TX 00h Start address = 00h RX <32 Bytes> Read EEPROM data page TX Reset Reset pulse RX Presence Presence pulse NOT RECOMMENDED FOR NEW DESIGNS

Voltage on DATA to Ground -0.5V to +6.0V DATA Sink Current 20mA Operating Temperature Range -40°C to +85°C Junction Temperature +150°C Storage Temperature Range -55°C to +125°C Lead Temperature (soldering 10s) +300°C Soldering Temperature (reflow) +260°C (TSOC) +250°C (TO-92) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(TA = -40°C to +85°C; see Note 1.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DATA PIN GENERAL DATA 1-Wire Pullup Voltage VPUP (Notes 2) 2.8 5.25 V 1-Wire Pullup Resistance RPUP (Notes 2, 3) 0.3 2.2 k Input Capacitance CIO (Notes 4, 5) 1000 pF Input Load Current IL DATA pin at VPUP 0.05 15 µA High-to-Low Switching Threshold V TL (Notes 5, 6, 7) 0.46 VPUP - 1.8V V Input Low Voltage VIL (Notes 2, 8) 0.5 V Low-to-High Switching Threshold VTH (Notes 5, 6, 9) 1.0 VPUP - 1.1V V Switching Hysteresis VHY (Notes 5, 6, 10) 0.21 1.70 V Output Low Voltage VOL At 4mA (Note 11) 0.4 V Recovery Time tREC RPUP = 2.2k (Notes 2,12) 5 µs Rising-Edge Hold-off Time t REH (Notes 5, 13) 0.5 5.0 µs Timeslot Duration tSLOT (Notes 2, 14) 65 µs DATA PIN, 1-WIRE RESET, PRESENCE DETECT CYCLE Reset Low Time tRSTL (Note 2) 480 960 µs Presence Detect High Time t PDH 15 60 µs Presence Detect Low Time tPDL 60 240 µs Presence Detect Sample Time t MSP (Notes 2, 15) 60 75 µs DATA PIN, 1-Wire WRITE Write-0 Low Time tW0L (Notes 2, 16) 60 120 -  µs Write-1 Low Time tW1L (Notes 2, 16) 1 15 -  µs DATA PIN, 1-Wire READ Read Low Time tRL (Notes 2, 17) 1 15 -  µs Read Sample Time tMSR (Notes 2, 17) tRL +  15 µs NOT RECOMMENDED FOR NEW DESIGNS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EEPROM Programming Current IPROG (Notes 5, 18) 0.5 mA Programming Time tPROG (Note 19) 10 ms At 25°C 200k Write/Erase Cycles (En- durance) (Notes 20, 21) NCY At 85°C (worst case) 50k  Data Retention (Notes 22, 23, 24) t DR At 85°C (worst case) 40 years Note 1: Specifications at TA = -40°C are guaranteed by design only and not production-tested. Note 2: System requirement. Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum tREC. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required. If longer tREC is used, higher RPUP values may be able to be tolerated. Note 4: Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 2.2k resistor is used to pull up the data line, 2.5µs after VPUP has been applied the parasite capacitance will not affect normal communications. Note 5: Guaranteed by design, characterization and/or simulation only. Not production tested. Note 6: VTL, VTH, and VHY are a function of the internal supply voltage which is itself a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on DATA. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Note 7: Voltage below which, during a falling edge on DATA, a logic 0 is detected. Note 8: The voltage on DATA needs to be less or equal to VIL(MAX) at all times the master is driving DATA to a logic-0 level. Note 9: Voltage above which, during a rising edge on DATA, a logic 1 is detected. Note 10: After VTH is crossed during a rising edge on DATA, the voltage on DATA has to drop by at least VHY to be detected as logic '0'. Note 11: The I-V characteristic is linear for voltages less than 1V. Note 12: Applies to a single device attached to a 1-Wire line. Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge. Note 14: Defines maximum possible bit rate. Equal to 1/(tW0L(min) + tREC(min)). Note 15: Interval after tRSTL during which a bus master is guaranteed to sample a logic-0 on DATA if there is a DS2430A present. Minimum limit is tPDH(max); maximum limit is tPDH(min) + tPDL(min). Note 16:  in Figure 10 represents the time required for the pullup circuitry to pull the voltage on DATA up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1Lmax + tF and tW0Lmax + tF respectively. Note 17:  in Figure 10 represents the time required for the pullup circuitry to pull the voltage on DATA up from VIL to the input high threshold of the bus master. The actual maximum duration for the master to pull the line low is t RLmax + tF. Note 18: Current drawn from DATA during the EEPROM programming interval. The pullup circuit on DATA during the programming interval should be such that the voltage drop been VPUP and DATA is less than 0.25V. Current increases with increased VPUP. Note 19: Interval begins tREHmax after the trailing rising edge on DATA for the last timeslot of the validation key for a valid copy sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from IPROG to IL. Note 20: Write-cycle endurance is degraded as TA increases. Note 21: Not 100% production-tested; guaranteed by reliability monitor sampling. Note 22: Data retention is degraded as TA increases. Note 23: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet limit at operating temperature range is established by reliability testing. Note 24: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C. NOT RECOMMENDED FOR NEW DESIGNS

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-“ in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the draw ing pertains to the package reg ardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

3 TO-92 (Bulk) Q3+1 21-0248

3 TO-92 (T&R) Q3+4 21-0250

6 TSOC D6+1 21-0382

NOT RECOMMENDED FOR NEW DESIGNS

REVISION HISTORY

4/3/95 Initial release — 8/26/96 Changed “C-lead” package to “TSOC” package. Deleted VIHmax specification value. Note “Under certain low voltage conditions VILMAX may have to be reduced to as much as 0.5V to always guarantee a presence pulse.” added to VIL specification, changed VCC to VPUP in Note 6. Various 3/26/97 Changed “Touch Memory” to “iButton”. Various 12/8/98 Programming time changed from 100ms to 10ms, change VDD to VPUP, revised note below Figure 7, programming current changed from 600µA to 500µA, QOP removed from EC table, deleted from Note 5 “and will remain valid for 14µs minimum (15µs total from falling edge on 1-wire bus).” Endurance added to EC table with note “The Copy Scratchpad takes 10 ms maximum, during which the voltage on the 1-Wire bus must not fall below 2.8V.” Various 1/20/99 Chip scale package added to ordering information 1 5/20/99 Deleted duplicate tPDL and contradicting tPROG spec from EC table 15 10/21/99 Template conversion, style changes (capitalization of command names, “Write- one” to “Write-1”, “Write-zero” to “Write-0”) All 2/2/02 Part number corrections, style corrections, note below figure 7 revised explain- ing the appropriate RPUP range, corrections in the Memory Functions Example (removed Read Memory section at the beginning), changed solder spec from 260°C to JEDEC reference, added notes 11, 12, 13 to EC table, changed t RSTLmax from 5000µs to 960µs, revised text of EC table note 8. Various 11/1/05 NRFND watermark added All 1/16/07 Lead free part numbers added; added flip chip graphic with bump electrical assignment, orientation mark and marking; Added flip chip 56-level drawing number, changed "Chip Scale" name to "Flip Chip"; replaced references to the Book of i Button Standards with the corresponding application notes. Various 8/8/07 Note on formed leads for TO-92 TRL and URL to 56-G0006-003 added, ILmin and ILmax spec values added to EC table. Data retention added to EC table. 1, 15 Ordering information for standard and flip chip versions deleted, pin assignment for flip chip version deleted, data rate changed from 16.3kbps to 15.3 kbps. Style corrections and minor text updates for clarification. New 1-Wire front end, improved EEPROM and related EC table with notes. Package information section added Various 12-14, 16-17 19 of 19 19 of 19 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. NOT RECOMMENDED FOR NEW DESIGNS