DS2413 MAXIM | Alldatasheet

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Technical content

1 of 17 REV: 051805 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS2413 is a dual-channel programmable I/O 1- Wire® chip. The PIO outputs are configured as open- drain and provide up to 20mA continuous sink capability and off-state operating voltage up to 28V. Control and sensing of the PIO pins is performed with a dedicated device-level command protocol. To provide a high level of fault tolerance in the end application, the 1-Wire IO and PIO pins are all capable of withstanding continuous application of voltages up to 28V max. Communication and operation of the DS2413 is performed with the single contact Maxim/Dallas 1-Wire serial interface.

APPLICATIONS

/g167/g32LED Control /g167/g32Accessory Identification and Control /g167/g32General Purpose Input/Output /g167/g32Key-Pick Systems /g167/g32Industrial Controllers /g167/g32System Monitoring TYPICAL OPERATING CIRCUIT PX.Y µC RPUP VCC Local Power LED Switch PIOA IO PIOB GND DS2413

FEATURES

/g167/g32Open-Drain Programmable I/O Pins /g167/g32PIO Pins Support 20mA max Continuous Current Sink /g167/g32Supports 28V (max) PIO Pin Operating Voltage /g167/g32On-Resistance of PIO Pulldown Transistor 20/g87 max; OFF Resistance 1M/g87 min /g167/g32Parasitic Power Supply Through 1-Wire /g167/g32Communicates to Host with a Single Digital Signal at 14.9kb or 100kbps Using 1-Wire Protocol /g167/g32Unique 64-bit ROM Serial Number Factory Lasered Into Each Device /g167/g32Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise /g167/g321-Wire IO Pin Supports 28V Absolute Maximum DC Level for Fault Conditions /g167/g32Operates Over a Wide 1-Wire Voltage Range of 2.8V to 5.25V from 0°C to +70°C /g167/g32High ESD Immunity of 1-Wire IO Pin: 8kV HBM Typical /g167/g32TSOC package

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE DS2413P 0°C to +70°C TSOC DS2413P/T&R 0°C to +70°C TSOC Tape &Reel PIN CONFIGURATION TSOC DS2413 1-Wire Dual Channel Addressable Switch www.maxim-ic.com Commands, Registers, and Modes are capitalized for clarity. 1-Wire is a registered trademark of Dallas Semiconductor Corp. TOP VIEW

DS2413: 1-Wire Dual Channel Addressable Switch 2 of 17 ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin to GND -0.5V, +30V Maximum Current into IO Pin /g17725mA Maximum Current into PIO Pin /g17730mA Maximum Current Through GND Pins (Both Pins Tied Together) /g17760mA Operating Temperature Range 0°C to +70°C Junction Temperature +150°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/JEDEC J-STD-020A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS T A = 0°C to +70°C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN GENERAL DATA Standard speed 2.8 5.25 Overdrive speed 2.9 5.25 1-Wire Pullup Voltage (Note 1) VPUP DC only; no 1-Wire communication 28 V 1-Wire Pullup Resistance RPUP (Notes 1, 2) 1.5 2.2 k/g87 VPUP /g163 5.25V 3.5 70 VPUP /g163 3.30V 3.5 15 Input Load Current I L V(IO) = 28V (Note 3) 400 950 µA Input Capacitance C IO At 25°C (Notes 4, 5) 800 pF Input Low Voltage V IL (Notes 1, 6) 0.4 V High-to-Low Switching Threshold VTL (Notes 5, 7, 8) 0.4 3.2 V Low-to-High Switching Threshold VTH (Notes 5, 7, 9) 0.7 3.6 V Switching Hysteresis V HY (Notes 5, 10) 0.2 V Output Low Voltage V OL At 4mA Current Load (Note 11) 0.4 V Standard speed, RPUP = 2.2k/g87 5 Overdrive speed, RPUP = 2.2k/g87 2 Recovery Time (Notes 1, 12) tREC Overdrive speed, directly prior to reset pulse; RPUP = 2.2k/g87 5 µs Standard speed 0.5 5.0 Rising-Edge Hold-off Time (Notes 5, 13) tREH Overdrive speed Not applicable (0) µs Standard speed, VPUP /g179 4.5V 65 Standard speed (Note 14) 67 Overdrive speed, VPUP /g179 4.5V (Note 14) 9 Time slot Duration (Note 1, 5) t SLOT Overdrive speed (Note 14) 10 µs IO PIN, 1-WIRE RESET, PRESENCE DETECT CYCLE Standard speed, VPUP /g179 4.5V 480 960 Standard speed (Note 14) 600 960 Overdrive speed, VPUP /g179 4.5V 48 80 Reset Low Time (Note 1) t RSTL Overdrive speed (Note 14) 63 80 µs Standard speed, VPUP /g179 4.5V 15 66 Standard speed 15 68 Overdrive speed, VPUP /g179 4.5V 2 7.0 Presence Detect High Time (Notes 14, 15) tPDH Overdrive speed 2 8.2 µs Standard speed, VPUP > 4.5V 0.24 1.4 Standard speed 0.24 1.6 Overdrive speed, VPUP /g179 4.5V 0 0.7 Presence Detect Fall Time (Notes 5, 16) tFPD Overdrive speed 0 0.9 µs Standard speed, VPUP > 4.5V 60 240 Standard speed (Note 14) 60 260 Overdrive speed, VPUP /g179 4.5V (Note 14) 8 25 Presence Detect Low Time (Note 15) tPDL Overdrive speed (Note 14) 8 32 µs

DS2413: 1-Wire Dual Channel Addressable Switch 3 of 17 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Standard speed, VPUP > 4.5V 67.4 75 Standard speed 69.6 75 Overdrive speed, VPUP /g179 4.5V 7.7 10 Presence Detect Sample Time (Notes 1, 20) tMSP Overdrive speed 9.1 10 µs IO PIN, 1-Wire WRITE Standard speed, VPUP > 4.5V 60 120 Standard speed (Note 14) 62 120 Overdrive speed, VPUP /g179 4.5V (Note 14) 7 16 Write-0 Low Time (Note 1) t W0L Overdrive speed (Note 14) 8 16 µs Standard speed 5 15 - /g101 Write-1 Low Time (Notes 1, 17) tW1L Overdrive speed 1 2 - /g101 µs IO PIN, 1-Wire READ Standard speed 5 15 - /g100 Read Low Time (Notes 1, 18) tRL Overdrive speed 1 2 - /g100 µs Standard speed tRL + /g100 15 Read Sample Time (Notes 1, 18) tMSR Overdrive speed tRL + /g100 2 µs PIO Pins Leakage Current I LP Pin at 28V (Note 19) 8.5 24 µA Input Capacitance C P (Note 5) 100 pF Output low voltage V OLP 20mA load current 0.4 V Input Low Voltage V ILP (Note 1) 0.8 V Input High Voltage (Note 21) VIHP (Note 1) VPUP – 0.3V 28 V Note 1: System requirement. Note 2: Full RPUP range guaranteed by design and simulation. not production tested. Production testing performed at a fixed RPUP value. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required. Note 3: The I-V characteristic is linear for voltages greater than 10V. Note 4: Capacitance on the data pin could be 800pF when V PUP is first applied. If a 2.2k/g87 resistor is used to pull up the data line, 2.5µs after VPUP has been applied the parasite capacitance will not affect normal communications. Note 5: Guaranteed by design and simulation. Not production tested. Note 6: The voltage on IO needs to be less than or equal to VILMAX whenever the master drives the line low. Note 7: VTL and VTH are functions of the internal supply voltage, which is a function of VPUP and the 1-Wire Recovery Times. Note 8: Voltage below which, during a falling edge on IO, a logic 0 is detected. Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected. Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic '0'. Note 11: The I-V characteristic is linear for voltages less than 1V. Note 12: Applies to a single DS2413 attached to a 1-Wire line. Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached. Note 14: Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below. Note 15: tPDH is deemed to have ended when the voltage on IO drops below 80% of VPUP on the leading edge of the presence-detect low pulse. tPDL is deemed to have begun when the voltage on IO drops below 20% of VPUP on the leading edge of the pulse. Note 16: Interval during the negative edge on IO at the beginning of a Presence Detect pulse between the time at which the voltage is 80% of VPUP and the time at which the voltage is 20% of VPUP. Note 17: /g101 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. Note 18: /g100 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold of the bus master. Note 19: Note 20: Note 21: The I-V characteristic is linear for voltages greater than 7V. t MSP is a system required sample point and not directly production tested. Production testing is performed on related parameters tPDH and tPDL. Parameter tFPD is guaranteed by design and simulation, not production tested. Production tested for VIHP(min). VIHP(max) is guaranteed by design and simulation, not production tested. LEGACY VALUES DS2413 VALUES PARAMETER STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED MIN MAX MIN MAX MIN MAX MIN MAX tRSTL 480µs (undef.) 48µs 80µs 600µs 960µs 63µs 80µs tPDH 15µs 60µs 2µs 6µs 15µs 68µs 2µs 8.2µs tPDL 60µs 240µs 8µs 24µs 60µs 260µs 8µs 32µs tW0L 60µs 120µs 6µs 16µs 62µs 120µs 8µs 16µs

DS2413: 1-Wire Dual Channel Addressable Switch 4 of 17 PIN DESCRIPTION NAME PIN # FUNCTION IO 2 1-Wire bus interface. Open-drain, requires external pullup resistor. PIOA 6 Programmable I/O pin, open-drain with weak pulldown PIOB 4 Programmable I/O pin, open-drain with weak pulldown GND1 1 Ground reference 1 GND2 5 Ground reference 2; both GND pins must be connected in the application. NC 3 Not connected

DESCRIPTION

The DS2413 combines two PIO pins and a fully featured 1-Wire interface in a single chip. PIO outputs are open- drain, operate at up to 28V and provide an on resistance of 20 /g87 max. A robust communication protocol ensures that PIO output changes occur error-free. Each DS2413 has a Registration Number that is 64 bits long. The Registration Number guarantees unique identification and is used to address the device in a multidrop 1-Wire network environment, where multiple devices reside on a common 1-Wire bus and operate independently of each other. Device power is supplied parasitically from the 1-Wire bus. The DS2413’s applications of include accessory identification and control, system monitoring, and general-purpose input/output. OVERVIEW The block diagram in Figure 1 shows the relationships between the major sections of the DS2413. The DS2413 has two main components: 64-bit Registration Number, and PIO Control. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive-Skip ROM or 7) Overdrive- Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the device enters Overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 10. After a ROM function command is successfully executed, the PIO functions become accessible and the master may provide one of the two PIO Function commands. The protocol for these commands is described in Figure 6. All data is read and written least significant bit first. Figure 1. Block Diagram

Figure 6. PIO Function Flow Chart

channels. In an endless loop this command first writes new data to the PIO and then reads back the PIO status. terminated at any time with a 1-Wire Reset. protect the transmission against data errors, the master must repeat the PIO Output Data byte in its inverted form. master can either continue writing more data to the PIO or issue a 1-Wire Reset to end the command. Figure 8. PIO Access Write Timing Diagram the falling edge of sync pulses from the bus master. outputs. The 1-Wire port of the DS2413 is open drain with an internal circuit equivalent to that shown in Figure 9.

(Overdrive speed) or more than 120µs (standard speed), one or more devices on the bus may be reset. Figure 9. Hardware Configuration result). The resultant family code and 48-bit serial number result in a mismatch of the CRC. command can be used with a single or multiple devices on the bus.

DS2413: 1-Wire Dual Channel Addressable Switch 10 of 17 SEARCH ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their device ID numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the device ID numbers of all slave devices. For each bit of the device ID number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its device ID number bit. On the second slot, each slave device participating in the search outputs the complemented value of its device ID number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the ROM code tree. After one complete pass, the bus master knows the device ID number of a single device. Additional passes identify the device ID numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. Since with the DS2413 the ROM CRC is not valid if one or more address inputs are tied to GND, it is recommended to do a double search when building a list of devices on the 1-Wire line. SKIP ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the PIO functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). RESUME [A5h] To maximize the data throughput in a multidrop environment, the Resume function is available. This function checks the status of the RC bit and, if it is set, directly transfers control to the PIO functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume Command function. Accessing another device on the bus clears the RC bit, preventing two or more devices from simultaneously responding to the Resume Command function. OVERDRIVE SKIP ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the PIO functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive Skip ROM sets the DS2413 in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a reset pulse of minimum 480µs duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus, this command sets all Overdrive-supporting devices into Overdrive mode. To subsequently address a specific Overdrive-supporting device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This speeds up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a Read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). OVERDRIVE MATCH ROM [69h] The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at Overdrive Speed allows the bus master to address a specific DS2413 on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS2413 that exactly matches the 64-bit ROM sequence responds to the subsequent PIO Function command. Slaves already in Overdrive mode from a previous Overdrive Skip or successful Overdrive Match command remain in Overdrive mode. All overdrive-capable slaves return to standard speed at the next Reset Pulse of minimum 480µs duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus.

DS2413: 1-Wire Dual Channel Addressable Switch 11 of 17 Figure 10-1. ROM Functions Flow Chart From Figure 10 2nd Part To PIO Functions Flow Chart (Figure 6) Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 Bit 63 Match ? RC = 0 DS2413 TX Bit 0 DS2413 TX Bit 0 Master TX Bit 0 DS2413 TX Bit 1 DS2413 TX Bit 1 Master TX Bit 1 DS2413 TX Bit 63 DS2413 TX Bit 63 Master TX Bit 63 RC = 1 Bit 1 Match ? Bit 0 Match ? Y N Y N Y NBit 63 Match ? RC = 0 RC = 1 Bit 1 Match ? Bit 0 Match ? Y N Y N Y N RC = 0 DS2413 TX CRC Byte DS2413 TX Serial Number (6 Bytes) DS2413 TX Family Code (1 Byte) RC = 0 To Figure 10 2nd Part NF0h Search ROM Command ? N55h Match ROM Command ? N CCh Skip ROM Command ? YY Y Y N 33h Read ROM Command ? To Figure 10 2nd Part From PIO Functions Flow Chart (Figure 6) Bus Master TX ROM Function Command DS2413 TX Presence Pulse OD Reset Pulse ? N Y OD = 0 Bus Master TX Reset Pulse From Figure 10, 2nd Part

DS2413: 1-Wire Dual Channel Addressable Switch 12 of 17 Figure 10-2. ROM Functions Flow Chart (continued) To Figure 10 1st Part From Figure 10 1st Part From Figure 10 1st Part To Figure 10, 1st Part Y NA5h Resume Command ? RC = 1 ? Y N3Ch Overdrive Skip ROM ? RC = 0 ; OD = 1 Master TX Reset ? Y N N Y Master TX Reset ? N Y Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 Bit 63 Match ? RC = 0 ; OD = 1 RC = 1 Bit 1 Match ? Y N Y N Bit 0 Match ? Y N Y N 69h Overdrive Match ROM ?

the definitions of the write- and read-time slots. a write-time slot and how long data is valid during a read-time slot. Figure 12. Read/Write Timing Diagram

DS2413: 1-Wire Dual Channel Addressable Switch 15 of 17 Master-to-Slave For a write-one time slot, the voltage on the data line must have crossed the V TH threshold before the write-one low time t W1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the V TH threshold until the write-zero low time t W0LMIN is expired. For the most reliable communication, the voltage on the data line should not exceed V ILMAX during the entire t W0L or tW1L window. After the V TH threshold has been crossed, the DS2413 needs a recovery time tREC before it is ready for the next time slot. Slave-to-Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below V TL until the read low time t RL is expired. During the t RL window, when responding with a 0, the DS2413 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS2413 does not hold the data line low at all, and the voltage starts rising as soon as t RL is over. The sum of t RL + /g100 (rise time) on one side and the internal timing generator of the DS2413 on the other side define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a read from the data line. For the most reliable communication, t RL should be as short as permissible, and the master should read close to but no later than t MSRMAX. After reading from the data line, the master must wait until t SLOT is expired. This guarantees sufficient recovery time t REC for the DS2413 to get ready for the next time slot. Note that t REC specified herein applies only to a single DS2413 attached to a 1-Wire line. For multidevice configurations, t REC needs to be extended to accommodate the additional 1-Wire device input capacitance. Alternatively, an interface that performs active pullup during the 1-Wire recovery time such as the DS2482-x00 or DS2480B 1-Wire line drivers can be used. IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS) In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and topology of the network, reflections from end points and branch points can add up, or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the 1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the master and, consequently, result in a search ROM command coming to a dead end or cause a device-specific function command to abort. For better performance in network applications, the DS2413 uses a new 1-Wire front end, which makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave device itself. The 1-Wire front end of the DS2413 differs from traditional slave devices in four characteristics. 1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line impedance than a digitally switched transistor, converting the high-frequency ringing known from traditional devices into a smoother low-bandwidth transition. The slew-rate control is specified by the parameter t FPD, which has different values for standard and Overdrive speed. 2) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed. 3) There is a hysteresis at the low-to-high switching threshold V TH. If a negative glitch crosses VTH but does not go below VTH - VHY, it will not be recognized (Figure 13, Case A). The hysteresis is effective at any 1-Wire speed. 4) There is a time window specified by the rising edge hold-off time t REH during which glitches are ignored, even if they extend below V TH - V HY threshold (Figure 13, Case B, t GL < t REH). Deep voltage droops or glitches that appear late after crossing the V TH threshold and extend beyond the t REH window cannot be filtered out and are taken as the beginning of a new time slot (Figure 13, Case C, tGL /g179 tREH). Only devices that have the parameters t FPD, V HY, and t REH specified in their electrical characteristics use the improved 1-Wire front end.

Figure 13. Noise Suppression Scheme RST 1-Wire Reset Pulse generated by master. PD 1-Wire Presence Pulse generated by slave. Select Command and data to satisfy the ROM function protocol. PIOR Command "PIO Access Read". PIOW Command "PIO Access Write". FF loop Indefinite loop where the master reads FF bytes.

DS2413: 1-Wire Dual Channel Addressable Switch 17 of 17 PIO ACCESS READ EXAMPLE Read the state of the PIOs 3 times. With only a single DS2413 connected to the bus master, the communication looks like this: MASTER MODE DATA (LSB FIRST) COMMENTS TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue “Skip ROM” command TX F5h Issue “PIO Access Read” command RX <3 data bytes> Read 3 PIO samples TX (Reset) Reset pulse RX (Presence) Presence pulse PIO ACCESS WRITE EXAMPLE Set both PIOs to 0 and then set PIOA to 1. Both PIOs are pulled high to V CC or VPUP by a resistor. With only a single DS2413 connected to the bus master, the communication looks like this: MASTER MODE DATA (LSB FIRST) COMMENTS TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue “Skip ROM” command TX 5Ah Issue “PIO Access Write” command TX FCh Write new PIO output state TX 03h Write inverted new PIO output state RX AAh Read confirmation byte RX F0h Read new PIO pin status TX FDh Write new PIO output state TX 02h Write inverted new PIO output state RX AAh Read confirmation byte RX C3h Read new PIO pin status TX (Reset) Reset pulse RX (Presence) Presence pulse Note: Usually, the PIO pin state and PIO Output Latch State are the same. To read from a PIO, the PIO Output Latch must be 1. If the PIO pin is then pulled low by a switch or external circuitry, the output latch state and pin state are different.

PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Ma xim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and spec ifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products /g183 Printed USA MAXIM is a registered trademark of Maxim Integrated Products, Inc. DALLAS is a registered trademark of Dallas Semiconductor Corporation