DS2411P+

DS2411 AD | Alldatasheet

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FEATURES

 Unique and Tested 64-Bit Registration Number (8-Bit Family Code Plus 48-Bit Serial Number Plus 8-Bit CRC Tester); Guaranteed No Two Pa rts Alike  Standby Current <1μA  Built-In Multidrop Controller Enables Multiple D S2411s to Reside on a Common 1-Wire Network  Multidrop Compatible with Other 1-Wire Products  8-Bit Family Code Identifies Device as DS2411 t o the 1-Wire Master  Low-Cost TSOC, SOT23-3, and Flip-Chip Su rface-Mount Packages  Directly Connects to a Single-Port Pin of a M icroprocessor and Communicates at up to 15. 4kbps  Overdrive Mode Boosts Communication Speed up to 125kbps  DS2411 Operating Range: 1.5V to 5.25V (VCC)  DS2411A Operating Range: 3V to 5.25V (no VCC), from -40°C to +85°C PIN DESCRIPTION NAME PIN SOT23 TSOC FLIP CHIP I/O 1 2 A1 VCC (DS2411) N.C. (DS2411A)* 2 6 B2 GND 3 1 B1 N.C. — 3, 4, 5 A2 *No connection to die, so pin may be connected to VCC. PIN CONFIGURATION 1 2 SOT23-3, Top View TSOC, Top View Flip Chip, Top View with Laser Mark, Contacts Not Visible. “rrd” = Revision/Date -1rrd A B

ORDERING INFORMATION

DS2411R+T&R -40°C to +85°C 3 SOT23-3 DS2411AR+T&R -40°C to +85°C 3 SOT23-3 DS2411P+ -40°C to +85°C 6 TSOC DS2411P+T&R -40°C to +85°C 6 TSOC DS2411X -40°C to +85°C 4 Flip Chip* +Denotes a lead(Pb)-free/RoHS-compliant package. T &R = Tape and reel. he DS2411X is RoHS qualified and comes in tape and reel.

DESCRIPTION

The DS2411 silicon serial number is a low -cost, electronic registration number with or without external power supply. It provides an absolutely unique i dentity that can be determined with a minimal electronic interface (typically, a single port pin of a microcontroller). The DS2411’s registration number is a 64-bit unique ROM that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit family c ode (01h). Data is transferred serially through the Analog Devices 1-Wire protocol. For the DS2411, an external power supply is required, extending the operating voltage range of the device below typical 1-W ire devices. The DS2411A does not require an external power supply and has a typical 1-Wire operating voltage range. However, it is functionally e quivalent to the DS2411, but with differing electrical parameters. DS2411 Silicon Serial Number with or without VCC Input 19-6131; Rev 4/22

I/O Voltage to GND -0.5V to +6V VCC Voltage to GND (DS2411) -0.5V to +6V I/O VCC Current (DS2411) ±20mA I/O Sink Current (DS2411A) ±10mA Operating Temperature Range -40°C to +85°C Junction Temperature +150°C Storage Temperature Range -55°C to +125°C Lead Temperature (TSOC, SOT23-3 only; soldering, 10s) +300°C Soldering Temperature (reflow) TSOC, SOT-23-3 Flip Chip +260°C +240°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

ELECTRICAL CHARACTERISTICS

(TA = -40°C to +85°C.) PARAMETER SYMBOL DEVICE CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC DS2411 (Note 1) 1.5 5.25 V Standby Supply Current ICCS V(I/O) ≤ VIL, or V(I/O) ≥ VIH 1 µs Active Supply Current ICCA 100 µs I/O PIN GENERAL DATA 1-Wire Pullup Voltage VPUP DS2411 (Note 1) VCC = VPUP 1.5 5.25 V DS2411A (Note 1) 3.0 5.25 1-Wire Pullup Resistance RPUP DS2411 (Notes 1, 2) 0.3 2.2 kΩ DS2411A (Notes 1, 2) 0.3 2.2 Power-Up Delay tPWRP DS2411 VCC stable to first 1-Wire command (Notes 1, 4) 1200 µs Input Capacitance CIO DS2411 (Note 4) 100 pF DS2411A (Notes 4, 5) 1000 Input Load Current IL DS2411 0V ≤ V(I/O) ≤ VCC -1 +1 µA DS2411A I/O pin at VPUP 0.05 1.75 6.7 High-to-Low Switching Threshold VTL DS2411 (Notes 4, 10, 11) 0.4 3.2 V DS2411A (Notes 4, 11, 18) 0.65 x VPUP Input Low Voltage VIL DS2411 (Note 1) 0.3 V DS2411A (Notes 1, 6) 0.5 Input High Voltage VIH DS2411 (Note 1) VCC - 0.3 V Low-to-High Switching Threshold VTH DS2411 (Notes 4, 10, 12) 0.75 3.4 V DS2411A (Notes 4, 12, 18) 0.75 x VPUP Switching Hysteresis VHY DS2411 (Notes 4, 6) 0.18 V DS2411A (Notes 4, 13, 18) 0.3 Output Low Voltage at 4mA VOL DS2411 (Note 14) IOL = 4mA 0.4 V DS2411A IOL = 4mA 0.4 Rising Edge Holdoff (Notes 4, 15) tREH DS2411 Standard speed 1.25 5 µs DS2411A Standard speed 1.3 DS2411 Overdrive speed 0.5 2.0 DS2411A Overdrive speed N/A (0) Recovery Time tREC DS2411 Standard speed, RPUP = 2.2kΩ (Note 1) 5 µs DS2411A Standard speed, RPUP = 2.2kΩ (Notes 1, 3) 5 DS2411 Overdrive speed, 2

PARAMETER SYMBOL DEVICE CONDITIONS MIN TYP MAX UNITS RPUP = 2.2kΩ (Note 1) DS2411A Overdrive speed, RPUP = 2.2kΩ (Notes 1, 3) 3 DS2411 Overdrive speed, directly prior to reset pulse; RPUP = 2.2kΩ (Note 1) DS2411A Overdrive speed, directly prior to reset pulse; RPUP = 2.2kΩ (Notes 1, 3) Timeslot Duration (Notes 1, 19) tSLOT DS2411 Standard speed 65 µs DS2411A Standard speed 65 DS2411 Overdrive VCC ≥ 2.2V 8 DS2411 Overdrive VCC ≥ 1.5V 10 DS2411A Overdrive speed 9 I/O PIN, 1-Wire RESET, PRESENCE DETECT CYCLE Reset Low Time tRSTL DS2411 Standard speed 480 640 µs DS2411A Standard speed 480 640 DS2411 Overdrive speed 60 80 DS2411A Overdrive speed 60 80 Presence-Detect High Time tPDH DS2411 Standard speed 15 60 µs DS2411A Standard speed 15 60 DS2411 Overdrive VCC ≥ 2.2V 2 6 DS2411 Overdrive VCC ≥ 1.5V 2 8.5 DS2411A Overdrive speed 2 6 Presence-Detect Low Time tPDL DS2411 Standard speed 60 240 µs DS2411A Standard speed 60 240 DS2411 Overdrive VCC ≥ 2.2V 8 24 DS2411 Overdrive VCC ≥ 1.5V 8 30 DS2411A Overdrive speed 8 24 Presence-Detect Sample Time (Notes 1, 7) tMSP DS2411 Standard speed 60 75 µs DS2411A Standard speed 60 75 DS2411 Overdrive VCC ≥ 2.2V (Note 1) 6 10 DS2411 Overdrive VCC ≥ 1.5V (Note 1) 8.5 10 DS2411A Overdrive speed 6 10 Presence-Detect Fall Time (Notes 4, 16) tFPD DS2411 Standard speed 0.4 8 µs DS2411 Overdrive speed 0.05 1 I/O PIN, 1-Wire WRITE Write-0 Low Time (Notes 1, 8, 17) tW0L DS2411 Standard speed 60 120 µs DS2411A Standard speed 60 120 DS2411 Overdrive VCC ≥ 2.2V 6 16 DS2411 Overdrive VCC ≥ 1.5V 8 16 DS2411A Overdrive 6 15.5 Write-1 Low Time (Notes 1, 8, 17) tW1L DS2411 Standard speed 5 15 µs DS2411A Standard speed 1 15 DS2411 Overdrive speed 1 2.0 DS2411A Overdrive speed 0.25 2 I/O PIN, 1-Wire READ Read Low Time (Notes 1, 9) tRL DS2411 Standard speed 5 15 - δ µs DS2411A Standard speed 5 15 - δ DS2411 Overdrive speed 1 2 - δ DS2411A Overdrive speed 0.25 2 - δ Read Sample Time (Notes 1, 9) tMSR DS2411 Standard speed tRL + δ µs DS2411A Standard speed 15 DS2411 Overdrive speed 2 DS2411A Overdrive speed 2

Note 1: System requirement. Note 2: Full R PUP range is guaranteed by design and simulation and not production tested. Production testing performed at a fixed R PUP value. Maximum allowable pullup resistance is a function of the number of 1- Wire devices in the system and 1- Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1 -Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required. Note 3: Applies to a single device attached to a 1-Wire line. Note 4: Guaranteed by design, simulation only. Not production tested. Note 5: Maximum value represents the internal parasite capacitance when V PUP is first applied. Once the parasite capacitance is charged, it does not affect normal communication. Note 6: The voltage on I/O must be less than or equal to VILMAX whenever the master drives the line low. Note 7: The interval after tRSTL during which a bus master can read a logic ‘0’ on I/O if there is a DS28E07 present. The power -up presence detect pulse could be outside this interval but will be complete within 1.5ms (DS2411) or 2ms (DS2411A) after power-up. Note 8: ε in Figure 7 represents the time required for the pullup circuitry to pull the voltage on I /O up from VIL to VIH. The actual maximum duration for the master to pull the line low is t W1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. Note 9: δ in Figure 7 represents the time required for the pullup circuitry to pull the voltage on I /O up from VIL to the input -high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. Note 10: VTL and VTH are functions of V CC and temperature. The V TH and VTL maximum specifications are valid at VCC = 5.25V. In any case, VTL < VTH < VCC. Note 11: Voltage below which during a falling edge on I/O, a logic ‘0’ is detected. Note 12: Voltage above which during a rising edge on I/O, a logic ‘1’ is detected. Note 13: After V TH is crossed during a rising edge on I/O, the voltage on I/O has to drop by V HY to be detected as logic ‘0’. Note 14: The I-V characteristic is linear for voltages less than 1V. Note 15: The earliest recognition of a negative edge is possible at t REH after VTH has been reached on the previous edge. Note 16: The interval during the negative edge on I/O at the beginning of a presence-detect pulse between the time at which the voltage is 90% of VPUP and the time the voltage is 10% of VPUP. Note 17: The i nterval begins when the voltage drops below V TL during a negative edge on I/O and ends when the voltage rises above VTH during a positive edge on I/O. Note 18: VTL, VTH, and V HY are a function of the internal supply voltage, which is a function of V PUP, RPUP, 1-Wire timing, and capacitive loading on I /O. Lower V PUP, higher R PUP, shorter t REC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Note 19: Defines the maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN). OPERATION The DS2411’s registration number is accessed through a single data line. The 48-bit serial number, 8-bit family code, and 8-bit CRC are retrieved using the Analog Devices 1-Wire protocol. This protocol defines bus transactions in terms of the bus state during specified time slots that are bus -master-generated falling edges on the I/O pin. All data is read and written least significant bit first. The DS2411 requires a delay between V CC power-up and initial 1-Wire communication, t PWRP (1200µs). The DS2411A requires a delay between I/O power -up and initial 1-Wire communication of 2ms. During this time the DS2411 or DS2411A may issue presence-detect pulses. 1-Wire BUS SYSTEM The 1-Wire bus has a single bus master and one or more slaves. In all instances, the DS2411 is a slave device. The bus master is typically a microcontroller . The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal type and timing).

Figure 4. BUS MASTER CIRCUIT the bus load characteristics.

The communication sequence for accessing the DS2411 through the 1-Wire bus is as follows:  Initialization  ROM Function Command  Read Data INITIALIZATION All tran sactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know tha t the DS2411 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the three ROM function commands. All ROM function command codes are 1 byte long. A list of these commands follows (see the flowchart in Figure 5). Read ROM [33h] This command allows the bus master to read the DS2411’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command should only be used if t here is a single slave device on the bus. If more than one slave is present on the bus, a data collision results when all slaves try to transmit at the same time (open drain produces a wired-AND result), and the resulting registration number read by the master will be invalid. Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1- Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device par ticipating in the search outputs the true value of its registration number bit. On the second slot, each slave device participating in the search outputs the complemented value of its registration number bit. On the third slot, the master writes the true v alue of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which st ate to write, the bus master branches in the romcode tree. After one complete pass, the bus master knows the registration number of a single device. Additional passes identify the registration numbers of the remaining devices. Refer to App Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. Overdrive Skip ROM [3Ch] This command causes all overdrive-capable slave devices on the 1-Wire network to enter overdrive speed (OD = 1). All communication following this command has to occur at overdrive speed until a reset pulse of minimum 480µs duration resets all devices on the bus to regular speed (OD = 0). To subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed has to be issued followed by a read ROM or search ROM command sequence. Overdrive speeds up the time for the search process.

Figure 5. ROM FUNCTIONS FLOW CHART

The DS2411 requires stri ct protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, and Read Data. Except for the presence pulse the bus master initiates all these signals. The DS2411 can communicate at two different speeds: standard speed and Overdrive speed. If not explicitly set into the Overdrive mode, the DS2411 will communicate at standard speed. While in Overdrive Mode the fast timing applies to all waveforms. To get from idle to active, the v oltage on the 1-Wire line needs to fall from V PUP below the threshold VTL. To get from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The voltage VILMAX is relevant for the DS2411 when determining a logical level, but not for triggering any events. The initialization sequence required to begin any communication with the DS2411 is shown in Figur e 6. A Reset Pulse followed by a Presence Pulse indicates the DS2411 is ready to receive data, given the correct ROM and memory function command. In a mixed population network, the reset low time t RSTL needs to be long enough for the slowest 1-Wire slave device to recognize it as a reset pulse. If the bus master uses slew-rate control on the falling edge, it must pull down the line for tRSTL + tF to compensate for the edge. A t RSTL duration of 480µs or longer will exit the Overdrive Mode returning the devic e to standard speed. If the DS2411 is in Overdrive Mode and t RSTL is no longer than 80µs, the device will remain in Overdrive Mode. After the bus master has released the line it goes into receive mode (RX). Now, the 1-Wire bus is pulled to VPUP via the pullup resistor or, in case of a DS2480B driver, by active circuitry. When the threshold V TH is crossed, the DS2411 waits for tPDH and then transmits a Presence Pulse by pulling the line low for t PDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP. The t RSTH window must be at least the sum of t PDHMAX, t PDLMAX, and t RECMIN. Immediately after tRSTH is expired, the DS2411 is ready for data communication. In a mixed population network, t RSTH should be extended to minimum 480µs at standard speed and 48µs at Overdrive speed to accommodate other 1- Wire devices. Read/Write Time Slots Data communication with the DS2411 takes place in time slots that carry a single bit each. Write time slots transport data from bus mas ter to slave. Read time-slots transfer data from slave to master. The definitions of the write and read time slots are illustrated in Figure 7. All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the threshold V TL, the DS2411 starts its internal timing generator that determines when the data line will be sampled during a write time slot and how long data will be valid during a read time slot. Master to Slave For a write-one time slot, the vol tage on the data line must have crossed the V THMAX threshold after the write-one low time t W1LMAX is expired. For a write -zero time slot, the voltage on the data line must stay below the V THMIN threshold until the write-zero low time t W0LMIN is expired. For most reliable communication the voltage on the data line should not exceed V ILMAX during the entire tW0L window. After the VTHMAX threshold has been crossed, the DS2411 needs a recovery time t REC before it is ready for the next time slot.

A read-data time slot begins like a write-one time sl ot. The voltage on the data line must remain below VTLMIN until the read low time t RL is expired. During the t RL window, when responding with a 0, the DS2411 will start pulling the data line low; its internal timing generator determines when this pull -down ends and the voltage starts risi ng again. When responding with a 1, the DS2411 will not hold the data line low at all, and the voltage starts rising as soon as tRL is over. The sum of t RL + δ (rise rime) on one side and the internal timing generator of the DS2411 on the other side defi ne the master sampling window (t MSRMIN to tMSRMAX) in which the master must perform a read from the data line. For most rel iable communication, t RL should be as short as permissible and the master should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until t SLOT is expired. This guarantees sufficient recovery time t REC for the D S2411 to get ready for the next time slot. Improved Network Behavior In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire driver). 1-Wire networks therefore are susceptible to noise of various origins. Depending on the physical size and topology of the network, reflections from end points and branch points can add up or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the m aster and, as a consequence, result in a search ROM command coming to a dead end. For better performance in network applications, the DS2411 uses a new 1-Wire front end, which makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave device itself. The 1-Wire front end of the DS2411 differs from traditional slave devices in four characteristics. 1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line impedance than a digitally switched transistor, converting the high frequency ringing known from traditional devices into a smoother low -bandwidth transition. The slew rate control is specified by the parameter t FPD, which has different values for standard and Overdrive s peed. This function is only available for the VCC-powered version. 2) There is additional low -pass filtering in the circuit that detects the falling edge at the beginning of a time slot. This reduces the sensitivity to high-frequency noise. As a consequence, the duration of the setup time t SU at standard speed is larger than with traditional devices. This additional filtering does not apply at Overdrive speed. 3) There is a hysteresis at the low -to-high switching threshold VTH. If a negative glitch crosses V TH but doesn’t go below VTH - VHY, it will not be recognized (Figure 8, Case A). The hysteresis i s effective at any 1-Wire speed. 4) There is a time window specified by the rising edge hold-off time t REH during which glitc hes will be ignored, even if they extend below VTH - VHY threshold (Figure 8, Case B, t GL < tREH). Deep voltage droops or glitches that appear late after crossing the V TH threshold and extend beyond the t REH window cannot be filtered out and will be taken as beginning of a new time slot (Figure 8, Case C, tGL ≥ tREH). The duration of the hold-off time is independent of the 1-Wire speed. Only devices which have the parameters VHY and tREH specified in their electrical characteristics use the improved 1-Wire front end.

NOISE SUPPRESSION SCHEME Figure 8 VPUP VTH VHY tREH tGL tREH tGL Case A Case CCase B CRC GENERATION To validate the registration number transmitted from the DS2411, the bus master can generate a CRC value from the 8-bit family code and unique 48-bit serial number as it is received. If the CRC matches the last 8 bits of the registration number, the transmission is error free. The equivalent polynomial function of this CRC is: CRC = x 8 + x 5 + x 4 + 1. For more information on generating CRC values see Application Note 27. CUSTOM DS2411 Customization of a portion of the unique 48-bit serial number by the customer is available. Maxim will register and assign a specific customer ID in the 12 most significant bits of the 48-bit field. The next most significant bits are selectable by the customer as a starting value, and the least significant bits are non- selectable and will be automatically incremented by one. Certain quantities and conditions apply for these custom parts. Contact your Maxim sales representative for more information.

PACKAGE INFORMATION

For the latest package outline information and land patterns (footprints), go to www.maxim -ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN SOT23-3 U3+2 21-0051 90-0179

6 TSOC D6+1 21-0382 90-0321

4 Flip Chip BF411-1 21-0282 Refer to 21-0282

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third pa rties th at may res ult from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. © 2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners .

REVISION HISTORY

020703 Initial release —

Corrected the Flip Chip pin configuration. 1 Section 1-Wire Signaling rewritten. 8, 10 Added section Improved Network Behavior. 10, 11 122106 Added flip chip top marking and URL to package outline drawing. Added SOT23-3 and TSOC lead-free part numbers to Ordering Information. 1 Updated ordering information, lead temperature, soldering temperature. 1, 2 In the Electrical Characteristics table, applied note 11 to the tW0L specification; deleted ε from the tW1L specification; corrected the tRL specification (replaced ε with δ, applied note 12), and added more details to notes 4, 11, and 12. 3, 4 Deleted the DS2480B (5V operation) master circuit from Figure 4. 5 Updated the Package Information section and added Revision History. 11, 12 Updated title, Features, Pin Description, Ordering Information, Description, Absolute Maximum Ratings, Electrical Characteristics, Operation, Figure 3, Figure 4, Improved Network Behavior, and Package Information 1-5, 10, 11 4/22 Removed DS2411A from the title 1