DS2408

DS2408 MAXIM | Alldatasheet

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Technical content

1-Wire 8-Channel Addressable Switch www.maxim-ic.com

FEATURES

/g167/g32Eight Channels of Programmable I/O with Open-Drain Outputs /g167/g32On-Resistance of PIO Pulldown Transistor 100/g87 (max); Off-Resistance 10M/g87 (typ) /g167/g32Individual Activity Latches Capture Asynchronous State Changes at PIO Inputs for Interrogation by the Bus Master /g167/g32Data-Strobe Output to Synchronize PIO Logic States to External Read/Write Circuitry /g167/g32Built-in Multidrop Controller Ensures Compatibility with Other Dallas Semiconductor 1-Wire® Net Products /g167/g32Supports 1-Wire Conditional Search Command with Response Controlled by Programmable PIO Conditions /g167/g32Unique Factory-Lasered 64-Bit Registration Number Ensures Error-Free Device Selection and Absolute Part Identity /g167/g32Communicates to Host with a Single Digital Signal at 15.3kbps or 100kbps using 1-Wire Protocol /g167/g32Operating Range: 2.8V to 5.25V, -40°C to +85°C PIN CONFIGURATION N.C. N.C. RSTZ N.C. VCC I/O GND N.C. 150-mil SO

ORDERING INFORMATION

DS2408S -40/g176C to +85/g176C 16-Pin SO, 150 mil DS2408S /T&R -40/g176C to +85/g176C Tape-and-Reel of DS2408S

DESCRIPTION

The DS2408 is an 8-cha nnel, programmable I/O 1-Wire chip. P IO outputs are confi gured as open -drain and provide an on resistance of 100/g87 max. A robust PIO channel-access communication protocol ensures that PIO output-setting changes occur error-free. A data-valid strobe output can be used to latch PIO logic states into external circuitry such as a D/A converter (DAC) or microcontroller data bus. DS2408 operation is controlled over the single-conductor 1-Wire bus. Device communication follows the standard Dallas Semiconductor 1-Wire protocol. Each DS2408 has its own unalterable and unique 64-bit ROM registration number that is factory lasered into the chip. The registration number guarantees unique identification and is used to addr ess the device in a multidrop 1-W ire net environment. Multiple DS 2408 devices can reside on a common 1-Wire bus and can operate independently of each other. The DS2408 also supports 1-W ire conditional search cap ability based on P IO conditions or power-on-reset activit y; the conditions to cause participa tion in the conditional search ar e pro grammable. The DS2408 has an optional VCC supply connection. When an external supply is absent, device power is supplied parasitically from the 1-Wire bus. When an external supply is present, PIO states are maintained in the absence of the 1-Wire bus pow er source. The RSTZ sig nal is c onfigurable to serve as either a hard-wired reset for the PIO output or as a strobe for external circuitry to indicate that a PIO write or PIO read has completed. 1 of 36 061604 1-Wire is a registered trademark of Dallas Semiconductor.

ABSOLUTE MAXIMUM RATINGS* P0 to P7, RSTZ, I/O Voltage to GND -0.5V, +6V P0 to P7, RSTZ, I/O combined sink current 20mA Operating Temperature Range -40°C to +85°C Junction Temperature +150°C Storage Temperature Range -55°C to +125°C Lead Temperature (10s) See J-STD-020A specification * This is a stress rating o nly and functional opera tion of the de vice at the se or any other conditions above those indic ated in the ope ration se ctions of this spe cification is not implie d. Ex posure to absolute maximum rating conditions for extended periods of time may affect reliability.

ELECTRICAL CHARACTERISTICS

(VCC = 0V or /g179 VPUP, TA = -40°C or +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Standard speed 2.8 5.25 1-Wire Pullup Voltage VPUP Overdrive speed 3.3 5.25 V Standby Supply Current ICCS VCC at VPUP, I/O pin at 0.3V 1 µA I/O Pin General Data 1-Wire Pullup Resistance RPUP (Notes 1, 2) 2.2 k/g87 Input Capacitance CIO (Notes 3, 4) 1200 pF Input Load Current IL I/O pin at VPUP, VCC at 0V 1 µA High-to-Low Switching Threshold VTL (Notes 4, 5, 6) 0.5 3.2 V Input-Low Voltage VIL (Notes 1, 7) 0.30 V Low-to-High Switching Threshold VTH (Notes 4, 5, 8) 0.8 3.4 V Switching Hysteresis VHY (Notes 9, 4) 0.16 0.73 V Output-Low Voltage at 4mA VOL (Note 10) 0.4 V Standard speed, RPUP = 2.2k/g87 5 Overdrive speed, RPUP = 2.2k/g87 2 Recovery Time (Note 1) tREC Overdrive speed, Directly prior to reset pulse; RPUP = 2.2k/g87 µs Standard speed 0.5 5 Rising-Edge Hold-off Time (Notes 11, 4) tREH Overdrive speed 0.5 2 µs Standard speed 65 Timeslot Duration (Notes 1, 12) tSLOT Overdrive speed 10 µs 2 of 36

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I/O Pin, 1-Wire Reset, Presence-Detect Cycle Standard speed, VPUP > 4.5V 480 720 Standard speed 660 720 Reset-Low Time (Notes 1, 12) tRSTL Overdrive speed 53 80 µs Standard speed 15 60 Presence-Detect High Time (Note 12) tPDH Overdrive speed 2 7 µs Standard speed, VPUP > 4.5V 1 5 Standard speed 1 8 Presence-Detect Fall Time (Note 13) tFPD Overdrive speed 1 µs Standard speed, VPUP > 4.5V 60 240 Standard speed 60 280 Presence-Detect Low Time (Note 12) tPDL Overdrive speed 7 27 µs Standard speed, VPUP > 4.5V 65 75 Standard speed 68 75 Presence-Detect Sample Time (Note 1) tMSP Overdrive speed 8 9 µs I/O Pin, 1-Wire Write Standard speed 60 120 Write-0 Low Time (Notes 1, 12) tW0L Overdrive speed 8 13 µs Standard speed 5 15 - /g101 Write-1 Low Time (Notes 1, 12, 14) tW1L Overdrive speed 1 1.8 - /g101 µs Standard speed 15 60 Write Sample Time (Slave Sampling) (Note 12) tSLS Overdrive speed 1.8 8 µs I/O Pin, 1-Wire Read Standard speed 5 15 - /g100 Read-Low Time (Notes 1, 15) tRL Overdrive speed 1 1.8 - /g100 µs Standard speed 15 60 Read-0 Low Time (Data From Slave) (Note 12) tSPD Overdrive speed 1.8 8 µs Standard speed tRL + /g100 15 Read-Sample Time (Notes 1, 12, 15) tMSR Overdrive speed tRL + /g100 1.8 µs P0 to P7, RSTZ Pin Input-Low Voltage VIL (Notes 1, 7) 0.30 V Input-High Voltage VIH VX = max (VPUP,VCC) (Note 1) VX - 0.8 5.25 V Output-Low Voltage at 4mA VOL (Note 10) 0.4 V Leakage Current ILP 5.25V at the pin 1 µA Output Fall Time tFPIO (Notes 4, 16) 100 ns Minimum-Sensed PIO Pulse tPWMIN (Notes 4, 17) 1 5 µs 3 of 36

Note 1: System Requirement Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required. Note 3: If a 2.2k/g87 resistor is used to pull up the data line to VPUP, 5µs after power has been applied, the parasite capacitance does not affect normal communications. Note 4: Guaranteed by design—n ot production tested. Note 5: VTL, VTH are a function of the internal supply voltage. Note 6: Voltage below which, during a falling edge on I/O, a logic '0' is detected. Note 7: The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line low. Note 8: Voltage above which, during a rising edge on I/O, a logic '1' is detected. Note 9: After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to be detected as logic '0'. Note 10: The I-V characteristic is linear for voltages less than 1V. Note 11: The earliest recognition of a negative edge is possible at tREH after VTH has been reached before. Note 12: Highlighted numbers are NOT in compliance with the published 1-Wire standards. See comparison table below. Note 13: Interval during the negative edge on I/O at the beginning of a presence detect pulse between the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of VPUP. Note 14: /g101 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. Note 15: /g100 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high threshold of the bus master. Note 16: Interval during the device-generated negative edge on any PIO pin or the RSTZ pin between the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of VPUP. PIO pullup resistor = 2.2k/g87. Note 17: Width of the narrowest pulse which trips the activity latch (for any PIO pin) or causes a reset (for the RSTZ pin). For a pulse duration tPW: If tPW < tPWMIN(min), the pulse will be rejected. If tPWMIN(min) < tPW < tPWMIN(max), the pulse may or may not be rejected. If tPW > tPWMIN(max) the pulse will be recognized and latched. Note 18: Maximum instantaneous pulldown current through all port pins and the RSTZ pin combined. No requirement for current balance among different pins. STANDARD VALUES DS2408 VALUES STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED PARAMETER NAME MIN MAX MIN MAX MIN MAX MIN MAX tRSTL 480µs (undef.) 48µs 80µs 660µs 720µs 53µs 80µs tPDH 15µs 60µs 2µs 6µs 15µs 60µs 2µs 7µs tPDL 60µs 240µs 8µs 24µs 60µs 280µs 7µs 27µs tW0L 60µs 120µs 6µs 16µs 60µs 120µs 8µs 13µs tSLS, tSPD 15µs 60µs 2µs 6µs 15µs 60µs 1.8µs 8µs 1) Intentional change, longer recovery-time requirement due to modified 1-Wire front end. 4 of 36

1 N.C. Not Connected 2 P0 I/O Pin of Channel 0. Logic input/open-drain output with 100/g87 maximum on-resistance; 0V to 5.25V operating range. Power-on default is indeterminate. If it is application-critical for the outputs to power up in the "off" state, the user should attach an appropriate power-on-reset circuit or supervisor IC to the RSTZ pin. 3 VCC Optional Power Supply Input. Range 2.8V to 5.25V; must be tied to GND if not used. 4 I/O 1-Wire Interface. Open-drain, requires external pullup resistor.

5 GND Ground

6 N.C. Not Connected 7 P7 I/O Pin of Channel 7. Same characteristics as P0. 8 P6 I/O Pin of Channel 6. Same characteristics as P0. 9 P5 I/O Pin of Channel 5. Same characteristics as P0.

10 RSTZ

SW configurable PIO reset input ( RST ) or open-drain strobe output (STRB ). When configured as RST , a LOW input sets all PIO outputs to the "off" state by setting all bits in the PIO Output Latch State Register. When configured as STRB , an output strobe will occur after a PIO write (see Channel-Access Write command) or after a PIO Read (see Channel- Access Read command). The power-on default function of this pin is RST .

11 P4 I/O pin of channel 4; same characteristics as P0

12 P3 I/O pin of channel 3; same characteristics as P0

13 P2 I/O pin of channel 2; same characteristics as P0

14 P1 I/O pin of channel 1; same characteristics as P0

15 N.C. Not connected 16 N.C. Not connected APPLICATION The DS2408 is a multipurpose device. T ypical applications include port expander for microcontr ollers, remote multichannel sensor/actuator, communication and control unit of a microterminal, or as network interface of a mic rocontroller. Typical application circuits and communication examples are found later in this data sheet (Figures 17 to 22). OVERVIEW 5 of 36 Figure 1 shows the relationships between the maj or function blocks of the DS2408. The device h as two main data components: 1) 64-bit lasered ROM, and 2) 64-bit register page of control and status registers. Figure 2 shows the hierarchical structure of the 1-Wire protocol. The bus master must first provide one of the ei ght ROM fu nction commands: 1) Read R OM, 2) M atch ROM, 3 ) Search ROM, 4) Conditional Search ROM, 5 ) Skip ROM, 6) Ove rdrive-Skip ROM, 7) Overd rive-Match ROM, or 8) R esume. Upon completion of an Overd rive R OM com mand b yte ex ecuted at st andard speed, t he devi ce wi ll ent er overdrive mode, where all subsequent communication occurs at a higher speed. The protocol required for these ROM function co mmands is de scribed in F igure 12. Aft er a ROM function command is success- fully executed, the control functions become accessible and the master ma y provide any one of the five available commands. The protocol for these control commands is described in Figure 8. All data is read and written least significant bit first.

if it is configured as STRB . See the Channel-access commands description for details on STRB . Figure 6. CHANNEL I/O AND RSTZ SIMPLIFIED LOGIC DIAGRAM

This register is read/write. Each bi t is associated with the respective P IO channel as shown in F igure 7. dress 008Dh. This register can only be written through the Write Conditional Search Registers command. This register is read/write. Each bit is associated with the respective PIO channel as shown in Figure 7. This register is cleared to 00h by a power-on reset. Figure 7. Conditional Search Logic

The data in this r egister reports status information, determines the function of the RSTZ pin a nd further configures the device for conditional search. This register can only be written through the W rite Condi- tional Search Registers command. Control/Status Register Bitmap ADDR b7 b6 b5 b4 b3 b2 b1 b0 008Dh VCCP 0 0 0 PORL ROS CT PLS This register is read/w rite. Without VCC supply, this register reads 08h after a power-on reset. The func- tional assignments of th e individual b its are ex plained in the table below. Bits 4 to 6 have no fu nction; they will always read 0 and cannot be set to 1. Control/Status Register Details BIT DESCRIPTION BIT(S) DEFINITION PLS: Pin or Activity Latch Select b0 Selects either the PIO pins or the PIO activity latches as input for the conditional search. 0: pin selected (default) 1: activity latch selected CT: Conditional Search Logical Term b1 Specifies whether the data of two or more channels needs to be OR’ed or AND’ed to meet the qualifying condition for the device to respond to a conditional search. If only a single channel is selected in the channel selection mask (008Bh) this bit is a don't care. 0: bitwise OR (default) 1: bitwise AND ROS: RSTZ Pin Mode Control b2 Configures RSTZ as either RST input or STRB output 0: configured as RST input (default) 1: configured as STRB output PORL: Power-On Reset Latch b3 Specifies whether the device has performed a power-on reset. This bit can only be cleared to 0 under software control. As long as this bit is 1 the device will always respond to a conditional search. VCCP: VCC Power Status (Read-Only) b7 For VCC powered operation the VCC pin needs to be tied to a voltage source /g179 VPUP. 0: VCC pin is grounded 1: VCC -powered operation The interaction of the v arious signals that determine whether the d evice responds to a conditional s earch is illustrated in Figure 7. The selection mask SM selects the participating channels. The polarity selection SP determines for each channel whether the channel signal needs to be 1 or 0 to qu alify. The PLS bit determines whether all channel signals are taken from the activity latches or I/O pins. The signals of all channels a re fed into an AND gate as well as an OR gate. Th e C T bit finally s elects the AND’ed or OR’ed result as the conditional search response signal CSR. Note on CT bit: OR The qualifying condition is met if the input (pin state or activity latch) for one or more selected channels matches the corresponding polarity. AND For the qualifying condition to be met, the input (pin state or activity latch) for every selected channel must match the corresponding polarity. 11 of 36

Figure 8-1. CONTROL FUNCTIONS FLOW CHART Bus Master TX TA1 (T7:T0), TA2 (T15:T8) YN F0h Read PIO Reg.? Y N Address < 90h? To Figure 8 2nd Part From Figure 8 2nd Part Bus Master TX Control Function Command To ROM Functions Flow Chart (Figure 12) From ROM Functions Flow Chart (Figure 12) DS2408 sets Register Address = (T15:T0) Bus Master RX Data Byte from Register Address Bus Master RX CRC16 of Command, Address, Data Bytes Bus Master RX “1”s Y N DS2408 Incre- ments Address Counter Y Y N N Master TX Reset? Address < 90h? Master TX Reset? Master TX Reset? Y N Note: To read the three PIO state and latch register bytes, the target address should be 0088h. Returned data for a target address <0088h is undefined. Address = 88h? Y N DS2408 Samples PIO Pin Status Note 1) See the command description for the exact timing of the PIO pin sampling. 12 of 36

Figure 8-2. CONTROL FUNCTIONS FLOW CHART From Figure 8 1st Part To Figure 8 1st Part To Figure 8 3rd Part From Figure 8 3rd Part F5h Channel Access Read? DS2408 Samples PIO Pin Status PIO Sample Counter = 0 Y N Sample Count = 31? Y NMaster TX Reset? Bus Master RX PIO Pin Status DS2408 Increments PIO Sample Counter DS2408 Samples PIO Pin Status Bus Master RX PIO Pin Status PIO Sample Counter = 0 DS2408 Samples PIO Pin Status Bus Master RX CRC16 of Command and 32 Bytes of PIO Pin Status (1st Pass) CRC16 of 32 Bytes of PIO Pin Status (Subsequent Passes) Y N5Ah Channel Access Write? Bus Master TX new PIO Output Data Byte Bus Master TX inverted new PIO Output Data Byte Transmission OK? DS2408 Updates PIO Pin Status Bus Master RX Confirmation AAh DS2408 Samples PIO Pin Status Bus Master RX PIO Pin Status Y N Master TX Reset? N Y Bus Master RX “1”s Y N Master TX Reset? Note 1) See the command description for the exact timing of the PIO pin sampling and updating. Note 2) If the RSTZ pin is con- figured as output, a STRB\\ is generated during the first two bits of this byte. N Y 2) 2) 1) 1) 1) 13 of 36

Figure 8-3. CONTROL FUNCTIONS FLOW CHART From Figure 8 2nd Part To Figure 8 2nd Part CCh Write C. Search Reg.? Bus Master TX TA1 (T7:T0), TA2 (T15:T8) N Y 8Bh/g163 Address /g163 8Dh? Y NMaster TX Reset? Bus Master TX Data Byte DS2408 Incre- ments Address Counter DS2408 Copies Data to Register Y NC3h Reset Activity Latches? DS2408 Clears all PIO Activity Latches Bus Master RX Confirmation AAh Y N Master TX Reset? Y N Master TX Reset? Bus Master RX “1”s Y N Master TX Reset? Note: To read 8Bh to 8Dh use the Read PIO Registers command. Y N 14 of 36

explicitly set into the overdrive mode, the device operates at standard speed. terminated at any time with a 1-Wire Reset. Figure 9. CHANNEL-ACCESS READ TIMING sample, or the MS byte of a CRC16. The example shows a read-1 time slot. Channel-Access Write command.

the sampling point is independent of the bit value being transmitted and the data direction (see Figure 9). the next data byte at the PIO for the master to read through the 1-Wire line. nated at any time with a 1-Wire Reset. Figure 10. CHANNEL-ACCESS WRITE TIMING "off" state and the PIO output latches will all read "1". See Figure 6 for a schematic of the logic.

the data pattern AAh. If the RSTZ pin is configured as STRB , a strobe signal will be generated during the transmission of the first two (least significant) bits of the confirmation byte. The strobe can signal a FIFO or a microcontroller to read the new data byte from the PIO. While the last bit of the confirmation byte is transmitted, the DS2408 samples the status of the P IO pins, as shown in Figure 9, and s ends it t o the master. Depending on the data, the master can either continue writing more data to the PIO or issue a 1- Wire reset to end the command. Write Conditional Search Register [CCh] This command is used to tell the DS2408 the conditions that need to be met for the device to respond to a Conditional Search command, to define the function of the RSTZ pin and to clear the power-on reset flag. After issuing the command the master sends the 2-byte target address, which must be a value between 008Bh and 008Dh. Next the master sends the byte to be written to the addressed cell. If the address was valid, the byte is imme diately written to its location in the register page. The master now can either end the command b y issuing a 1-W ire reset or send another b yte for the nex t higher address. Once register address 008Dh has be en written, any subsequent data b ytes will be ig nored. The master has to send a 1- Wire reset to end the co mmand. Since the W rite Conditional Search Register fl ow does not inclu de any error-checking for the new r egister data, it is imp ortant to ve rify correct writing by reading the registers using the Read PIO Registers command. Reset Activity Latches [C3h] Each PIO channel includes an activity latch that is set whenever there is a state transition at a PIO pin. This c hange ma y be cause d b y a n external e vent/signal or b y writing t o the P IO. D epending o n the application there may be a need t o reset the activity latch after having captured and serviced an external event. Since there is onl y read access to the PI O Activity Latch State Re gister, the DS2408 supports a special c ommand to re set the la tches. A fter ha ving re ceived the c ommand c ode, the d evice r esets a ll activity latches simultaneously. There are two ways for the ma ster to verify the execution of the Reset Activity Latches command. The easiest w ay is to st art re ading from the 1-W ire line right after the command code is tr ansmitted. In this c ase the master will r ead AAh b ytes until it se nds a 1-Wire reset. The other way to verify execution is to read register address 008Ah. 1-WIRE BUS SYSTEM The 1-W ire bus i s a s ystem t hat has a si ngle bu s m aster and on e o r m ore sl aves. In al l i nstances t he DS2408 is a slave device. The bus mast er is t ypically a microcontroller or PC. F or small config urations the 1-Wire communication signals can be generated under software control using a sin gle port pin. F or multisensor networks, th e DS2480B 1-W ire line driver chip or serial po rt adapters bas ed on thi s chip (DS9097U series) are recommended. This simplifies th e hardware design and fr ees the microprocessor from responding in real time. The discussion of this b us system is broken down into three topics: hard ware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. HARDWARE CONFIGURATION The 1-Wire bus has onl y a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain or tri-state outputs. The 1-Wire port of the DS2408 is open-drain with an internal circuit equivalent to that shown in Figure 11. 17 of 36

Figure 11. HARDWARE CONFIGURATION is 100kbps. The value of the pullup resistor prim arily depends on the net work size and load conditions. speed and 1.5k/g87 for overdrive speed. values must be modified (see EC table).

The protocol for accessing the DS2408 through the 1-Wire port is as follows: /g167/g32Initialization /g167/g32ROM Function Command /g167/g32Control Function Command /g167/g32Transaction/Data Illustrations of the transaction sequence for the various control function commands are found later in this document. INITIALIZATION All tr ansactions on the 1-Wire bus be gin with an initia lization se quence. The initia lization se quence consists of a reset pulse transmitted by the bus m aster followed by presence pulse(s) transmitted by the slave(s). Th e p resence p ulse lets the bus master know that th e DS2408 is on the bus and is re ady to operate. For more details, see the 1-Wire Signaling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the sev en ROM function commands. All ROM f unction c ommands a re e ight bits long . A list of the se c ommands f ollows ( see the f lowchart in Figure 12). Read ROM [33h] This command allows the bus master to read the DS2408's 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This c ommand can only be used if there is a single device on the bus. If more than one slave is pr esent on the bus, a data collision will occur when all slaves try to tr ansmit at the same time (open drain will produc e a wired-A ND result). The resultant famil y code and 48-bit serial numbe r will result in a mismatch of the CRC. Match ROM [55h] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a spe- cific DS2408 on a multidrop bus. Onl y the DS2408 that exactly matches the 64-bit ROM sequen ce will respond to the following control function command. A ll slaves that do not match the 64-bit R OM se- quence will wait for a reset pulse. This command can be used with either single or multiple devices on the bus. Search ROM [F0h] When a s ystem is initiall y b rought up, the bus master mi ght not know the number of d evices o n the 1-Wire bus or their 64-bit ROM codes. The Sear ch R OM com mand al lows t he bus m aster t o use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple three-step routine: read a bit, r ead the complement of the bit, the n write the desired value of that bit. The bus m aster performs this simple, three-step routine on each bit of the ROM. After one complete pass, the bus ma ster knows the contents of the ROM in one devi ce. The remaining numbe r of d evices and their ROM code s ma y b e ide ntified b y a dditional pa sses. Se e Application Note 187 for a detailed discussion on the Sear ch ROM command process including a software example. Conditional Search [ECh] 19 of 36 The Conditional Search ROM command operates similarly to the Search ROM command except that only devices fulfilling the spe cified condition will part icipate in the search. Th e condition is specified by the Conditional Search chan nel and polarit y s election (addresses 008Bh, 008 Ch), the bit functions CT and

PLS of the Control/Status Register (address 008Dh), and the state of the PIO channels. See Figure 7 for a description of the Conditional Search log ic. Th e device also responds to the Conditional Search if the PORL bit is se t. The Conditional Search ROM pr ovides an efficient means for the bus ma ster to deter- mine devices on a m ultidrop system that have t o signal an i mportant event, such as a st ate change at a PIO pin caus ed by an external signal. After e ach pass of the conditional search that successfully deter- mined the 64-bit ROM for a specific device on the multidrop bus, that particular device can be individu- ally accessed as if a Match ROM ha d been issued, sinc e all other devices will ha ve dropped out o f the search process and will be waiting for a reset pulse. Skip ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the control functions without provid ing the 64- bit ROM code. If more than one slav e is present on the bus and a Read command is issue d following the Skip ROM command, data coll ision will occur on the bus as multiple slaves transmit simultaneously (open-drain pulldowns will produce a wired-AND result). Resume Command [A5h] In a t ypical application the DS2408 can be accessed several times to complete a control or adjustment function. In a multidrop environment this means th at the 64-bit ROM seq uence of a Mat ch ROM com- mand has to be repeated for every access. To maximize the data throughput in a multidrop environment, the Resume Command function is implemented. This function checks the status of the RC flag and, if it is set, directly transfers control to the control f unctions, similar to a Sk ip ROM command. The onl y way to set t he R C fl ag i s t hrough succ essfully executing t he Mat ch R OM, S earch R OM, C onditional Search ROM, or Ov erdrive-Match R OM com mand. O nce t he R C fl ag i s set , t he d evice can be rep eatedly accessed through the Resume Command function. Accessing another device on the bus will clear the RC flag, preventing two or more devices from simultaneously responding to the Resume Command function. Skip ROM [3Ch] On a sin gle-drop bus th is c ommand ca n sa ve ti me b y a llowing the bus ma ster to access the contr ol functions without provi ding the 64-bit ROM code. Unlike the normal Skip ROM comman d, the Overdrive Skip ROM se ts the DS2408 in the ov erdrive mode (OD = 1). All communication foll owing this command has to occur at overdrive speed until a reset pulse o f minimum 480µs duration res ets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus this command will set all overdrive-supporting de vices into overd rive m ode. To subsequ ently address a speci fic ove rdrive- supporting device, a reset pulse at overdrive speed has to be issued followed by a Match ROM or Search ROM c ommand se quence. This will spe ed up th e time f or the se arch p rocess. If mor e tha n one sla ve supporting overdrive is present on the bus and the Ov erdrive Skip ROM command is followed b y a Read command, data collision will occur on the bus as multip le slaves transm it simul taneously (open -drain pulldowns will produce a wired-AND result). Overdrive Match ROM [69h] The Ove rdrive Ma tch R OM c ommand f ollowed b y a 64- bit ROM se quence tra nsmitted a t ove rdrive speed allows the bus master to address a specific DS2408 on a multidrop bus and to simultaneously set it in overdrive mode. Onl y the DS2408 that ex actly matches the 64-bit ROM se quence will respond to the subsequent control function command. Slaves already in overdrive mode from a previous Overdrive Skip or Match command will remain in ov erdrive mode. All overdrive-capable slaves will re turn to sta ndard speed at the n ext Reset Pulse of minimum 480µs duration. The Overdrive Match ROM command can be used with either single or multiple devices on the bus. 20 of 36

Figure 12-1. ROM FUNCTIONS FLOW CHART From Figure 12 2nd PartTo Control Functions Flow Chart (Figure 8) Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 RC = 1 DS2408 TX CRC Byte DS2408 TX Serial Number (6 Bytes) DS2408 TX Family Code (1 Byte) Bit 0 Match? Y N Bit 1 Match? Y N Bit 63 Match? Y N DS2408 TX Bit 0 DS2408 TX Bit 0 Master TX Bit 0 DS2408 TX Bit 1 DS2408 TX Bit 1 Master TX Bit 1 DS2408 TX Bit 63 DS2408 TX Bit 63 Master TX Bit 63 RC = 1 Bit 0 Match? Y N Bit 1 Match? Y N Bit 63 Match? Y N To Figure 12 2nd Part RC = 0RC = 0 RC = 0RC = 0 YY YY NF0h Search ROM Command? N55h Match ROM Command? N ECh Cond. Search Command? N33h Read ROM Command? To Figure 12 2nd Part From Control Functions Flow Chart (Figure 8) Bus Master TX ROM Function Command DS2408 TX Presence Pulse OD Reset Pulse? N Y OD = 0 Bus Master TX Reset Pulse From Figure 12, 2nd Part Condition Met? Y N DS2408 TX Bit 0 DS2408 TX Bit 0 Master TX Bit 0 DS2408 TX Bit 1 DS2408 TX Bit 1 Master TX Bit 1 DS2408 TX Bit 63 DS2408 TX Bit 63 Master TX Bit 63 RC = 1 Bit 0 Match? Y N Bit 1 Match? Y N Bit 63 Match? Y N 21 of 36

Figure 12-2. ROM FUNCTIONS FLOW CHART From Figure 12 1st Part From Figure 12 1st Part To Figure 12, 1st Part RC = 1 ? N Y RC = 0 ; OD = 1 Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 RC = 1 Bit 0 Match? Y N Bit 1 Match? Y N Bit 63 Match? Y N Y N69h Overdrive Match ROM? RC = 0 ; OD = 1 Master TX Reset ? Y N Master TX Reset ? N Y Y N3Ch Overdrive Skip ROM? Y NA5h Resume Command? RC = 0 Y NCCh Skip ROM Command? To Figure 12 1st Part 22 of 36

definitions of the write and read time slots are illustrated in Figure 14. line at the sampling point determines whether the DS2408 decodes the time slot as 1 or 0. communication, the voltage on th e data line sho uld not ex ceed V ILMAX d uring the entire t W0L wi ndow. Figure 14. READ/WRITE TIMING DIAGRAM

/g100tF tSLOT tRL tMSR tSPDMAX Slave-to-Master A read-data time slot be gins like a write-one time slot. The voltage on the data line must r emain below VTLMIN until the read low time tRL has ex pired. During the t RL window, when respondin g with a 0, the DS2408 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS2408 does not hold the data line low at all, and the voltage starts rising as soon as tRL is over. The sum of t RL + /g100 (rise time) on one side and th e internal timing generator of the DS2408 on the other side define th e master sampling window (t MSRMIN to t MSRMAX) in whic h the master must p erform a r ead from the data line. For most reliable communication, tRL should be as short as permissible and the master should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is e xpired. This guarantees sufficient recovery time tREC for the DS 2408 to g et ready for th e next time slot. Improved Network Behavior In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire driver). 1-Wire networks therefore are susceptible to noise of various origins. Depending on the physical size and topolo gy of the network, reflections from end points and branch points c an add up or cancel each other to some ex tent. Such reflecti ons are visible as g litches or ring ing on the 1-W ire communication line. Noise coupled onto the 1 -Wire line from external sources can also result in s ignal glitching. A g litch during the rising edge of a time slot c an cause a slave device to lose synchronization with the master and, as a consequence, result in a Search ROM command coming to a dead end or cause a device level command to abort. For better performance in network applications, the DS2408 uses a new 1-Wire front end, which makes it less sensitive to noise and also redu ces the magnitude of noise injected by the slave device itself. The 1-Wire front end of the DS2408 differs from traditional slave devices in four characteristics. 1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line impedance than a dig itally switched transi stor, converting the high-frequ ency rin ging known from traditional devices into a smoot her low-bandwidth transition. The sl ew rate control is specifi ed by the parameter tFPD, which has different values for standard and overdrive speed. 2) There is a dditional lowpass filtering in the circuit that detects the falling edge at the beginning of a time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at overdrive speed. 25 of 36

Figure 15. NOISE SUPPRESSION SCHEME reading from the scratchpad, and when reading from the P IO using the C hannel-access Read command. address and ending with the last byte of the register page, address 008Fh. clearing the CRC generator and then shifting in the command code followed by 32 bytes of PIO pin data. CRC values see Application Note 27.

Figure 16. CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL Figure 17. DS2408 AS SLAVE INTERFACE FOR MICROCONTROLLER

8051 Equiv CPU

The data direction (upload/download) is determined by application-specific data protocol.

Figure 18. DS2408 AS SLAVE INTERFACE FOR INTELLIGENT DISPLAY

6 R/ W

5 D/ C

Figure 19. DS2408 AS MICROCONTROLLER PORT EXPANDER

24 I/O LINES OR

3 BYTE-WIDE

Figure 22. DS2408 AS MULTIPURPOSE SENSOR/ACTUATOR

Command-Specific 1-Wire Communication Protocol—Legend SYMBOL DESCRIPTION RST 1-Wire Reset Pulse generated by master. PD 1-Wire Presence Pulse generated by slave. Select Command and data to satisfy the ROM function protocol. RPR Command "Read PIO Registers". CAR Command "Channel-Access Read". CAW Command "Channel-Access Write". WCS Command "Write Conditional Search Register". RAL Command "Reset Activity Latches". TA Target Address TA1, TA2. <data> Transfer of an undetermined amount of data. CRC16\\ Transfer of an inverted CRC16. FF loop Indefinite loop where the master reads FF bytes. AA loop Indefinite loop where the master reads AA bytes. <32 samples>, CRC16\\ loop Indefinite loop where the master reads 32 PIO samples followed by an inverted CRC16. <new state>, <new state\\> Transfer of 2 bytes, where the second byte is the bit-inverse of the first byte. The first byte will be taken as the new PIO state. AAh, <read back> Transfer of 2 bytes, where the first byte is a constant (AAh) and the second byte is the current PIO state. <new state>, <invalid> Transfer of 2 bytes, where the second byte is NOT the bit-inverse of the first byte. Command-Specific 1-Wire Communication Protocol—Col or Codes Master to slave Slave to master Read PIO Registers (Success) RST PD Select RPR TA <data> CRC16\\ FF loop Read PIO Registers (Fail Address) RST PD Select RPR TA FF loop Channel-Access Read (Cannot Fail) RST PD Select CAR <32 samples>, CRC16\\ loop 31 of 36

Channel-Access Write (Success) RST PD Select CAW <new state>, <new state\\> AAh, <read back> Channel-Access Write (Fail New State) Loop RST PD Select CAW <new state>, <invalid> FF loop Write Conditional Search Register (Success) RST PD Select WCS TA <data> FF loop Write Conditional Search Register (Fail Address) RST PD Select WCS TA FF loop Reset Activity Latches (Cannot Fail) RST PD Select RAL AA loop COMMUNICATION EXAMPLES The examples in this section demonstrate the use of ROM and control functions in typical situations. The first two ex amples are related to Figure 17. They sho w how to w rite to the P IO with re adback fo r verification or f or receiving a n imme diate r esponse ( example 1) a nd how to r ead f rom the P IO in a n endless loop (example 2). The third ex ample assumes a network of multip le DS2408s where each of the devices is connected to 8 pushbuttons, as in Figure 21. Example 1 Task: Write to the PIO with readback for verification or for receiving an immediate response. This task is broken into the following steps: 1) Configure RSTZ as STRB output. 2) Verify configuration setting. 3) Write to the PIO and read back the response. With only a single DS2408 connected to the bus master, the communication is as follows: 32 of 36 MASTER MODE DATA (LSB FIRST) COMMENTS Step 1 TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue Skip ROM command TX CCh Issue Write Conditional Search Register command TX 8Dh TA1, target address = 8Dh TX 00h TA2, target address = 008Dh TX 04h Write byte to Control/Status Register

MASTER MODE DATA (LSB FIRST) COMMENTS TX (Reset) Reset pulse RX (Presence) Presence pulse Step 2 TX CCh Issue Skip ROM command TX F0h Issue Read PIO Registers command TX 8Dh TA1, target address = 8Dh TX 00h TA2, target address = 008Dh RX 84h Read Control/Status Register and verify TX (Reset) Reset pulse RX (Presence) Presence pulse Step 3 TX CCh Issue Skip ROM command TX 5Ah Issue Channel-access Write command TX <PIO output byte> Write byte to PIO TX <inverted PIO output byte> Write inverted byte to PIO (— ) (— ) DS2408 updates PIO status if transmission was OK RX AAh Read for verification (AAh = success) (— ) (— ) DS2408 samples PIO pin status RX <PIO pin status byte> Read PIO pin status TX <PIO output byte> Write byte to PIO (next byte) TX <inverted PIO output byte> Write inverted byte to PIO (next byte) RX AAh Read for verification (AAh = success) RX <PIO pin status byte> Read PIO pin status (— ) (— ) Repeat the previous 4 steps with more PIO output data as needed in the application. TX (Reset) Reset pulse RX (Presence) Presence pulse When using this comm unication ex ample to se nd data to a r emote mi crocontroller, as in F igure 17, synchronization be tween the ma ster a nd th e re mote mic rocontroller ca n be ma intained b y t ransmitting data pa ckets that be gin with a le ngth b yte and end with a CRC16. See Application Note 114 , section "UNIVERSAL DATA PACKET" for details. Example 2 Task: Read from the PIO in an endless loop. This task is broken into the following steps: 1) Configure RSTZ as STRB output. 2) Verify configuration setting. 3) Read from the PIO. With only a single DS2408 connected to the bus master, the communication is as follows: MASTER MODE DATA (LSB FIRST) COMMENTS Step 1 TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue Skip ROM command TX CCh Issue Write Conditional Search Register command TX 8Dh TA1, target address = 8Dh TX 00h TA2, target address = 008Dh 33 of 36

MASTER MODE DATA (LSB FIRST) COMMENTS TX 04h Write byte to Control/Status Register TX (Reset) Reset pulse RX (Presence) Presence pulse Step 2 TX CCh Issue Skip ROM command TX F0h Issue Read PIO Registers command TX 8Dh TA1, target address = 8Dh TX 00h TA2, target address = 008Dh RX 84h Read Control/Status Register and verify TX (Reset) Reset pulse RX (Presence) Presence pulse Step 3 TX CCh Issue Skip ROM command TX F5h Issue Channel-access Read command (— ) (— ) DS2408 samples PIO pin status RX <PIO pin status byte> Read PIO pin status (— ) (— ) Repeat the previous 2 steps until the master has received a total of 32 bytes of PIO pin status RX <2 bytes CRC16> Read CRC16 (— ) (— ) PIO pin status and CRC loop can be continued as long as the application requires. TX (Reset) Reset pulse RX (Presence) Presence pulse When using this commu nication ex ample to re ad data f rom a remote mic rocontroller, as in Figure 17, synchronization be tween the r emote mic rocontroller a nd the ma ster c an be ma intained b y t ransmitting data pa ckets that be gin with a le ngth b yte and end with a CRC16. See Application Note 114 , section "UNIVERSAL DATA PACKET" for details. Example 3 Task: Detect the specific DS2408 where the button was pressed and identify the pin to which the pushbutton is connected. This task is broken into the following steps: 1) Configure the conditional search and verify configuration setting. 2) Switch off all channel output transistors. 3) Clear the activity latches. 4) Search until a pushbutton is pressed. 5) Identify device and pushbutton; reset activity latches. The device has to respond to the conditional search if the activity latch of at least one of the 8 channels is set. This requires the following setup data for the conditional search registers: Channel Selection Mask, select all channels /g222 FFh Channel Polarity Selection, select logic 1 for all channels /g222 FFh 34 of 36

Control/Status register, Source is Activity Latch /g222 PLS = 1 Term is OR /g222 CT = 0 RSTZ = inactive (input) /g222 ROS = 0 Clear Power-On Reset Latch /g222 PORL = 0 The resulting setup data for the Control/Status Register is 01h. For each DS2408 in the application, perform the following initialization: MASTER MODE DATA (LSB FIRST) COMMENTS Step 1 TX (Reset) Reset pulse RX (Presence) Presence pulse TX 55h Issue Match ROM command TX <8 byte ROM ID> Send ROM ID of the device to be accessed TX CCh Issue Write Conditional Search Register command TX 8Bh TA1, target address = 8Bh TX 00h TA2, target address = 008Bh TX FFh Write Channel Selection Mask TX FFh Write Channel Polarity Selection TX 01h Write Control/Status Register TX (Reset) Reset pulse RX (Presence) Presence pulse TX A5h Issue Resume command TX F0h Issue Read PIO Registers command TX 8Bh TA1, target address = 8Bh TX 00h TA2, target address = 008Bh RX <FFh, FFh, 81h> Read Registers and verify TX (Reset) Reset pulse RX (Presence) Presence pulse Step 2 TX A5h Issue Resume command TX 5Ah Issue Channel-access Write command TX FFh Write byte to PIO TX 00h Write inverted byte to PIO (— ) (— ) DS2408 switches off all channel output transistors if transmission was OK RX AAh Read for verification (AAh = success) RX FFh Read PIO pin status and verify; FFh = OK TX (Reset) Reset pulse RX (Presence) Presence pulse Step 3 TX A5h Issue Resume command TX C3 Issue Reset Activity Latch command RX AAh Read for verification (AAh = success) TX (Reset) Reset pulse RX (Presence) Presence pulse 35 of 36

After all DS2408s are initialized, perform the search process below as an endless loop: MASTER MODE DATA (LSB FIRST) COMMENTS Step 4 TX (Reset) Reset pulse RX (Presence) Presence pulse TX ECh Issue Conditional Search ROM command RX <2 bits> Read 2 bits; if both bits are 1, no push button has been pressed; in this case return to Step 4. If the bit pattern is 01 or 10 or 00, a push button has been pressed; in this case continue with Step 5. Step 5 TX <1 bits> Identify and select the LS bit of the ROM ID of the DS2408 that has responded to the Conditional Search. RX <2 bits> Read 2 bits; this relates to the next bit of the ROM ID of the participating device(s). TX <1 bits> Identify and select the next bit of the ROM ID of the DS2408 that has responded to the Conditional Search. (— ) (— ) Repeat the previous 2 steps until one device has been identified and accessed. (see Note TX F0h Issue Read PIO Registers command TX 88h TA1, target address = 88h TX 00h TA2, target address = 0000h RX <8 data bytes> Read register page; the data in the Activity Latch State Register tells which button has been pressed. RX <2 bytes CRC16> Read CRC16 and verify correct data transmission. TX (Reset) Reset pulse RX (Presence) Presence pulse TX A5h Issue Resume command TX C3 Issue Reset Activity Latch command RX AAh Read for verification (AAh = success) (— ) (— ) Now, as the device and push button are identified and the Activity Latch is cleared, continue at Step 4. Note 1: For a full description of the Search Algorithm see Application Note 187.