DS22EV5110SQX/NOPB

Texas Instruments

DVI, HDMI Extended Reach Equalizer with Retimer and Output De-Emphasis

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www.ti.com SNLS311E –APRIL 2009–REVISED APRIL 2013 DS22EV5110DVI,HDMIExtendedReachEqualizerwithRetimerandOutputDe-Emphasis Check forSamples: DS22EV5110 1FEATURES DESCRIPTION The DS22EV5110 isa 6.75 Gbps (3 x 2.25 Gbps) 2• OptimizedforHDMI/DVI Source and Repeater extended reach equalizeroptimizedforDVI™ andApplications HDMI ™ cable extensionapplicationswith a high• TMDS Compatible InputswithConfigurable performance re-clockingfeature.It supports 3 Receive EqualizationSupportingData Rates TransitionMinimized DifferentialSignaling(TMDS) up to2.25Gbps datachannelsand a singleclockchanneloverDVI™ v1.0,and HDMI ™ v1.3adataratesup to2.25Gbps• TMDS Compatible Outputs withConfigurable foreach data channel.The device incorporatesaTransmitDe-Emphasis configurablereceiveequalizer,a clock and data• DedicatedCDR on Each Data Channel recovery(CDR) circuitand a de-emphasisdriveronReduces JitterTransfer each data channelover DVI v1.0,and HDMI v1.3a

ResistorAdjustableDifferentialOutput Voltage data ratesup to 2.25 Gbps foreach data channel. The device incorporatesa configurablereceiveforAC Coupled Cat5e and Cat6 Extension equalizerwitha clockand datarecovery(CDR) circuitApplications on each data channel.The clockchannel feeds a• 2 EqualizerSettingsfora Wide Range ofCable high-performancephase locked loop (PLL) thatReaches up to2.25Gbps regeneratesa lowjitteroutputclockfordatarecovery,
TotalOutput Jitterof0.09UI at2.25Gbps enablingthe extended reach of drivingcapability featureforrepeaterapplication.• DVI 1.0and HDMI v1.3aCompatible TMDS Source and Sink Interface The DS22EV5110 equalizesgreaterthan 25 meters
7 mm x 7 mm 48 Pin WQFN Package 28 AWG of HDMI cable,enabling1080p resolution with12 bitdeep colordepth (2.25Gbps), to a low• >8 kV HBM ESD Protection jitterversionof the clockand data signaloutputs,• 0 °C to+70 °C OperatingTemperature reducing both deterministicand random jitter. Obtainingtotaljitteris 0.09 UI or less over the APPLICATIONS supporteddata rates.This extremelylow levelof outputjitterprovidessystem designerswith extra• RepeaterApplications margin and flexibilitywhen working with stringent– HDMI /DVI Extender timingbudgets.Itis idealforthe DVI and HDMI
Source Applications sourceand repeaterapplications. – Video Cards The transmittersupportsconfigurabletransmitde- – Blu-rayDVD Players emphasis so the outputcan be optimizedfordriving additionallengthsofcablesorFR4 traces.– Game Consoles
Sink Applications – High DefinitionDisplays – Projectors Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2009–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

6.75 G DVI/HDMI Sink

7.5m 28 AWG DVI/HDMI Cable DS22EV5110 DS22EV5110 DES/Display Processor

6.75 G DVI/HDMI Source

7.5m 28 AWG DVI/HDMI Cable SNLS311E –APRIL 2009–REVISED APRIL 2013 www.ti.com ApplicationDiagram PIN DESCRIPTIONS Pin Name Pin Number I/O,Type Description High Speed DifferentialI/O C_IN− 1 Invertingand non-invertingTMDS Clockinputstotheequalizer.An on-chip50 Ω terminatingI,CMLC_IN+ 2 resistorconnectsC_IN+ toVDD and C_IN-toVDD . D_IN0− 4 Invertingand non-invertingTMDS Data inputstotheequalizer.An on-chip50 Ω terminatingI,CMLD_IN0+ 5 resistorconnectsD_IN0+ toVDD and D_IN0-toVDD . D_IN1− 8 Invertingand non-invertingTMDS Data inputstotheequalizer.An on-chip50 Ω terminatingI,CMLD_IN1+ 9 resistorconnectsD_IN1+ toVDD and D_IN1-toVDD . D_IN2− 11 Invertingand non-invertingTMDS Data inputstotheequalizer.An on-chip50 Ω terminatingI,CMLD_IN2+ 12 resistorconnectsD_IN2+ toVDD and D_IN2-toVDD . C_OUT- 36 O, CML Invertingand non-invertingTMDS outputsfromtheequalizer.Open collector.C_OUT+ 35 D_OUT0 − 33 O, CML Invertingand non-invertingTMDS outputsfromtheequalizer.Open collector.D_OUT0+ 32 D_OUT1 – 29 O, CML Invertingand non-invertingTMDS outputsfromtheequalizer.Open collector.D_OUT1+ 28 D_OUT2 − 26 O, CML Invertingand non-invertingTMDS outputsfromtheequalizer.Open collector.D_OUT2+ 25 EqualizationControl EQ2 37 EQ2, EQ1 and EQ0 selecttheequalizerboostlevelforEQ channels.InternallypulledLOWEQ1 38 I,LVCMOS as default.RefertoTable1.EQ0 39 De-Emphasis Control DE1 42 I, DE1, DE0 selecttheDE-emphasis levelforoutputdrivers.Internallypulledlowas default. DE0 43 LVCMOS RefertoTable2. Device Control BYPASS 47 Reclockerenablecontrol.Internallypulledlowas default.I, H = Reclockand De-Emphasis functionisbypassed.LVCMOS L = Normal operation. EN 44 EnableOutputDrivers.InternallypulledHIGH as default. I,LVCMOS H = normaloperation(enabled). L = standbymode. SD 45 SignalDetectOutputpin. O, LVCMOS H = signaldetectedon allchannels. L = no signaldetectedon one ormore channels. LOCK 14 Lock IndicatorOutputpin. O, LVCMOS H = PLL islocked. L = PLL isnotlocked.

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DAP = GND DS22EV5110 (Top View) D_IN2+ D_IN2- D_IN1+ D_IN1- D_IN0+ D_IN0- C_IN+ C_IN- D_OUT2+ D_OUT2- D_OUT1+ D_OUT1- D_OUT0+ D_OUT0- C_OUT+ C_OUT- VDD VDD VDD VDD GND GND GND GND VDD VDD GND GND EQ1 EQ0 BYPASS VDD SD EN LFn DE0 DE1 LFp VOD_CRL EQ2 Reserv Reserv LOCK Reserv Reserv Reserv Reserv Reserv DS22EV5110 www.ti.com SNLS311E –APRIL 2009–REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O,Type Description LFp 40 I, Loop filtercapacitorpins. LFn 41 Analog See FunctionalDescription. Power VDD 3,6,7, VDD = 3.3V ±5%. VDD pinsshouldbe tiedtotheVDD planethrougha lowinductancepath.A 10,13, Power 0.1µF bypasscapacitorshouldbe connectedbetween each VDD pintotheGND planes.See 15,46 Power SupplyBypassingforadditionaldetails. GND 22,24, Ground reference.GND shouldbe tiedtoa solidgroundplanethrougha lowimpedance27,30, GND path.31,34 Exposed DAP Ground reference.The exposed pad atthecenterofthepackage must be connectedtotheGNDDAP groundplane. Other Reserv 16,17, 18,19, Reserved.Do notconnect.Leave open.20,21, Connection Diagram TOP VIEW — Not toScale

48 Pin WQFN Package

See Package Number RHS0048A These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS22EV5110

SNLS311E –APRIL 2009–REVISED APRIL 2013 www.ti.com AbsoluteMaximum Ratings(1)(2) SupplyVoltage(VDD ) -0.5Vto4.0V LVCMOS InputVoltage -0.5Vto(VDD + 0.5)V LVCMOS OutputVoltage -0.5Vto(VDD + 0.5)V CML Input/OutputVoltage -0.5Vto(VDD + 0.5)V JunctionTemperature +125°C StorageTemperature -65°C to+150°C Lead Temp. (Soldering,5 sec.) +260°C ESD Rating HBM, 1.5kΩ,100 pF >8 kV ThermalResistanceθJA,No Airflow 33°C/W (1) “AbsoluteMaximum Ratings”aretheratingsbeyond whichthesafetyofthedevicecannotbe verified.They arenotmeant toimplythat thedeviceshouldbe operatedattheselimits. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions(1)(2) Min Typ Max Units SupplyVoltage(VDD toGND) 3.135 3.3 3.465 V SupplyNoiseTolerance(100Hz to50 MHz) (3) 100 mVp-p AmbientTemperature 0 25 +70 °C (1) Typicalparametersaremeasured atVDD = 3.3V,TA = 25 °C. They areforreferencepurposes,and arenotproduction-tested. (2) Parameterisspecifiedby statisticalanalysisand/ordesign. (3) Allowedsupplynoise(mVp-p sinewave) attypicalcondition. ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.Allparametersarespecifiedby test,statisticalanalysis,ordesignunlessotherwisespecified.(1) Symbol Parameter Condition Min Typ Max Unit Power EN = H, DeviceEnabled PRBS15 pattern, 1000 1150 mWfCLK=225 MHz RT= 50Ω toAV CC ,Figure2Power SupplyP Consumption EN = L,StandbyMode PRBS15 pattern, 750 900 mWfCLK=225 MHz RT= 50Ω toAV CC ,Figure2 LVCMOS /LVTTL DC Specifications HighlevelinputVIH 2 VDD Vvoltage Low levelinputVIL GND 0.8 Vvoltage HighleveloutputVOH IOH = -3mA 2.4 Vvoltage Low leveloutputVOL IOL = 3 mA 0.4 Vvoltage VIN = VDD ,EQ2, EQ1, EQ0, DE1, DE0, BYPASS pins(pull 60 μA IIH InputHighCurrent down) VIN = VDD ,EN pin(pullup) -15 μA VIN = 0 V,EQ2, EQ1, EQ0, DE1, DE0, BYPASS pins(pull 15 μA IIL InputLow Current down) VIN = 0 V,EN pin(pullup) -20 μA (1) Typicalparametersaremeasured atVDD = 3.3V,TA = 25 °C. They areforreferencepurposes,and arenotproduction-tested.

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www.ti.com SNLS311E –APRIL 2009–REVISED APRIL 2013 ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.Allparametersarespecifiedby test,statisticalanalysis,ordesignunlessotherwisespecified.(1) Symbol Parameter Condition Min Typ Max Unit SignalDetect DefaultInputsignalleveltoSDH SignalDetectHigh 80 mVp-passertSD pin DefaultInputsignalleveltoSDL SignalDetectLow 20 mVp-pdeassertSD CML Inputs VTX InputVoltage Measured differentiallyatTPA,Swing (Launch 800 1000 1560 mVp-pFigure1(2) Amplitude) VICMDC DC-Coupled requirement InputCommon- Measured atTPB, VDD -0.3 VDD -0.2 VMode Voltage VINmin=800mV, VINmax=1200mV, Figure1 VIN Measured differentiallyatTPB,InputVoltage Figure1 150 1560 mVp-pSensitivity 2.25Gbps, ClockPattern RIN Inputresistance IN+ toVDD and IN-toVDD 40 50 60 Ohms DifferentialoutputRLI 100 MHz — 1125 MHz 10 dBreturnloss CML Outputs Measured DC outputsatTPC, RT = 50Ω when DUT VDD isStandbyOutputVOFF offwithOUT+ and OUT- AV CC -10 AV CC + 10 mVVoltage terminatedby RT= 50Ω to AV CC ,Figure2 Externalresistor= 24 kΩ at VOD_CRL pin.MeasuredDifferentialOutputVO differentiallywithOUT+ and 800 1200 mVp-pvoltageswing OUT- terminatedby RT=50 Ω toAV CC ,Figure2,Figure3 Outputcommon- Measured single-ended,VOCM AV CC -0.35 AV CC -0.2 Vmode Voltage > 1.65Gbps, Figure2 20% to80% ofdifferential outputvoltage,measuredtR,tF Transitiontime 85 pswithin1”fromoutputpins, Figure3 InterPairData Differencein50% crossingChannel-to-tCCSK between channels 2 3 psChannelSkew (all 2.25Gbps, ClockPattern(2) 3 datachannels) Differencein50% crossingInterPairData between channelsofany twotPPSK ChannelsPart- 50 psdevicestoPartSkew 2.25Gbps, ClockPattern Data Channels 2.25Gbps, ClockPattern,tDD 400 psLatency Figure4 ClockChannel 2.25Gbps, ClockPattern,tCD 600 psLatency Figure4 LVCMOS Outputs tSL SD toLOCK time Figure4 4 ms BitRate fCLK ClockFrequency ClockPath(2) 25 250 MHz bR BitRate Data Paths(2) 0.25 2.25 Gbps (2) Parameterisspecifiedby statisticalanalysisand/ordesign. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS22EV5110

SNLS311E –APRIL 2009–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.Allparametersarespecifiedby test,statisticalanalysis,ordesignunlessotherwisespecified.(1) Symbol Parameter Condition Min Typ Max Unit Data Channel Random Jitter RJ Random Jitter See (3)(4)(5)(6) 3 psrms Data Channel CDR JitterGeneration Data Paths,measured atTPCTotalOutputJitterTROJ1 PRBS7, EQ [2:0]= 000 0.03 0.05 UIp-p0.25Gbps Figure1(3)(4)(5) Data Paths,measured atTPCTotalOutputJitterTROJ2 PRBS7, EQ [2:0]= 000 0.08 0.14 UIp-p1.65Gbps Figure1(3)(4)(5) Data Paths,measured atTPCTotalOutputJitterTROJ3 PRBS7, EQ [2:0]= 000 0.09 0.16 UIp-p2.25Gbps Figure1(3)(4)(5) 0.25Gbps datarate 0.25 MHz CDR LoopBWLOOP 1.65Gbps datarate 1.65 MHzBandwidth 2.25Gbps datarate 2.25 MHz Clock Channel PLL JitterGeneration TotalOutputJitter ClockPath,measured atTPCTROJ4 0.03 0.045 UIp-p25 MHz Figure1(3)(4)(5) TotalOutputJitter ClockPath,measured atTPCTROJ5 0.07 0.13 UIp-p165 MHz Figure1(3)(4)(5) TotalOutputJitter ClockPath,measured atTPCTROJ6 0.08 0.135 UIp-p225 MHz Figure1(3)(4)(5) (3) Parameterisspecifiedby statisticalanalysisand/ordesign. (4) Deterministicjitterismeasured atthedifferentialoutputs(TPC ofFigure1),minus thedeterministicjitterbeforethetestchannel(TPA of Figure1).Random jitterisremoved throughtheuse ofaveragingorsimilarmeans. (5) TotalJitterisdefinedas peak-to-peakdeterministicjitterfrom+ 12 timesrandom jitter(ps). (6) Random jittercontributedby theequalizerisdefinedas sq rt(JOUT 2 − JIN 2).JOUT istherandom jitteratequalizeroutputsinps-rms,see TPC ofFigure1;JIN istherandom jitterattheinputoftheequalizerinps-rms,see TPA ofFigure1.

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A B VOH = VDD VOL = VDD - 500mV 0V (DIFF) Vo = 1000 mVp-p Single-ended Waveforms @ A and B Differential Waveform A - B Vocm AV cc 50Ö50Ö Coax Coax Coax Coax Coax Coax Data0 + Data0 - Pattern Generator Clk - Clk + SMA SMA SMA SMA R T SMA SMA SMA SMA TPA TPB TPC Jitter Test Instrument Coax Coax Coax Coax SMA SMA SMA SMA SMA SMA Data1 - Data1 + Data2 - Data2 + AVcc AVcc AVcc AVcc SMA Coax Coax SMA DS22EV5110 Coax Coax Coax Coax VDD VDD VDD VDD TPD R T R T R TR T R TR T R TR T R T R TR T R TR T R TR T HDMI Cable A HDMI Cable B DS22EV5110 www.ti.com SNLS311E –APRIL 2009–REVISED APRIL 2013 Setup and Timing Diagrams Figure1. TestSetup Diagram Figure2. CML Output Swings atA/B (VOD_CRL = 24 kΩ) Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS22EV5110

SD 50% 50% tDD, tCD OUT IN 0V 20% 80% 80% 20% OUT+ OUT- VO = (OUT+) ± (OUT-) tFtR DS22EV5110 SNLS311E –APRIL 2009–REVISED APRIL 2013 www.ti.com Figure3. CML Output TransitionTimes Figure4. CML Latency Delay Time Figure5. SD – LOCK Delay Time

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VOD_CRL LFp LFn GND DAP VDD VDD VDD VDD VDD VDDDS22EV5110 HDMI/DVI Retimer C_IN+ C_IN- D_IN0+ C_OUT+ 3V3 TMDS INPUT PORT - 4 CHANNEL TMDS OUTPUT PORT - 4 CHANNEL Input Equalization Control 10 PF DC Couple 50 Termination PLL EQ DE EN BYPASS Reserv 3V3 All Bypass CAPS 0.1 PF unless noted. 10 PF VDD Output De-E Control D_IN0- D_IN1+ D_IN2+ D_IN1- D_IN2- C_OUT- D_OUT0+ D_OUT0- D_OUT2+ D_OUT1+ D_OUT1- D_OUT2- VDD VDD VDD VDD Other Control Analog Pins Other Outputs CDR AV CC AV CC AV CC AV CC GND DS22EV5110 www.ti.com SNLS311E –APRIL 2009–REVISED APRIL 2013 FunctionalDescription The DS22EV5110 DVI, HDMI Extended Reach EqualizerwithRetimerand Output De-Emphasis consistsof threedata channelsand a clockchannel.Each data channelconsistsof a TMDS compatiblereceiverwitha power efficientequalizer,a dedicatedclock-datarecovery(CDR) unit,and a TMDS compatibletransmitter. Figure6. Block Diagram PHASE-LOCKED-LOCKED LOOP (PLL) The clockchannelhas a high-performancePLL thatcreatesa low jittersamplingclockfortheclockand data recoveryunitsinthedatachannels.An externalloopfilter,composed of2.2nF (+5% tolerance)capacitorand a 3.3kΩ (+5% tolerance)resistorinseries,arerequiredbetween theLFp and theLFn pins. CLOCK-DATA RECOVERY UNIT (CDR) Each TMDS datachannelhas a CDR thatoperatesindependentlyfrom otherTMDS datachannels.Each CDR alignsthe samplingclockedges by digitallyinterpolatingthe clockfrom PLL of the TMDS clockchannel.The deviceisdesignedtoconnecttoDVI/HDMI compatibletransmitterand receiveratany dataratebetween 250 Gbps data. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS22EV5110

SNLS311E –APRIL 2009–REVISED APRIL 2013 www.ti.com INPUT EQUALIZATION The inputdatachannelequalizerssupporteightprogrammable levelsofequalizationboostTable1 by theEQ pins(EQ [2:0]).The range of boostsettingsprovidedenablesthe DS22EV5110 to addressa wide range of transmissionlinepathlossscenarios,enablingsupportfora varietyofdataratesand formats.See Application Informationforrecommended EQ settings. OUTPUT DE-EMPHASIS De-emphasisistheconditioningfunctionforuse incompensatingagainstbackplaneand cabletransmissionloss. The DS22EV5110 providesfourstepsofde-emphasisrangingfrom0,3,6 and 9 dB, user-selectabledependent on thelossprofileofoutputchannels.Table2 shows theDe-emphasis controlwithdefaultVO = 1000 mVp-p, and Figure7 shows a driverde-emphasiswaveform. OUTPUT VO CONTROL Outputdifferentialvoltage(VO) iscontrolledthroughVOD_CRL pintiesan externalresistorto the ground as shown inTable3.Users shouldrestricttheexternalresistorvaluesused tobe 12 kΩ to24 kΩ.+5% toleranceis recommended. Table1.EqualizationControl INPUTS RESULT EQ2 EQ1 EQ0 EqualizationindB (1.125GHz) 0 0 0 0 (default) 0 0 1 12 0 1 0 18 0 1 1 21 1 0 0 24 1 0 1 26 1 1 0 28 1 1 1 30 Table2.De-Emphasis Control INPUTS RESULT VO De-Emphasis levelinmVp-pDE1 DE0 VO De-Emphasis indB(VODE w/VOD_CRL = 24 kΩ 0 0 1000 (default) 0 (default) 0 1 710 -3 1 0 500 -6 1 1 355 -9 Table3.VO Control ExternalResistorValue Applications VO Level(mVp-p)(VOD_CRL pin) 24 kΩ DC Coupled 1000 12 kΩ AC Coupled 1000

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1-bit 1 to N bits 1-bit 1 to N bits 0 dB -3 dB -6 dB -9 dB DS22EV5110 www.ti.com SNLS311E –APRIL 2009–REVISED APRIL 2013 Figure7. Output De-Emphasis DifferentialWaveform (showing allde-emphasis steps) RETIMING AND DE-EMPHASIS BYPASS The retimingand De-emphasis BYPASS pinprovidestheflexibilitytoconfigurethedevicetoan equalizeronly mode. The deviceisinnormaloperation,when holdinga LOW stateon theBYPASS pin.The retimingand De- emphasisfeaturesaredisabled,when a HIGH stateisapplied. DEVICE STATE AND ENABLE CONTROL The DS22EV5110 has an Enable featurewhich providestheabilitytocontroldevicepower consumption.This featurecan be controlledviatheEnablePin(EN Pin).IfEnableisactivated,thedatachannelsand clockchannel are placedinthe ACTIVE stateand alldeviceblocksfunctionas described.The DS22EV5110 can alsobe placedinSTANDBY mode tosave power.Inthismode, theoutputdriversofthedevicearedisabled.The CML outputsareintheHIGH (AVCC) state.AllLVCMOS outputsareintheHiZ state. LOCK DETECT When thePLL oftheDS22EV5110 islocked,and thegeneratedreferencephases aresuccessfullyinterpolated by theCDR, thisstatusisindicatedby a logicHIGH on theLOCK pin.The LOCK pinmay be connectedtothe Enable(EN)pininputtodisablethedatachannelsand clockchannelwhen no datasignalisbeingreceived. SIGNAL DETECT The DS22EV5110 featuresa signaldetectcircuiton allchannels.The statusof the inputsignalscan be determinedby the stateof the SD pin.A logicHIGH indicatesthe presenceof signalsthathave exceeded a specifiedmaximum thresholdvalue(calledSD_ON) on allchannels.A logicLOW means thatthesignalshave fallenbelowa minimum thresholdvalue(calledSD_OFF) on one ormore channels. AUTOMATIC ENABLE FEATURE Duringnormaloperation(i.e.BYPASS pinisLOW), theDS22EV5110 can be configuredtoautomaticallyenter STANDBY mode, ifthe PLL of the DS22EV5110 isnot locked.The STANDBY mode can be implementedby connectingthe LOCK DETECT (LOCK) pin to the external(LVCMOS) Enable (EN) pin.Ifthe LOCK pin is connectedto the EN pin,a logicHIGH on the LOCK pin willenable the device;thus the DS22EV5110 will automaticallyentertheACTIVE state.IfthePLL isunlocked,thentheLOCK pinwillbe assertedLOW, causing theaforementionedblockstobe placedintheSTANDBY state. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS22EV5110

24 k5VOD_CRL 505 DES/Display Processor 7.5m 28 AWG DVI/HDMI Cable DS22EV5110 DS22EV5110 DES/Display Processor 7.5m 28 AWG DVI/HDMI Cable SNLS311E –APRIL 2009–REVISED APRIL 2013 www.ti.com

APPLICATION INFORMATION

The DS22EV5110 isa DVI/HDMI videosignalreconditioningdevice.The deviceconformstoDVI v1.0and HDMI v1.3astandardssupportingup to6.75Gbps totalthroughputTMDS datafor1080p with36 bitdeep colordepth. TYPICAL APPLICATION The DS22EV5110 isused as a DVI/HDMI sourcedevice,sinkdevice,ora repeaterdevice,see Figure8.As the sourcedevice,the outputde-emphasissettingshouldbe configuredbased on the drivingcablelength.When used as the sinkdevice,the levelsof the equalizationboostof the inputdata channelsshouldbe optimized based on thereceivingcablelength.The DS22EV5110 can alsobe used as a repeaterinan externalextender box withtheequalizationand de-emphasislevelsettingsoptimizedtoprovidethemaximum cablereach. Figure8. TypicalApplicationDiagram DC AND AC COUPLED APPLICATIONS The DS22EV5110 isdesignedtosupportTMDS differentialpairswithDC coupledtransmissionlines.Itcontains integratedterminationresistors(50Ω),pulledup toVDD attheinputstage,and open collectoroutputsforDVI / HDMI signaling.Figure9 shows theDC coupledconnectionbetween theHDMI Source (ie.DS22EV5110) and HDMI Sink (ie.DS22EV5110) devices.In the DC coupled application,the externalresistanceof 24 kΩ at VOD_CRL pinisused attheSource toensuretheVO levelof1000 mVp-p. The AC coupledmethod connecting between the Source and the Sink devicesmay be preferredto eliminatethe impactof the ground potential difference,or to use one CAT5/6 cablebetween two chassis.To optimizethe DS22EV5110 performance,the externalresistanceof12 kΩ attheVOD_CRL pinshouldbe used on theSource DS22EV5110, and a pairof50 Ω pull-upresistorsshouldbe placedclosetotheoutputsoftheSource DS22EV5110, inordertoDC biasthe outputdriver.Meanwhile,622Ω pull-downresistorsshouldbe placedat the inputsof the Sink DS22EV5110 device,inordertosettheinputcommon mode toa 3.05V.Note AC coupledconfigurationisnotcomplianttothe HDMI specificationofSourcerequirement(See Figure10). Figure9. DC Coupled Application

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VOD_CRL VDD 505 505 505 DS22EV5110 www.ti.com SNLS311E –APRIL 2009–REVISED APRIL 2013 Figure10. AC Coupled Application CABLE SELECTION AND INTER-PAIR SKEW DVI v1.0and HDMI v1.3aspecifyInter-PairSkew requirementsforthe system.The DS22EV5110 intendsto extendthelongercablereachwithSTP (DVI/HDMI) cable,orUTP (Cat5/Cat5e /Cat6)cable,and itdoes not have a de-skew functiontocompensate any cableInter-PairSkews. Long cablewithInter-PairSkew exceeding theDVI /HDMI standardlimittolerancecouldcause system distortion.Therefore,TIsuggeststheconsideration ofInter-PairSkew budgetduringthesystem design,and recommends Low-Skew Video grade cablesforcable extendingapplications.

28 AWG STP (SHIELDED TWIST PAIRS) DVI /HDMI CABLES RECOMMENDED EQ SETTINGS

Table 4 providesthe recommended EQ controlsettingsforvariousdata ratesand cablelengthsfor28 AWG DVI/HDMI compliantconfigurations.The EQ settingismade viathreeEQ [2:0]pins. Table4.EQ ControlSettingforSTP Cable Format(DataRate) 0 ~ 10m > 10m 1080P 36-bit(2.25Gbps) Setting0x01 Setting0x06 1080P (1.65Gbps) Setting0x01 Setting0x06 1080I(750Mbps) Setting0x06 Setting0x06

24 AWG UTP (LOW SKEW UNSHIELDED TWIST PAIRS) CABLES

The DS22EV5110 can be used toextendthelengthoflow skew gradeUTP cables,such as Cat5e and Cat6 to distancesgreaterthan 30 meters at 1.65 Gbps with< 0.20 UI of jitter.Note thatfornon-standardDVI/HDMI cables,theusermust ensuretheinterpairskew requirementsare met.Table5 shows therecommended EQ controlsettingsforvariousdataratesand cablelengthsforUTP configurations. Table5.EQ ControlSettingforUTP Cable Format(DataRate) 0 ~ 10m > 10m 1080P 36-bit(2.25Gbps) Setting0x01 Setting0x05 1080P (1.65Gbps) Setting0x01 Setting0x05 1080I(750Mbps) Setting0x05 Setting0x05 GeneralRecommendations The DS22EV5110 isa highperformancecircuitcapableofdeliveringexcellentperformance.To achieveoptimal performance,carefulattentionmust be paidtothedetailsassociatedwithhigh-speeddesignas wellas providing a cleanpower supply.RefertotheLVDS Owner ’s Manual formore detailedinformationon high-speeddesign tipsas wellas many otheravailableresourcesaddressingsignalintegritydesignissues. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS22EV5110

+ Clamp Circuitry DS22EV5110 SNLS311E –APRIL 2009–REVISED APRIL 2013 www.ti.com PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS The TMDS differentialinputsand outputsmust have a controlleddifferentialimpedance of100 Ω.Itispreferable torouteTMDS linesexclusivelyon one layeroftheboard,particularlyfortheinputtraces.The use ofviasshould be avoidedifpossible.Ifviasmust be used,theyshouldbe used sparinglyand must be placedsymmetricallyfor each sideofa givendifferentialpair.Route theTMDS signalsaway fromothersignalsand noisesourceson the printedcircuitboard.AlltracesofTMDS differentialinputsand outputsmust be equalinlengthtominimizeintra- pairskew. WQFN FOOTPRINT RECOMMENDATIONS See TI applicationnote:“AN-1187 LeadlessLeadframe Package (LLP)ApplicationReport” (literaturenumber SNOA401 ).foradditionalinformationon WQFN packagesfootprintand solderinginformation. POWER SUPPLY BYPASSING Two approachesare recommended to ensure the DS22EV5110 isprovidedwithan adequate power supply. First,thesupply(VDD) and ground(GND) pinsshouldbe connectedtopower planesroutedon adjacentlayers of the printedcircuitboard.The layerthicknessof the dielectricshouldbe minimizedso the VDD and GND planes createa low inductancesupply with distributedcapacitance.Second, carefulattentionto supply bypassingthroughthe properuse of bypass capacitorsis required.A 0.1 μF bypass capacitorshould be connectedtoeach VDD pinsuch thatthecapacitorisplacedas closeas possibletotheDS22EV5110. Smaller body size capacitorscan help facilitateproper component placement.Additionally,two capacitorswith capacitanceintherange of2.2μF to10 μF shouldbe incorporatedinthepower supplybypassingdesignas well.These capacitorscan be eithertantalumor an ultra-lowESR ceramicand shouldbe placedas closeas possibletotheDS22EV5110. EQUIVALENT I/OSTRUCTURES Figure11 shows theDS22EV5110 CML outputstructureand ESD protectioncircuitry. Figure12 shows theDS22EV5110 CML inputstructureand ESD protectioncircuitry. Figure11. EquivalentOutput Structure Figure12. EquivalentInputStructure

14 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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www.ti.com SNLS311E –APRIL 2009–REVISED APRIL 2013 TypicalPerformance Characteristicsas a Repeater Figure13. SimplifiedTestSetup as a SingleRepeater Figure14.System Source Eye Diagram atTPA Figure15.Device Sink Eye Diagram atTPB (2.25Gbps) (2.25Gbps, Cable A = 25m 28 AWG HDMI) Figure16.Device Source Eye Diagram atTPC Figure17.Device Source Eye Diagram atTPC (2.25Gbps, Cable A = 25m 28 AWG HDMI, (2.25Gbps, Cable A = 25m 28 AWG HDMI, EQ = 0x05,BYPASS = 0,DE = 0dB) EQ = 0x05,BYPASS = 0,DE = -3dB) Figure18.System Sink Eye Diagram atTPD Figure19.System Source Eye Diagram atTPA (2.25Gbps, Cable A = 25m 28 AWG HDMI, Cable B = 7.5m (1.65Gbps) 28AWG HDMI, EQ = 0x05,BYPASS = 0,DE = -3dB) Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS22EV5110

SNLS311E –APRIL 2009–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristicsas a Repeater(continued) Figure20.Device Sink Eye Diagram atTPB Figure21.Device Source Eye Diagram atTPC (1.65Gbps, Cable A = 35m 28 AWG HDMI) (1.65Gbps, Cable A = 35m 28 AWG HDMI, EQ = 0x05,BYPASS = 0,DE = 0dB) Figure22.Device Source Eye Diagram atTPC Figure23.System Sink Eye Diagram atTPD (1.65Gbps, Cable A = 35m 28 AWG HDMI, (1.65Gbps, Cable A = 35m 28 AWG HDMI, Cable B = 10m 28AWG HDMI, EQ = 0x05,BYPASS = 0,DE = -6dB)EQ = 0x05,BYPASS = 0,DE = -6dB)

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www.ti.com SNLS311E –APRIL 2009–REVISED APRIL 2013

REVISION HISTORY

www.ti.com 5-Nov-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS22EV5110SQ/NOPB NRND WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 22EV5110 DS22EV5110SQE/NOPB NRND WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 22EV5110 DS22EV5110SQX/NOPB NRND WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 22EV5110 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 5-Nov-2014 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS22EV5110SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS22EV5110SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS22EV5110SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 2

www.ti.com SQA48A (Rev B)

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