DS22EV5110 NSC | Alldatasheet
Document overview
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Technical content
Features
■ Optimized for HDMI/DVI source and repeater applications ■ TMDS compatible inputs with configurable receive equalization supporting data rates up to 2.25 Gbps ■ TMDS compatible outputs with configurable transmit de- emphasis ■ Dedicated CDR on each data channel reduces jitter transfer ■ Resistor adjustable differential output voltage for AC coupled Cat5e and Cat6 extension applications ■ 2 equalizer settings for a wide range of cable reaches up to 2.25 Gbps ■ Total Output Jitter of 0.09 UI at 2.25 Gbps ■ DVI 1.0 and HDMI v1.3a compatible TMDS source and sink interface ■ 7 mm x 7 mm 48 pin LLP package ■ >8 kV HBM ESD protection ■ 0 °C to +70 °C operating temperature
Applications
■ Repeater Applications — HDMI / DVI Extender ■ Source Applications — Video Cards — Blu-ray DVD Players — Game Consoles ■ Sink Applications — High Definition Displays — Projectors Application Diagram 30094953 © 2009 National Semiconductor Corporation 300949 www.national.com DS22EV5110 DVI, HDMI Extended Reach Equalizer with Retimer and Output De-Emphasis
Pin Name Pin Number I/O, Type Description High Speed Differential I/O C_IN− C_IN+ I, CML Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50 Ω terminating resistor connects C_IN+ to VDD and C_IN- to VDD. D_IN0− D_IN0+ I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating resistor connects D_IN0+ to VDD and D_IN0- to VDD. D_IN1− D_IN1+ I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating resistor connects D_IN1+ to VDD and D_IN1- to VDD. D_IN2− D_IN2+ I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating resistor connects D_IN2+ to VDD and D_IN2- to VDD. C_OUT- C_OUT+ O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector. D_OUT0− D_OUT0+ O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector. D_OUT1– D_OUT1+ O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector. D_OUT2− D_OUT2+ O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector. Equalization Control EQ2 EQ1 EQ0 I, LVCMOS EQ2, EQ1 and EQ0 select the equalizer boost level for EQ channels. Internally pulled LOW as default. See Table 1. De-Emphasis Control DE1 DE0 LVCMOS DE1, DE0 select the DE-emphasis level for output drivers. Internally pulled low as default. Refer to Table 2. Device Control BYPASS 47 I, LVCMOS Reclocker enable control. Internally pulled low as default. H = Reclock and De-Emphasis function is bypassed. L = Normal operation. EN 44 I, LVCMOS Enable Output Drivers. Internally pulled HIGH as default. H = normal operation (enabled). L = standby mode. SD 45 O, LVCMOS Signal Detect Output pin. H = signal detected on all channels. L = no signal detected on one or more channels. LOCK 14 O, LVCMOS Lock Indicator Output pin. H = PLL is locked. L = PLL is not locked. VOD_CRL 48 I, Analog VOD control pin. Refer to Table 3. See Functional Description. External resistance = 24 kΩ to GND, Output DC Coupled Application. External resistance = 12 kΩ to GND, Output AC Coupled Application. LFp LFn Analog Loop filter capacitor pins. See Functional Description. Power VDD 3, 6, 7, 10, 13, 15, 46 Power VDD = 3.3 V ±5%. VDD pins should be tied to the VDD plane through a low inductance path. A 0.1 µF bypass capacitor should be connected between each VDD pin to the GND planes. See Power Supply Bypassing for additional details. GND 22, 24, 27, 30, 31, 34 GND Ground reference. GND should be tied to a solid ground plane through a low impedance path. Exposed DAP DAP GND Ground reference. The exposed pad at the center of the package must be connected to the ground plane. www.national.com 2 DS22EV5110
Pin Name Pin Number I/O, Type Description Other Reserv 16, 17, 18, 19, 20,21, Reserved. Do not connect. Leave open. Note: I = Input, O = Output, IO =Input/Output, Connection Diagram 30094952 TOP VIEW — Not to Scale
Ordering Information
DS22EV5110SQE 48 Lead LLP 250 SQA48A DS22EV5110SQ 48 Lead LLP 1000 SQA48A DS22EV5110SQX 48 Lead LLP 2,500 SQA48A 3 www.national.com DS22EV5110
Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) -0.5V to 4.0 V LVCMOS Input Voltage -0.5V to (VDD+ 0.5) V LVCMOS Output Voltage -0.5V to (VDD+ 0.5) V CML Input/Output Voltage -0.5V to (VDD+ 0.5) V Junction Temperature +125°C Storage Temperature -65°C to +150°C Lead Temp. (Soldering, 5 sec.) +260°C ESD Rating HBM, 1.5 k Ω, 100 pF >8 kV Thermal Resistance θJA, No Airflow 33°C/W Recommended Operating Conditions (Notes 3, 4) Min Typ Max Units Supply Voltage (V DD to GND) 3.135 3.3 3.465 V Supply Noise Tolerance (100 Hz to 50 MHz) 100 mVp-p Ambient Temperature 0 25 +70 °C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. All parameters are guaranteed by test, statistical analysis, or design unless otherwise specified. (Note 3) Symbol Parameter Condition Min Typ Max Unit Power P Power Supply Consumption EN = H, Device Enabled PRBS15 pattern, fCLK=225 MHz RT= 50Ω to AVCC, Figure 2 1000 1150 mW EN = L, Standby Mode PRBS15 pattern, fCLK=225 MHz RT= 50Ω to AVCC, Figure 2 750 900 mW LVCMOS / LVTTL DC Specifications VIH High level input voltage 2 VDD V VIL Low level input voltage GND 0.8 V VOH High level output voltage IOH = -3 mA 2.4 V VOL Low level output voltage IOL = 3 mA 0.4 V IIH Input HighCurrent VIN = VDD, EQ2, EQ1, EQ0, DE1, DE0, BYPASS pins (pull down) 60 mA VIN = VDD, EN pin (pull up) -15 mA IIL Input Low Current VIN = 0 V, EQ2, EQ1, EQ0, DE1, DE0, BYPASS pins (pull down) 15 μA VIN = 0 V, EN pin (pull up) -20 μA Signal Detect SDH Signal Detect High Default Input signal level to assert SD pin 80 mVp-p SDL Signal Detect Low Default Input signal level to deassert SD 20 mVp-p www.national.com 4 DS22EV5110
Symbol Parameter Condition Min Typ Max Unit CML Inputs VTX Input Voltage Swing (Launch Amplitude) Measured differentially at TPA, Figure 1, note 4 800 1000 1560 mVp-p VICMDC Input Common- Mode Voltage DC-Coupled requirement Measured at TPB, VINmin=800mV, VINmax=1200mV, Figure 1 VDD-0.3 VDD-0.2 V VIN Input Voltage Sensitivity Measured differentially at TPB, Figure 1
2.25 Gbps, Clock Pattern
RIN Input resistance IN+ to VDD and IN- to VDD 40 50 60 Ohms RLI Differential output return loss 100 MHz — 1125 MHz 10 dB CML Outputs VOFF Standby Output Voltage Measured DC outputs at TPC, RT = 50Ω when DUT VDD is off with OUT+ and OUT- terminated by RT= 50Ω to AVCC, Figure 2 AVCC- 10 AVCC+ 10 mV VO Differential Output voltage swing External resistor = 24 kΩ at VOD_CRL pin.Measured differentially with OUT+ and OUT- terminated by RT=50Ω to AVCC,Figures 2, 800 1200 mVp-p VOCM Output common- mode Voltage Measured single-ended, > 1.65 Gbps, Figure 2 AVCC- 0.35 AVCC- 0.2 V tR, tF Transition time 20% to 80% of differential output voltage, measured within 1” from output pins, Figure 3 85 ps tCCSK Inter Pair Data Channel-to- Channel Skew (all 3 data channels) Difference in 50% crossing between channels (Note 4) 2 3 ps tPPSK Inter Pair Data Channels Part- toPart Skew Difference in 50% crossing between channels of any two devices
2.25 Gbps, Clock Pattern,
tSL SD to LOCK time Figure 4 4 ms Bit Rate fCLK Clock Frequency Clock Path (Note 4) 25 250 MHz bR Bit Rate Data Paths (Note 4) 0.25 2.25 Gbps 5 www.national.com DS22EV5110
Symbol Parameter Condition Min Typ Max Unit Data Channel Random Jitter RJ Random Jitter (Notes 4, 5, 6) 3 psrms Data Channel CDR Jitter Generation TROJ1 Total Output Jitter
0.25 Gbps
Data Paths, measured at TPC PRBS7, EQ [2:0] = 000 Figure 1, (Notes 4, 5, 6) 0.03 0.05 UIp-p TROJ2 Total Output Jitter
1.65 Gbps
Data Paths, measured at TPC PRBS7, EQ [2:0] = 000 Figure 1, (Notes 4, 5, 6) 0.08 0.14 UIp-p TROJ3 Total Output Jitter
2.25 Gbps
Data Paths, measured at TPC PRBS7, EQ [2:0] = 000 Figure 1, (Notes 4, 5, 6) 0.09 0.16 UIp-p BWLOOP CDR Loop Bandwidth 0.25 Gbps data rate 0.25 MHz 1.65 Gbps data rate 1.65 MHz 2.25 Gbps data rate 2.25 MHz Clock Channel PLL Jitter Generation TROJ4 Total Output Jitter
25 MHz
Clock Path, measured at TPC Figure 1 (Notes 4, 5, 6) 0.03 0.045 UIp-p TROJ5 Total Output Jitter
165 MHz
Clock Path, measured at TPC Figure 1 (Notes 4, 5, 6) 0.07 0.13 UIp-p TROJ6 Total Output Jitter
225 MHz
Clock Path, measured at TPC Figure 1 (Notes 4, 5, 6) 0.08 0.135 UIp-p Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. Note 2: Allowed supply noise (mVp-p sine wave) at typical condition. Note 3: Typical parameters are measured at VDD = 3.3 V, TA = 25 °C. They are for reference purposes, and are not production-tested. Note 4: Parameter is guaranteed by statistical analysis and/or design. Note 5: Deterministic jitter is measured at the differential outputs (TPC of Figure 1), minus the deterministic jitter before the test channel (TPA of Figure 1). Random jitter is removed through the use of averaging or similar means. Note 6: Total Jitter is defined as peak-to-peak deterministic jitter from + 12 times random jitter (ps). Note 7: Random jitter contributed by the equalizer is defined as sq rt (JOUT2 − JIN2). JOUT is the random jitter at equalizer outputs in ps-rms, see TPC of Figure 1; JIN is the random jitter at the input of the equalizer in ps-rms, see TPA of Figure 1. www.national.com 6 DS22EV5110
FIGURE 6. Block Diagram bandwidth of the CDR is approximately baud_rate/1000, i.e. 2.25 MHz for 2.25 Gbps data. driver de-emphasis waveform. used to be 12 kΩ to 24 kΩ. +5% tolerance is recommended.
TABLE 1. Equalization Control TABLE 2. De-Emphasis Control TABLE 3. VO Control FIGURE 7. Output De-Emphasis Differential Waveform (showing all de-emphasis steps)
RETIMING AND DE-EMPHASIS BYPASS The retiming and De-emphasis BYPASS pin provides the flexibility to configure the device to an equalizer only mode. The device is in normal operation, when holding a LOW state on the BYPASS pin. The retiming and De-emphasis features are disabled, when a HIGH state is applied. DEVICE STATE AND ENABLE CONTROL The DS22EV5110 has an Enable feature which provides the ability to control device power consumption. This feature can be controlled via the Enable Pin (EN Pin). If Enable is acti- vated, the data channels and clock channel are placed in the ACTIVE state and all device blocks function as described. The DS22EV5110 can also be placed in STANDBY mode to save power. In this mode, the output drivers of the device are disabled. The CML outputs are in the HIGH (AVCC) state. All LVCMOS outputs are in the HiZ state. LOCK DETECT When the PLL of the DS22EV5110 is locked, and the gener- ated reference phases are successfully interpolated by the CDR, this status is indicated by a logic HIGH on the LOCK pin. The LOCK pin may be connected to the Enable (EN) pin input to disable the data channels and clock channel when no data signal is being received. SIGNAL DETECT The DS22EV5110 features a signal detect circuit on all chan- nels. The status of the input signals can be determined by the state of the SD pin. A logic HIGH indicates the presence of signals that have exceeded a specified maximum threshold value (called SD_ON) on all channels. A logic LOW means that the signals have fallen below a minimum threshold value (called SD_OFF) on one or more channels. AUTOMATIC ENABLE FEATURE During normal operation (i.e. BYPASS pin is LOW), the DS22EV5110 can be configured to automatically enter STANDBY mode, if the PLL of the DS22EV5110 is not locked. The STANDBY mode can be implemented by connecting the LOCK DETECT (LOCK) pin to the external (LVCMOS) En- able (EN) pin. If the LOCK pin is connected to the EN pin, a logic HIGH on the LOCK pin will enable the device; thus the DS22EV5110 will automatically enter the ACTIVE state. If the PLL is unlocked, then the LOCK pin will be asserted LOW, causing the aforementioned blocks to be placed in the STANDBY state. 11 www.national.com DS22EV5110
FIGURE 10. AC Coupled Application grade cables for cable extending applications.
28 AWG STP (SHIELDED TWIST PAIRS) DVI / HDMI
TABLE 4. EQ Control Setting for STP Cable
24 AWG UTP (LOW SKEW UNSHIELDED TWIST PAIRS)
greater than 30 meters at 1.65 Gbps with < 0.20 UI of jitter. rates and cable lengths for UTP configurations. TABLE 5. EQ Control Setting for UTP Cable
Physical Dimensions inches (millimeters) unless otherwise noted 7mm x 7mm 48-pin LLP Package Order Number DS22EV5110SQ 17 www.national.com DS22EV5110
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