DS2229 MAXIM | Alldatasheet
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Technical content
FEATURES
/elevenoclock Organized as a high density 512k x 16 bit StikTM /elevenoclock Fast access time of 85 ns /elevenoclock Unlimited write cycles /elevenoclock Employs popular JEDEC standard 80-position SIMM connector /elevenoclock Full ±10% operating range /elevenoclock Read cycle time equals write cycle time /elevenoclock Ultra-low standby current < 10 µA /elevenoclock Suitable for battery-backed applications PIN ASSIGNMENT
DESCRIPTION
The DS2229 is an 8,388,608-bit low-power fully static Random Access Memory organized as a 524,888 word by 16 bits using CMOS technology. The device employs the popular JEDEC standard 80-pin SIMM connection scheme with no additional circuitry required. The device operates from a single power supply with a voltage input of 4.5 to 5.5 volts. The Chip Enable inputs ( CE0 , CE1 , CE2 , CE3 ) are used for device selection and can be used in order to achieve the minimum standby current mode which facilitates battery backup. The device provides a fast access time of 85 ns. The DS2229 maintains TTL levels over input voltage range 4.5V to 5.5V. The DS2229 is JEDEC pin compatible (see Figure 1) with flash EEPROM memory SIMM boards of similar density. DS2229 Word-Wide 8 Meg SRAM Stik www.dalsemi.com 80 1 SRAM SRAM SRAM SRAM 80-PIN SIP STIK
PIN # PIN NAME PIN # PIN NAME PIN # PIN NAME
1 GND 32 NC 63 DQ 7
4 OE 35 NC 66 DQ 4
5 WEH 36 A 16 67 DQ 3
6 WEL 37 A 15 68 DQ 2
10 NC 41 A 11 72 V CC
11 NC 42 A 10 73 NC
12 NC 43 A 9 74 GND
13 NC 44 A 8 75 NC
14 NC 45 A 7 76 GND
15 NC 46 A 6 77 GND
16 NC 47 A 5 78 NC
17 NC 48 A 4 79 NC
18 NC 49 A 3 80 GND
19 NC 50 A 2
20 NC 51 A 1
21 CE3 52 A 0 PIN NAME DESCRIPTION
22 CE2 53 GND A 0 - A16 Address Input
23 CE1 54 GND WEL Write Enable Input Low
24 CE0 55 DQ 15 WEH Write Enable Input High
25 GND 56 DQ 14 OE Output Enable Input
26 NC 57 DQ 13 NC No Connect
27 NC 58 DQ 12 CE0 - CE3 Chip Enable Input
28 NC 59 DQ 11 CS Chip Select
29 NC 60 DQ 10 DQ0 - DQ15 Data Input/Output
30 NC 61 DQ 9 VCC +5 Volts
31 NC 62 DQ 8 GND Ground
DS2229 STATIC RAM MODULE FUNCTION DIAGRAM Figure 2
ABSOLUTE MAXIMUM RATINGS* Power Supply Voltage -0.3V to +7.0V Input, Input/Output Voltage -0.3 to V CC +0.3V Operating Temperature 0°C to 70°C Storage Temperature -55°C to +125°C * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. OPERATION MODE MODE CE0 - CE3 CS OE WE A0 - A16 DQ - DQ15 POWER READ L H L H STABLE DATA OUT I CC0 WRITE L H X L STABLE DATA IN I CC0 DESELECT L H H H X HIGH-Z I CC0 STANDBY H X X X X HIGH-Z I CCS1, ICCS2 STANDBY X L X X X HIGH-Z I CCS1, ICCS2 CAPACITANCE (tA=25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C IN 64 pF Input/Output Capacitance C I/O 80 pF RECOMMENDED DC OPERATING CONDITIONS (tA= 0°C to 70°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Power Supply Voltage V CC 4.5 5.0 5.5 V Input High Voltage V IH 2.0 V CC+0.3 V Input Low Voltage V IL -0.3 0.8 V DC CHARACTERISTICS (tA= 0°C to 70°C; VCC= 5V ± 10%) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES Input Leakage Current I IL 0V ≤ VIN ≤ VCC 8 µA I/O Leakage Current I LO CE0 - CE3 = VIH, 0V ≤ VI/O ≤ VCC 8 µA Output High Current I OH VOH = 2.4V -1.0 mA Output Low Current I OL VOL = 0.4V 2.1 mA Standby Current I CCS1 CE0 - CE3 =2.0V tA=25°C 8m A Standby Current I CCS2 CE0 - CE3 ≥ VCC -0.3V tA=25°C 10 µA Operating Current I CCO CE0 - CE3 = 0.8V; Cycle=100 ns tA=25°C 100 mA 9
LOW VCC DATA RETENTION CHARACTERISTICS (tA= 0°C to 70°C) PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONTIDION VCC for Data Retention V DR 2.0 - - V CE0 - CE3 ≥ VCC -0.2V, CS ≥ VCC -0.2V or 0V ≤ CS ≤ 0.2V VIN ≥ 0V Data Retention Current I CCDR -18 µAV CC = 3.0V, VIN ≥ 0V CE0 - CE3 ≥ VCC -0.2V, CS ≥ VCC -0.2V or 0V ≤ CS ≤ 0.2V tA =25°C Chip Deselect to Data Retention Time tCDR 0-- n s Operation Recovery Time t R 5--m s See Retention Waveform LOW VCC DATA RETENTION TIMING WAVEFORM (1) (CE0 -CE3 Controlled) Figure 3 SEE NOTE 5 LOW VCC DATA RETENTION TIMING WAVEFORM (2) (CS Controlled) Figure 4 SEE NOTE 5
AC ELECTRICAL CHARACTERISTICS READ CYCLE (0°C to 70°C; VCC = 5V + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Read Cycle Time t RC 85 ns Access Time t ACC 85 ns OE to Output Valid tOE 45 ns CE0 - CE3 to Output Valid tCO 85 ns OE or CE0 - CE3 to Output In Low-Z tCOE 10 ns 8 Output High-Z from Deselection t OD 03 0 n s 8 Output Hold from Address Change t OH 10 ns AC ELECTRICAL CHARACTERISTICS WRITE CYCLE (0°C to 70°C; VCC = 5V + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Write Cycle Time t WC 85 ns Write Pulse Width t WP 65 ns 1 Address Setup Time t AW 0n s Write Recovery Time t WR 10 ns 4 Output High-Z from WE tODW 03 0 n s 8 Output Active from WE tOEW 5n s 8 Data Setup Time t DS 35 ns 3 Data Hold Time from WE tDH 0n s 3
SEE NOTES 1, 3, 4, 6, 7, AND 9
NOTES: 1. A write occurs during the overlap of a low CE0 - CE3 , a high CS, and a low WE . A write begins at the latest transition among CE0 - CE3 going low, CS going high, and WE going low. A write ends at the earliest transition among CE0 - CE3 going high, CS going low and WE going high. t WP is measured from the beginning of write to the end of write. 2. WE is high for a read cycle. 3. tDS ends and tDH begins at the earliest transaction among CE0 - CE3 going high. 4. tWR is measured from the earliest of CE0 - CE3 or WE going high or CS going low to the end of write cycle. 5. CS controls address buffer, WE buffer, CE0 - CE3 buffer, OE buffer and D IN buffer. If CS controls data retention mode, VIN levels (address, WE , OE , CE0 - CE3 , I/O) can be in the high impedance state. If CE0 - CE3 controls data retention mode, CS must be CS ≥ VCC - 0.2V or 0V < CS < 0.2V. The other input levels (address, WE , OE , I/O) can be in the high impedance state. 6. If CE0 - CE3 goes low simultaneously with WE going low or after WE going low, the outputs remain in a high impedance state. 7. If CE0 - CE3 is low and CS is high during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 8. This parameter is sampled and not 100% tested. 9. Only one CE active during any read or write cycle.
A 4.645 4.655 B 4.379 4.389 C 0.729 0.739 D 0.395 0.405 E 0.245 0.255 F 0.050 BSC G 0.075 0.085 H 0.245 0.255 I 1.950 BSC J 0.120 0.130 K 2.320 2.330 L 2.445 2.455 M 0.057 0.067 N 0.130 O 0.130 P 0.054