DS21352DK MAXIM | Alldatasheet
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1 of 21 REV: 110106 GENERAL DESCRIPTION The DS21352 design kit is an easy-to-use evaluation board for the DS21352 T1 single-chip transceiver (SCT). The DS21352DK is intended to be used as a daughter card with either the DK2000 or the DK101 motherboards. The DS21352DK comes complete with an SCT, transformers, termination resistors, configuration switches, line-protection circuitry, network connectors, and motherboard connectors. The DK101/DK2000 motherboard and Dallas’ ChipView software give point-and-click access to configuration and status re gisters from a Windows ®- based PC. On-board LEDs indicate receive loss-of- signal and interrupt status, as well as multiple clock and signal routing configurations. Each DS21352DK is shipped with a free DK101 motherboard. For complex applications, the DK2000 high-performance demo kit motherboard can be purchased separately. Windows is a registered trademark of Microsoft Corp.
ORDERING INFORMATION
DS21352DK DS21352 Design Kit Daughter Card (with included DK101 motherboard)
FEATURES
Demonstrates Key Functions of DS21352 T1 SCT Transceiver Includes DS21352 SCT, Transformers, Bantum, BNC and RJ48 Network Connectors, and Termination Passives Compatible with DK101 and DK2000 Demo Kit Motherboards DK101/DK2000 and ChipView Software Provide Point-and-Click Access to the DS21352 Register Set Software-Controlled (Register Mapped) Configuration Switches to Facilitate Clock and Signal Routing All Equipment-Side Framer Pins are Easily Accessible for External Data Source/Sink LEDs for Loss-Of-Signal and Interrupt Status as well as Multiple Clock and Signal Routing Configurations Easy-to-Read Silk Screen Labels Identify the Signals Associated with all Connectors, Jumpers and LEDs Network Interface Protection for Overvoltage and Overcurrent Events DEMO KIT CONTENTS DS21352DK Design Kit Daughter Card DK101 Low-Cost Motherboard CD ROM ChipView Software DS21352DK Data Sheet DK101 Data Sheet DS21352 Data Sheet DS21352 Errata Sheet DS21352DK T1 Single-Chip Transceiver Design Kit Daughter Card www.maxim-ic.com
DESIGNATION QTY DESCRIPTION SUPPLIER PART C1–C5, C8–C12, C15–C19, C21, C22, C29–C34 23 0.1μF 10%, 16V ceramic capacitors (0603) Digi-Key 311-1088-1-ND C7, C36 2 1μF 10%, 16V ceramic capacitors (1206) Digi-Key PCC1882CT-ND C13, C14 2 0.1μF 10%, 16V ceramic capacitors (0805) Digi-Key 311-1142-1-ND C23 1 0.1μF 10%, 25V ceramic capacitor (1206) Digi-Key PCC1883CT-ND C24–C27 4 0.22μF, 50V ceramic capacitors Digi-Key UNK C35 1 10μF 20%, 16V tantalum capacitor (B case) Digi-Key PCS3106CT-ND DS1, DS4–DS18 16 LED, gree n, SMD Digi-Key P501CT-ND DS2, DS3 2 LED, red, SMD Digi-Key P500CT-ND F1–F6 6 250V, 1.25A fuse, SMT Teccor Electronics F1250T J1, J2 2 Male 0.1, SMD, 50-pin, dual -row vertical Samtec TSM-125-01-T-DV J3, J4 2 Bantam connectors SWK RTT34B02 J5, J6 2 Connector BNC RA 5-pin Kruvand UCBJR220 J7–J9 3 Socket, SMD, 50-pin, dual-row vertical Samtec TFM-125-02-S-D- LC JT10 1 Connector, 10-pin, dual-ro w vertical Digi-Key S2012-05-ND L1 1 Choke, dual 4-line 24μH, 8-pin SO Pulse Engineering PE-65857 R1, R14, R21 3 51.1Ω 1%, 1/8W resistors (1206) Digi-Key P51.1FCT-ND R2, R3, R58, R59 4 0Ω 5%, 1/8W resistors (1206) Digi-Key P0.0ETR-ND R4, R5, R60 3 51.1Ω 1%, 1/10W resistors (0805) Digi-Key P51.1CCT-ND R6, R9, R10, R13, R15–R19, R22, R23, R25–R29, R32, R37, R38, R44, R47–R49, R61 24 10kΩ 1%, 1/10W resistors (0805) Digi-Key P10.0KCCT-ND R7, R8, R11, R12, R30, R31, R35, R36, R39–R43, R45, R50–R53 18 330Ω 0.1%, 1/10W MF resistors (0805) Digi-Key P330ZCT-ND R24 1 1.0kΩ 1%, 1/10W resistor (0805) Digi-Key P1.00KCCT-ND R33, R34 2 Not populated — Not populated R46 1 4.7kΩ 1%, 1/8W resistor (0805) Digi-Key 9C08052A4701FK HFT R54, R55 2 61.9Ω 1%, 1/8W resistors (1206) Digi-Key P61.9FCT-ND R56, R57 2 49.9Ω 1%, 1/8W resistors (1206) Digi-Key P49.9FCT-ND RJ1 1 RJ48 connector Molex 43223 SW1 1 Switch DPDT slide 6-pin TH Avnet SSA22 T1 1 XFMR 16-pin SMT Pulse Engineering TX1099 U1–U4, U6 5 BBUS switch 10-bit CMOS, 150-mil, 24-pin SO IDT IDTQS3R861Q U5 1 144-pin macrocell CPLD Avnet XC95144XL- 10TQ100C U7–U10 4 Quad bus switch, 150-mil, 16-pin SO IDT IDTQS3125Q U11 1 T1/E1/J1 XCVR 100-pin QFP, 0°C to +70°C Dallas Semiconductor DS2156L Z1, Z6–Z8 4 160V, 500A Sidactor Teccor Electronics P1800SCMC Z2, Z3 2 58V, 500A Sidactor Teccor Electronics P0640SCMC Z4, Z5 2 6V, 50A Sidactor Teccor Electronics P0080SAMC Z9, Z10 2 25V, 500A Sidactor Teccor Electronics P0300SCMC
This design kit relies upon several supporting files, which can be downloaded from our website at www.maxim-ic.com/DS21352DK. See the DS21352DK QuickView data sheet for these files. Hardware Configuration Using the DK101 processor board:
- Connect the daughter card to the DK101 processor board.
- Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. (The external 5V connector and the TIM 5V supply headers are unused.)
- All processor board DIP switch settings should be in the ON position with exception for the flash programming switch, which should be OFF.
- From the Programs menu, launch the host application named ChipView.exe. Run the ChipView application. If the default installation options were used, click the Start button on the Windows toolbar and select Programs→ChipView→ChipView. Using the DK2000 processor board:
- Connect the daughter card to the DK2000 processor board.
- Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply can be connected to connector J2.
- From the Programs menu, launch the host application named ChipView.exe. Run the ChipView application. If the default installation options were used, click the Start button on the Windows toolbar and select Programs→ChipView→ChipView. General:
- Upon power-up the RLOS LED is lit, as well as the MCLK-2.048MHz and TCLK-2.048MHz LEDs. Quick Setup (Demo Mode)
- The PC loads the program, offering a choice among Demo Mode, Register View, and Terminal Mode. Select Demo Mode.
- The program requests a configuration file, then select DS21352DK_DRVR.cfg.
- The Demo Mode screen appears. Upon external loopback, the LOS and OOF indicators extinguish. Quick Setup (Register View)
- The PC loads the program, offering a choice among Demo Mode, Register View, and Terminal Mode. Select Register View.
- The program requests a definition file, then select DS21352.def.
- The Register View screen appears, showing the register names, acronyms, and values. Note: During th edefinition file load process, all registers are initialized according to the init value filed in the definition file (because the SETUP field in the .def file is turned on).
- Predefined register settings for several functions are available as initialization files. ⎯ INI files are loaded by selecting the menu F ile→Reg Ini File→Load Ini File. ⎯ Load the INI file DS21352t1_b8zs_esf.ini. ⎯ After loading the INI file the following may be observed: The RLOS LED extinguishes upon external loopback. The device is now configured for T1 B8ZS ESF. Miscellaneous:
- Clock frequencies and certain pin bias levels are provided by a register-mapped CPLD, which is on the DS21352 daughter card.
- The definition file for this CPLD is named DS215x_35x_CPLD_V2.def. See the CPLD Register Map section for definitions.
- All files referenced above are available for download in the section marked “File Locations.”
The DK101 daughter card address space begins at 0x81000000. All offsets given in Table 1 are relative to the beginning of the daughter card address space. Table 1. Daughter Card Address Map Please see the data sheet(s) for details. DS21352.def, or DS21354.def, depending on the board population option. Table 2. CPLD Register Map
The control registers are used primarily to control severa l banks of FET switches that route clocks and backplane both to 0 would drive MCLK with both 1.544MHz and 2.048MHz. SWITCH1: PIN TO 1.544MHz (OFFSET = 0x0011) INITIAL VALUE = 0xF (MSB) (LSB) — — — — MCLK TCLK RSYSCLK TSYSCLK NAME POSITION FUNCTION MCLK SWITCH1.3 0 = Connect MCLK to the 1.544MHz clock 1 = Open Switch 1.4 TCLK SWITCH1.2 0 = Connect TCLK to the 1.544MHz clock 1 = Open Switch 1.3 RSYSCLK SWITCH1.1 0 = Connect RSYSCLK to the 1.544MHz clock 1 = Open Switch 1.2 TSYSCLK SWITCH1.0 0 = Connect TSYSCLK to the 1.544MHz clock 1 = Open Switch 1.1 SWITCH2: PIN TO 2.048MHz (Offset = 0x0012) INITIAL VALUE = 0x3 (MSB) (LSB) — — — — MCLK TCLK RSYSCLK TSYSCLK NAME POSITION FUNCTION MCLK SWITCH2.3 0 = Connect MCLK to the 2.048MHz clock 1 = Open Switch 2.4 TCLK SWITCH2.2 0 = Connect TCLK to the 2.048MHz clock 1 = Open Switch 2.3 RSYSCLK SWITCH2.1 0 = Connect RSYSCLK to the 2.048MHz clock 1 = Open Switch 2.2 TSYSCLK SWITCH2.0 0 = Connect TSYSCLK to the 2.048MHz clock 1 = Open Switch 2.1 SWITCH3: PIN-TO-PIN CONNECT (Offset = 0x0013) INITIAL VALUE = 0xF (MSB) (LSB) NAME POSITION FUNCTION TSS_RS SWITCH3.3 0 = Connect TSSYNC to RSYNC 1 = Open Switch 3.4 TCL_RC SWITCH3.2 0 = Connect TCLK to RCLK 1 = Open Switch 3.3 RSY_RC SWITCH3.1 0 = Connect RSYSCLK to RCLK 1 = Open Switch 3.2 TSY_RC SWITCH3.0 0 = Connect TSYSCLK to RCLK 1 = Open Switch 3.1
SWITCH4: PIN-TO-PIN CONNECT (Offset = 0x0014) INITIAL VALUE = 0x3 (MSB) (LSB) — — — — URCLK_2048 UTCLK_2048 RSER_TSER RSYNC_TSYNC NAME POSITION FUNCTION URCLK_2048 SWITCH4.3 0 = Connect UR_CLK (TSSYNC) to 2.048MHz 1 = Open Switch 4.4 UTCLK_2048 SWITCH4.2 0 = Connect UT_CLK (TCHCLK) to 2.048MHz 1 = Open Switch 4.3 RSER_TSER SWITCH4.1 0 = Connect RER to TSER 1 = Open Switch 4.2 RSYNC_TSYNC SWITCH4.0 0 = Connect RSYNC to TSYNC 1 = Open Switch 4.1 LEVELS: SET LEVEL ON PIN (Offset = 0x0015) INITIAL VALUE = 0x6 (MSB) (LSB) NAME POSITION FUNCTION — LEVELS1.3 — BP_EN LEVELS1.2 0 = Enable IDT switches that connect the UTOPIA bus to daughter card header PPCTDM_EN LEVELS1.1 0 = Enable IDT switches that connect the TDM bus to the daughter card header TUSEL LEVELS1.0 0 = Set DS2156.TUSEL to enable TDM backplane 1 = Set DS2156.TUSEL to enable UTOPIA backplane Note (DS2156 only): When the UTOPIA backplane is enabled (LEVELS.TUSEL = 1) there is a possibility for contention between the UTOPIA bus master and TSYSCLK, TSER, and RSER . To avoid this, the following switches should be opened when the UTOPIA backplane is enabled: SWITCH1.0, SWITCH2.0, SWITCH3.0, and SWITCH4.1
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor. DS21352 INFORMATION For more information about the DS21352, please cons ult the DS21352 data sheets available on our website at www.maxim-ic.com/DS21352. Software downloads are also available for this design kit. DS21352DK INFORMATION For more information about the DS21352DK, including software downloads, please consult the DS21352DK data sheet available on our website at www.maxim-ic.com/DS21352DK. TECHNICAL SUPPORT For additional technical support, please e-mail your questions to telecom.support@dalsemi.com. SCHEMATICS The DS21352DK schematics are featured in the following 13 pages. DOCUMENT REVISION HISTORY REVISION DATE DESCRIPTION 060303 Initial DS21352DK data sheet release.
011904 Updated the General Description and Features sections; added the Demo Kit
Contents section.
012705 Updated schematics (removed component values for Fuse and Sidactor; see
Component List). 110106 Updated schematics.
D_AD2 D_AD3 UOP3 UOP2 UOP1 UOP0 ESIBS1 ESIBS0 BPCLK RMSYNC D_AD4 D_AD5 D_AD6 D_AD7 TSYSCLK TLCLK 8XCLK TTIP LIUC RCL INT D_AD0 CS TCHBLK RCHBLK TSSYNC TCLK TLINK RPOSI TSIG TCHCLK TSYNC TRING TPOSO TCLKI TCLKO TNEGO JTRST JTDO TPOSI RFSYNC BTS MUX RSIG RSER TUSEL TSER ESIBRD XTALD N_P27 RDATA JTMS JTDI JTCLK RLOS_LOTC RNEGI TNEGI RSYSCLK RCLKI RPOSO RNEGO RCLKO MCLK RSIGF TSTRST RD_DS WR_RW N_P28 RRING D_AD1 RLCLK RCHCLK RSYNC RLINK RCLK RTIP DS2156L U11 100 47 48
22 TDATA
PAGE: DATE: TITLE: ENGINEER: A A B B C C D D V3_3 TQFP DS2156 D/AD<2> D/AD<3> UOP3 UOP2 UOP1 UOP0 ESIBS<1> ESIBS<0> DVSS4 DVSS3 BPCLK RMSYNC ALE/AS/A<7> D/AD<4> D/AD<5> D/AD<6> D/AD<7> TSYSCLK TLCLK 8XCLK TTIP LIUC RCL INT* A<0> A<1> D/AD<0> CS* TCHBLK RCHBLK TSSYNC TDATA TCLK TLINK RVDD RPOSI TESO TSIG TCHCLK TSYNC DVDD3 TRING TPOSO TCLKI TCLKO TNEGO JTRST JTDO RVSS1 TVSS TPOSI RFSYNC TVDD DVDD1 DVDD2 DVSS1 DVSS2 BTS MUX RSIG RSER RVSS2 NC1 TSER ESIBRD XTALD NC2 RDATA A<4> A<3> JTMS JTDI JTCLK RLOS/LOTC RNEGI TNEGI RSYSCLK RCLKI RPOSO RNEGO RCLKO MCLK RSIGF TSTRST RD/DS* WR/RW* NC3 RRING RVSS3 A<2> D/AD<1> RLCLK RCHCLK RSYNC DVDD4 A<5> A<6> RLINK RCLK RTIP
/ 13 10/04/02 STEVE SCULLY DS2156DK02A0 2 1 C25 2 1 C24 2 1 R60 Z10 R59 R58
1 C23
49.9 0.22UF 24 UH RRING RTIP TRING TTIP 61.9 61.9 51.1 0.22UF 0.22UF 49.9 0.1UF 1UF 24 UH 0.22UF PAGE: DATE: TITLE: ENGINEER: A A B B C C D D Z Z Z Z Z RJ48 Z CONN_BANTAM_IPC R T CONN_BANTAM_IPC R T DPDT Z Z 1:1 1:0.8 Z 1:1 1:0.8 Z CONN_BNC_5PIN CONN_BNC_5PIN
(TIM LSB)
13 STEVE SCULLY
SNIM_B4 A10 NIMD13 RESET_OUT PPC_RXCLK PPC_TXCLK A12 A13 SNIM_B3 SNIM_B2 CLK16384_T A15 A14 D_AD7 D_AD6 D_AD5 TIM5V TIM5V CLK1544_T SNIM_B6 SNIM_B5 51.1 PPC_TXD PPC_RXD INT WE_T RW_T PPC_RSYNC D_AD0 D_AD2 D_AD3 D_AD4 CS_T PPC_TSYNC SNIM_B7 NIMD11 NIMD10 NIMD9 NIMD8 NIMD12 D_AD1 1 2 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PAGE: DATE: TITLE: ENGINEER: A A B B C C D D 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 24 23 22 21 25 26 20 19 V3_3 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 24 23 22 21 25 26 20 19
ALL UNMARKED BIAS RESISTORS ARE 10K GREEN LEDS DS7 ..TO.. DS18 / 13 10/04/02 STEVE SCULLY DS2156DK02A0 JT10 DS16 DS17 TSSYNC A12 BP_EN 10K
12 R61
12 R44
12 R28
12 R47
12 R16
12 R23
21 R22
21 R49
12 R10
21 R38
21 R32
21 R48
21 R37
21 R19
21 R29
21 R18
21 R15
21 R17
21 R13
INT_INDICATOR RED TSYSCLK CLK16384_T CLK2048 TUSEL MUX RESET_OUT RW_T CS_T PPC_TDM_EN WE_T A11 INT LIUC TSIG TLINK 330 330 330 330 330 330 330 330 330 330 330 330 RED 10K 10K 1.0K TCK SW4_B2EN SW4_B3EN CS RD_DS WR_RW BTS D_AD0 D_AD1 D_AD4 D_AD6 RLOS_LOTC INT SW3_B3EN D_AD2 SW4_B0EN SW4_B1EN TCK TDO TDI RSYNC TSYNC TCLK TDO TDI TMS ESIBRD RPOSI RNEGI RCLKI TNEGI TCLKI TSTRST MUX 330 TMS 330 D_AD5 D_AD3 SW2_B3EN SW2_B1EN SW1_B2EN SW1_B0EN SW2_B2EN 330 D_AD7 SW3_B0EN SW3_B1EN SW3_B2EN RLOS_LOTC_INDICATOR TSER TPOSI RSYSCLK 4.7K JTRST 330 SW2_B0EN SW1_B3EN SW1_B1EN PAGE: DATE: TITLE: ENGINEER: A A B B C C D D V3_3 V3_3 V3_3 CONN_10P V3_3 TP TP TP V3_3 XILINX_XC9572XL TDI TDO GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 3.3V2 TCK TMS NC<8-0> 2.5V_3.3V1 2.5V_3.3V2 2.5V_3.3V3 2.5V_3.3V4 3.3V1 3.3V3 V3_3 TP XILINX_XC9572XL GCK1 GCK2 GCK3 IO17 IO18 IO34 IO24 IO23 IO54 IO53 IO52 IO51 IO50 IO49 IO48 IO47 IO46 IO45 IO44 IO43 IO42 IO41 IO40 IO39 IO38 IO37 IO19 IO20 IO21 IO22 IO25 IO26 IO27 IO28 IO29 IO30 IO31 IO32 IO33 IO35 IO36 IO16 IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO8 IO7 IO6 IO5 IO4 IO3 IO1 IO61 IO72 IO71 IO70 IO69 IO68 IO67 IO66 IO65 IO64 IO63 IO62 IO60 IO59 IO58 IO55 IO57 IO56 IO2 TP TP
BP_EN IS BIT MAPPED TO LOGIC 0 CLOSES SWITCHES TIM J2X PLD ADDRESS 0X15 BIT 2 DS2156DK02A0 STEVE SCULLY 10/04/02 6 13 22 21 20 19 18 17 16 15 14 13 12 11 10 9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 DS4
21 R12
TXDATA_4 BP_EN RXPRTY 51.1 51.1 330 GREEN UT_CLK TXA_0 TXA_4_TXCLAV_3 TXENA TXDATA_3 TXDATA_1 TXDATA_5 TXDATA_7 TXA_2_TXCLAV_1 BP_EN TXA_4_TXCLAV_3 UR_CLK RXA_2_RXCLAV_1 RXENA RXDATA_1 RXDATA_5 RXDATA_3 RXDATA_7 RXA_0 RXA_4_RXCLAV_3 TXA_2_TXCLAV_1 GND TXPRTY GND GND GND GND GND GND GND RXA_3_RXCLAV_2 TXCLAV_0 TXA_3_TXCLAV_2 TXSOC TXDATA_0 TXDATA_2 TXDATA_6 TXA_1 TXA_3_TXCLAV_2 RXSOC RXDATA_0 RXDATA_4 RXDATA_2 RXDATA_6 RXA_1 BP_EN BP_EN RXA_4_RXCLAV_3 RXA_2_RXCLAV_1 RXCLAV_0 RXA_3_RXCLAV_2 PAGE: DATE: TITLE: ENGINEER: A A B B C C D D IDTQS3R861 NC1 GND VCC BE* V3_3 IDTQS3R861 NC1 GND VCC BE* IDTQS3R861 NC1 GND VCC BE* V3_3 IDTQS3R861 NC1 GND VCC BE* V3_3 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 24 23 22 21 25 26 20 19 V3_3
WE_T 1TP8 RESET_OUT TP6 1 CS_T TP7 1 A13 1 TP2 CLK16384_T 1 TP1 CLK1544_T TP16 1 RW_T 1TP9 A9 TP10 1 A8 TP11 1 A12 TP3
21 R21
12 R14
1 TP5
UT_CLK TXDATA_0 TXDATA_7 TXADDR4 TXADDR2 TXADDR0 TXENABLE TXSOC GND TXDATA_4 RXDATA_1 RXADDR0 GND GND TXDATA_2 UR_CLK RXSOC RXDATA_3 RXDATA_6 RXDATA_2 RXDATA_0 GND RXADDR4 GND RXENB RXADDR1 RXDATA_4 GND RXCLAV0 RXADDR3 RXADDR2 GND RXDATA_5 RXDATA_7 TXDATA_3 TXDATA_6 GND TXADDR1 TXCLAV0 TXDATA_1 TXADDR3 GND GND TXDATA_5 51.1 PAGE: DATE: TITLE: ENGINEER: A A B B C C D D TP TP TP TP TP TP TP TP 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 24 23 22 21 18 17 16 15 14 13 12 11 25 26 CONN_50P1 20 19 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 24 23 22 21 18 17 16 15 14 13 12 11 25 26 CONN_50P1 20 19 TP TP TP TP TP TP TP
UR_SOC UR_ENB UOP3 TXA_1 TXA_2_TXCLAV_1 NOPOP 0.1UF NOPOP 0.1UF TXDATA_6 TXDATA_6 TSIG TSYSCLK TXDATA_7 TXDATA_7 TXENA TXENABLE UOP1 UOP0 TXSOC TXSOC TSSYNC UT_CLK TCHCLK UR_CLK UT_DATA6 RXENA RXENB BPCLK RXSOC UT_DATA7 UT_ENB UT_SOC RCHBLK TXA_0 TXADDR0 TCHBLK TXADDR2 TLCLK TXA_3_TXCLAV_2 TXADDR3 TLINK TXA_4_TXCLAV_3 TXADDR4 UT_CLAV TXCLAV0 TPOSI LIUC UT_ADDR0 UT_ADDR1 UT_ADDR2 UT_ADDR3 UT_ADDR4 TXCLAV_0 TXDATA_0 TXDATA_0 TNEGI TXDATA_1 TXDATA_1 TCLKI TCLKO TXDATA_2 TXDATA_2 TXDATA_3 TXDATA_3 TNEGO TXDATA_4 TXDATA_4 TPOSO TSER TXDATA_5 TXDATA_5 UT_DATA0 UT_DATA1 UT_DATA2 UT_DATA3 UT_DATA4 UT_DATA5 RCHCLK RXA_0 RXADDR0 RXA_1 RXADDR1 UR_ADDR0 RSIGF RXA_2_RXCLAV_1 RXADDR2 RSIG RXA_3_RXCLAV_2 RXADDR3 RMSYNC RXA_4_RXCLAV_3 RXADDR4 RFSYNC UR_ADDR1 UR_ADDR2 UR_ADDR3 UR_ADDR4 RXCLAV_0 RXCLAV0 RSER RXDATA_0 RXDATA_0 RLINK RXDATA_1 RXDATA_1 UR_CLAV UR_DATA0 RLCLK RXDATA_2 RXDATA_2 RPOSI RXDATA_3 RXDATA_3 RNEGI RXDATA_4 RXDATA_4 RCLKI UR_DATA1 UR_DATA2 UR_DATA3 UR_DATA4 RXDATA_5 RXDATA_5 RCLKO RXDATA_6 RXDATA_6 RNEGO RXDATA_7 RXDATA_7 RPOSO UR_DATA5 UR_DATA6 UR_DATA7 TXADDR1 PAGE: DATE: TITLE: ENGINEER: A A B B C C D D
PPC_TDM_EN IS BIT MAPPED TO TO PLD REGISTER 0X14 SWITCH 4 IS MEMORY MAPPED LOGIC 0 CLOSES SWITCH TO PLD REGISTER 0X13 TO PLD REGISTER 0X12 LOGIC 0 CLOSES SWITCH TO PLD REGISTER 0X11 LOGIC 1 OPENS SWITCH LOGIC 0 CLOSES SWITCH SWITCH 1 IS MEMORY MAPPED LOGIC 1 OPENS SWITCH LOGIC 0 CLOSES SWITCH SWITCH 3 IS MEMORY MAPPED LOGIC 1 OPENS SWITCH SWITCH 2 IS MEMORY MAPPED PLD ADDRESS 0X15 BIT 1LOGIC 0 CLOSES SWITCHES 13 9 10/04/02 STEVE SCULLY DS2156DK02A0 U10 DS1 21 R7 SW1_B1EN SW4_B1EN SW4_B0EN SW1_B2EN SW2_B2EN SW2_B1EN SW2_B0EN MCLK RSYSCLK TSYSCLK SW1_B3EN TCLK MCLK PPC_TXD PPC_TDM_EN PPC_RXD PPC_RXCLK PPC_TSYNC PPC_RSYNC PPC_TXCLK TSER RSER RCLK TCLK TSYNC RSYNC TSER TSYNC SW4_B3EN SW4_B2EN UT_CLK UR_CLK RSER RSYNC RCLK RCLK TSSYNC TCLK SW3_B3EN SW3_B2EN SW3_B1EN SW3_B0EN RCLK RSYNC RSYSCLK TSYSCLK CLK2048 CLK2048 GREEN 330 TCLK RSYSCLK TSYSCLK SW2_B3EN CLK1544_T SW1_B0EN PAGE: DATE: TITLE: ENGINEER: A A B B C C D D V3_3 IDTQS3125 4OE* 3OE* 2OE* 1OE* NC2 GND VCC NC1 V3_3 IDTQS3125 4OE* 3OE* 2OE* 1OE* NC2 GND VCC NC1 IDTQS3125 4OE* 3OE* 2OE* 1OE* NC2 GND VCC NC1 V3_3 IDTQS3125 4OE* 3OE* 2OE* 1OE* NC2 GND VCC NC1 V3_3 IDTQS3R861 NC1 GND VCC BE* V3_3
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 1UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF VCC PAGE: DATE: TITLE: ENGINEER: A A B B C C D D V3_3 TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP V3_3
/ 13 11 10/04/02 DS2156DK02A0 STEVE SCULLY 48 47 100 RLINK RSYNC RSYSCLK RDATA RFSYNC TCLK TLINK TSYNC TSYSCLK TLCLK TDATA TSSYNC D_AD2 D_AD3 UOP3 UOP2 UOP1 UOP0 ESIBS1 ESIBS0 BPCLK RMSYNC D_AD4 D_AD5 D_AD6 D_AD7 8XCLK TTIP LIUC RCL INT D_AD0 CS TCHBLK RCHBLK RPOSI TSIG TCHCLK TRING TPOSO TCLKI TCLKO TNEGO JTRST JTDO TPOSI BTS MUX RSIG RSER TUSEL TSER ESIBRD XTALD N_P27 JTMS JTDI JTCLK RLOS_LOTC RNEGI TNEGI RCLKI RPOSO RNEGO RCLKO MCLK RSIGF TSTRST RD_DS WR_RW N_P28 RRING D_AD1 RLCLK RCHCLK RCLK RTIP VALUE=NA PAGE: DATE: TITLE: ENGINEER: A A B B C C D D TQFP DS2156 D/AD<2> D/AD<3> UOP3 UOP2 UOP1 UOP0 ESIBS<1> ESIBS<0> DVSS4 DVSS3 BPCLK RMSYNC ALE/AS/A<7> D/AD<4> D/AD<5> D/AD<6> D/AD<7> TSYSCLK TLCLK 8XCLK TTIP LIUC RCL INT* A<0> A<1> D/AD<0> CS* TCHBLK RCHBLK TSSYNC TDATA TCLK TLINK RVDD RPOSI TESO TSIG TCHCLK TSYNC DVDD3 TRING TPOSO TCLKI TCLKO TNEGO JTRST JTDO RVSS1 TVSS TPOSI RFSYNC TVDD DVDD1 DVDD2 DVSS1 DVSS2 BTS MUX RSIG RSER RVSS2 NC1 TSER ESIBRD XTALD NC2 RDATA A<4> A<3> JTMS JTDI JTCLK RLOS/LOTC RNEGI TNEGI RSYSCLK RCLKI RPOSO RNEGO RCLKO MCLK RSIGF TSTRST RD/DS* WR/RW* NC3 RRING RVSS3 A<2> D/AD<1> RLCLK RCHCLK RSYNC DVDD4 A<5> A<6> RLINK RCLK RTIP V3_3
RCL 2C8> 11C7> RDATA 2D6> 11D5> NIMD11 4B2<> NIMD12 4B2<> NIMD13 4B2<> NIMD14 4B2<> NIMD15 4C2<> N_P27 2A4< 11A4< N_P28 2A3< 11A3< NIMD10 4B2<> NIMD9 4B2<> NIMD8 4B2<> RLCLK 2D6> 8B7> 11D5> RFSYNC 2D6> 8C7> 11D5> RCLKO 2C8> 8A7> 11C7> RCLKI 8A7> 2C8< 5A8< 11C7< RCHCLK 2D6> 8D7> 11D5> RCHBLK 2C3> 8D4> 11C3> MUX 5C4<> 2A3< 5A8< 11A3< INT_INDICATOR 5A2<> JTCLK 2A8< 11A7< JTDI 2A8< 11A7< JTDO 2A8> 11A7> JTMS 2B8< 11B7< A15 4B3<> A14 4B3<> A13 4B3<> 7B3<> A10 4C3<> 7C3<> ESIBS0 2A6<> 11A6<> ESIBS1 2A6<> 11A5<> JTRST 2B8< 5A8< 11A7< LIUC 8B4> 2C8< 5A6< 11B7< CS 5B4<> 2C3< 11C3< BTS 5D4<> 2B3< 5A6< 11A3< BPCLK 2A5> 8D4> 11A4> SW4_B3EN 5B4<> 9B2< TCHBLK 2D3> 8C4> 11C3> TCHCLK 2D5> 11D4> 8A1< TCK 5B8<> 5D8< TCLKI 8B4> 2B8< 5A8< 11B7< TCLKO 2B8> 8A4> 11B7> TDATA 2D5<> 11D4<> TDI 5B8<> 5D7< TDO 5B8<> 5C7< TIM5V 4D3<> 4D8<> TLCLK 2D5> 8C4> 11D4> TLINK 8C4> 2D5< 5B6< 11D5< TMS 5B8<> 5C7< SW4_B2EN 5B4<> 9B2< SW4_B1EN 5B4<> 9B3< SW4_B0EN 5B4<> 9B3< SW3_B3EN 5A3<> 9D1< SW3_B2EN 5A3<> 9D1< SW3_B1EN 5A3<> 9D3< SW3_B0EN 5A3<> 9D3< SW2_B3EN 5A3<> 9B6< SW2_B2EN 5A3<> 9B6< SW2_B1EN 5A3<> 9B8< SW2_B0EN 5A3<> 9B8< SW1_B3EN 5A3<> 9D6< SW1_B2EN 5A3<> 9D6< SW1_B1EN 5A4<> 9D8< SW1_B0EN 5A4<> 9D8< SNIM_B7 4C2<> SNIM_B6 4C2<> SNIM_B5 4C2<> SNIM_B4 4C2<> SNIM_B3 4C2<> SNIM_B2 4C2<> RXSOC 6B7<> 7B6<> 8D4> 8D5 RXPRTY 6B5<> RXENB 7A6<> 8D5 RXENA 6A2<> 8D4> RXCLAV_0 6A7<> 8C7> RXCLAV0 7A8<> 8C8 RXA_1 6B7<> 8D7> RXA_0 6B2<> 8D7> RXADDR4 7B6<> 8C8 RXADDR3 7B8<> 8C8 RXADDR2 7B8<> 8D8 RXADDR1 7B6<> 8D8 RXADDR0 7B8<> 8D8 RTIP 2C8< 3B8< 11C7< 11D5< 5A6< A8 4C6<> 7B1<> 8XCLK 2C8> 11C7> * Signal Cross-Reference for the entire design * RNEGO 2C8> 8A7> 11C7> RPOSI 8B7> 2C8< 5A8< 11C7< RPOSO 2C8> 8A7> 11C7> RRING 2C8< 3B8< 11C7< RSIG 2A5> 8D7> 11A5> RSIGF 2A5> 8D7> 11A4> RNEGI 8B7> 2C8< 5A8< 11C7< RMSYNC 2A5> 8C7> 11A5> RLOS_LOTC_INDICATOR 5A2<> RLOS_LOTC 2C3> 5B2<> 11C3> RLINK 2D6> 8B7> 11D6> UT_SOC 8B2 UT_ENB 8C2 UT_DATA7 8D2 UT_DATA5 8A5 UT_DATA4 8A5 UT_DATA3 8A5 UT_DATA2 8A5 UT_DATA0 8B5 UT_CLAV 8B4> UT_ADDR4 8C5 UT_ADDR3 8C5 UT_ADDR1 8C5 UT_ADDR0 8D5 UR_SOC 8D5 UR_ENB 8D5 UR_DATA7 8A8 UR_DATA5 8A8 UR_DATA4 8A8 UR_DATA3 8B8 UR_DATA2 8B8 UR_DATA1 8B8 UR_DATA0 8B8 UR_CLAV 8C8 UR_ADDR4 8C8 UR_ADDR3 8C8 UR_ADDR2 8D8 UR_ADDR1 8D8 UR_ADDR0 8D8 UOP2 2A6> 11A5> UOP1 2A6> 8C1> 11A5> UOP0 2A6> 8B1> 11A5> TXSOC 6C7<> 7B4<> 8B1> 8B2 TXPRTY 6C5<> TXENABLE 7B4<> 8C2 TXCLAV_0 6C7<> 8B5 TXCLAV0 7B5<> 8B5 TXA_0 6C2<> 8D4> TXADDR4 7B4<> 8C5 TXADDR3 7B5<> 8C5 TXADDR2 7B4<> 8C5 TXADDR1 7B4<> 8C5 TXADDR0 7B5<> 8D5 TTIP 2B8> 11B7> 3C8< TSTRST 2A5< 5A8< 11A4< TSSYNC 9C3<> 2D5< 5B6< 8A1< 11D4< TSIG 8D1> 2D5< 5B6< 11D4< TRING 2B8> 11B7> 3C8< TPOSO 2B8> 8A4> 11B7> TPOSI 8C4> 2B8< 5A8< 11B7< TNEGO 2B8> 8A4> 11B7> TNEGI 8B4> 2B8< 5A8< 11B7< 11D4< XTALD 2A5> 11A4> TUSEL 5D2<> 2A4< 11A4< TXA_1 6C7<> 8C4> TXENA 6C2<> 8C1> UOP3 2A6> 8D4> 11A5> UR_DATA6 8A8 UT_ADDR2 8C5 UT_DATA1 8B5 UT_DATA6 8D2 /STEVE SCULLY DS2156DK02A0 10/04/02 12 13 PAGE: DATE: TITLE: ENGINEER: A A B B C C D D
J5 CONN_BNC_5PIN 3A3 J7 CONN_50P2 6D4 J8 CONN_50P2 4D3 JT10 CONN_10P 5C8 R1 RES1 4B2 R3 RES 3B7 R4 RES 6A2 R6 RES1 5A7 J4 CONN_BANTAM_IPC 3C1 J1 CONN_50P1 7D5 J2 CONN_50P1 7D7 J3 CONN_BANTAM_IPC 3B1 F6 FUSE 3A3 F5 FUSE 3D4 F4 FUSE 3C4 F3 FUSE 3D4 F2 FUSE 3B4 F1 FUSE 3B4 DS18 LED 5A3 DS17 LED 5B5 DS16 LED 5B5 DS15 LED 5A3 DS14 LED 5A3 DS13 LED 5A3 DS12 LED 5A3 DS11 LED 5A4 DS10 LED 5A3 DS9 LED 5A4 DS8 LED 5A4 DS7 LED 5A3 DS6 LED 5A4 DS5 LED 5A3 DS4 LED 6D5 DS3 LED 5A2 DS2 LED 5A2 DS1 LED 9B4 C36 CAP 10B6 C35 CAP 10B6 C34 CAP 10B5 C33 CAP 10B5 C32 CAP 10B5 C31 CAP 10B6 C30 CAP 10B4 C29 CAP 10B4 C27 CAP 3D5 C26 CAP 3A5 C25 CAP 3B5 C24 CAP 3C5 C23 CAP 3A6 C22 CAP 10B5 C21 CAP 10B2 C19 CAP 10B3 C18 CAP 10B3 C17 CAP 10B2 C16 CAP 10B3 C15 CAP 10B3 C14 CAP 8A1 C13 CAP 8A1 C12 CAP 10B2 TP6 TSTPNT_SNG 7B2 TP7 TSTPNT_SNG 7B2 TP8 TSTPNT_SNG 7B2 TP9 TSTPNT_SNG 7B2 TP10 TSTPNT_SNG 7B2 TP11 TSTPNT_SNG 7B2 TP12 TSTPNT_SNG 5D2 TP13 TSTPNT_SNG 5D2 TP14 TSTPNT_SNG 5A6 TP15 TSTPNT_SNG 5A6 TP16 TSTPNT_SNG 7B2 TP17 TSTPNT_SNG 5D2 TP18 TSTPNT_SNG 5A6 TP20 TSTPNT_SNG 7B2 TP21 TSTPNT_SNG 7B1 TP5 TSTPNT_SNG 7C2 TP4 TSTPNT_SNG 7C2 TP3 TSTPNT_SNG 7B2 TP2 TSTPNT_SNG 7B2 TP1 TSTPNT_SNG 7B2 T1 XFMR_2IN_4OUT_U 3B5 3D5 SW1 SWITCH_DPDT_SLIDE_6P 3A6 RJ1 RJ48_CON 3C3 R61 RES1 5A7 R60 RES 3A5 R59 RES 3C7 R58 RES 3D7 R57 RES 3B6 R56 RES 3B5 R55 RES1 3B6 R54 RES1 3B6 R53 RES 5A3 R52 RES 5B4 R51 RES 5B4 R50 RES 5A3 R49 RES1 5A7 R48 RES1 5A6 R47 RES1 5A7 R46 RES1 5B7 R45 RES 5A3 R44 RES1 5A7 R43 RES 5A3 R42 RES 5A4 R41 RES 5A3 R40 RES 5A4 R39 RES 5A3 R38 RES 5A7 R37 RES1 5A6 R36 RES 5A3 R35 RES 5A3 R34 RES1 8A1 R33 RES1 8A1 R32 RES1 5A6 R31 RES 5A3 R30 RES 5A3 R29 RES1 5A6 R28 RES1 5A7 R27 RES1 5D8 R26 RES1 5D8 R25 RES1 5D7 R24 RES1 5B8 R23 RES1 5A7 R22 RES1 5A7 R21 RES1 7A8 R19 RES1 5A6 C11 CAP 10B4 C10 CAP 10B4 C9 CAP 10B4 C8 CAP 10B4 C7 CAP 3D6 C5 CAP 10B2 C4 CAP 10B2 C3 CAP 10B2 C2 CAP 10B3 C1 CAP 10B5
1 DS2156_TQFP 11D7
* Part Cross-Reference for the entire design * R12 RES 6D5 R13 RES1 5B6 R14 RES1 7B4 R15 RES1 5B6 R16 RES1 5A7 R17 RES1 5B6 R18 RES1 5A6 R11 RES1 5A2 R10 RES1 5A7 R9 RES1 5A7 R8 RES1 5A2 R7 RES 9B4 Z10 SIDACTOR_2 3B4 Z9 SIDACTOR_2 3C4 Z8 SIDACTOR_2 3A4 Z7 SIDACTOR_2 3C4 Z6 SIDACTOR_2 3A4 Z4 SIDACTOR_2 3B5 Z3 SIDACTOR_2 3A5 Z2 SIDACTOR_2 3D5 Z1 SIDACTOR_2 3C4 U11 DS2156_TQFP 2D7 U10 IDTQS3125_U 9B7 U8 IDTQS3125_U 9D7 U7 IDTQS3125_U 9D3 U6 IDTQS3R861_U 9B5 U5 XILINX_XC9572XL 5D4 5D7 U3 IDTQS3R861_U 6B6 U2 IDTQS3R861_U 6D3 U1 IDTQS3R861_U 6B3 TP38 TSTPNT_SNG 10A5 TP36 TSTPNT_SNG 10A5 TP35 TSTPNT_SNG 10A5 TP34 TSTPNT_SNG 10A5 TP33 TSTPNT_SNG 10A5 TP31 TSTPNT_SNG 10A4 TP30 TSTPNT_SNG 10A7 TP29 TSTPNT_SNG 10A7 TP27 TSTPNT_SNG 10A7 TP26 TSTPNT_SNG 10A7 TP24 TSTPNT_SNG 10A8 TP23 TSTPNT_SNG 10A7 TP22 TSTPNT_SNG 7B1 TP25 TSTPNT_SNG 10A7 TP28 TSTPNT_SNG 10A7 TP32 TSTPNT_SNG 10A4 TP37 TSTPNT_SNG 10A5 U4 IDTQS3R861_U 6D6 U9 IDTQS3125_U 9B3 Z5 SIDACTOR_2 3C6 R5 RES 6C2 R2 RES 3B7 L1 CHOKE_DUAL_T1 3B4 3C4 J9 CONN_50P2 4D7 J6 CONN_BNC_5PIN 3D2 /STEVE SCULLY DS2156DK02A0 10/04/02 13 13 PAGE: DATE: TITLE: ENGINEER: A A B B C C D D