DS1992 MAXIM | Alldatasheet
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1 of 17 REV: 101408 SPECIAL FEATURES 4096 bits of Read/Write Nonvolatile Memory (DS1993) 1024 bits of Read/Write Nonvolatile Memory (DS1992) 256-bit Scratchpad Ensures Integrity of Data Transfer Memory Partitioned into 256-bit Pages for Packetizing Data Data Integrity Assured with Strict Read/Write Protocols Operating Temperature Range from -40°C to +70°C Over 10 years of data retention
ORDERING INFORMATION
DS9096P Self-Stick Adhesive Pad DS9101 Multipurpose Clip DS9093RA Mounting Lock Ring DS9093F Snap-In Fob DS9092 i Button Probe F5 MicroCan COMMON iButton FEATURES Unique, Factory-Lasered and Tested 64-bit Registration Number (8-bit Family Code + 48-bit Serial Number + 8-bit CRC Tester) Assures Absolute Traceability Because No Two Parts are Alike Multidrop Controller for MicroLAN Digital Identification and Information by Momentary Contact Chip-Based Data Carrier Compactly Stores Information Data Can be Accessed While Affixed to Object Economically Communicates to Bus Master with a Single Digital Signal at 16.3kbps Standard 16mm Diameter and 1-Wire® Protocol Ensure Compatibility with iButton® Family Button Shape is Self-Aligning with Cup- Shaped Probes Durable Stainless Steel Case Engraved with Registration Number Withstands Harsh Environments Easily Affixed with Self-Stick Adhesive Backing, Latched by its Flange, or Locked with a Ring Pressed onto its Rim Presence Detector Acknowledges When Reader First Applies Voltage Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Concept for use in Class I, Division 1, Group A, B, C and D Locations DS1992/DS1993 1Kb/4Kb Memory iButton® www.iButton.com 1-Wire and iButton are registered trademarks of Maxim Integrated Products, Inc.
The DS1992/DS1993 memory i Buttons (hereafter referred to as DS199_) are rugged read/write data carriers that act as a localized database, easil y accessible with minimal hardware. The nonvolatile memory and optional timekeeping capability offer a simple solution to stor ing and retrieving vital information pertaining to th e object to which the i Button is attached. Data is transferred serially through the 1-Wire protocol that requires only a single data lead and a ground return. The scratchpad is an additional page that acts as a bu ffer when writing to memory. Data is first written to the scratchpad where it can be re ad back. After the data has been verified, a copy scratchpad command transfers the data to memory. This process ensures data integrity when modifying the memory. A 48-bit serial number is factory lasered into each DS199_ to pr ovide a guaranteed unique identity that allows for absolute traceability. The durable MicroCan package is highly resistant to environmental hazards such as dirt, moisture, and shock. Its compact coin-shaped profile is self-aligning wi th mating receptacles, allowing the DS199_ to be easily used by human operators. Accessories permit the DS199_ to be mounted on almost any surface including plastic key fobs, photo-ID badges, and PC boards. Applications include access control, work-in-progress tracking, electronic travelers, storage of calibration constants, and debit tokens. OPERATION The DS199_ have three main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad, and 3) 1024-bit (DS1992) or 4096-bit (DS1993) SRAM. All data is read and written least significant bit first. The memory functions are not avai lable until the ROM f unction protocol has been established. This protocol is described in the ROM f unctions flow chart (Figure 9). The master must first provide one of four ROM function commands: 1) read ROM, 2) match ROM, 3) search ROM, or 4) skip ROM. After a ROM function sequence has been successfully execute d, the memory functions are accessible and the master can then provide any one of the four memory function commands (Figure 6). PARASITE POWER The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry steals power whenever the data input is high. The data line provides sufficie nt power as long as the sp ecified timing and voltage requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input, battery power is not consumed for 1-Wire ROM function commands, and 2) if the battery is exhausted for any reason, the ROM may still be read normally. Th e remaining circuitry of the DS1992 and DS1993 is solely operated by battery energy. 64-BIT LASERED ROM Each DS199_ contain a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 2.) The 1-Wire CRC is generated using a polynomial genera tor consisting of a shift register and XOR gates as shown in Figure 3. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-Wire Cyclic Redundancy Check is avai lable in the Book of DS19xx i Button Standards. The shift register bits are initialized to zero. Then starting with the least significant bit of the family code, 1 bit at a time is shifted in. After the 8th bit of the family code has b een entered, then the serial number is entered. After the 48th bit of the serial number ha s been entered, the shift register co ntains the CRC value. Shifting in the 8 bits of CRC should return the shift register to all zeros.
Figure 1. DS199_ BLOCK DIAGRAM
16 PAGES of 256-
4 PAGES of 256-
Figure 2. 64-BIT LASERED ROM Figure 3. 1-WIRE CRC CODE
contain pages 0 through 15 that make up the 4096-bit SRAM. transfers the data to memory. This process ensures data integrity when modifying the memory. The Memory Function Flow Chart (Figure 6) describes the protocols necessary for accessing the memory. would point to the last Byte of a page. Byte flag. Bit 6 (OF) is the overflow flag. Bit 7 (AA) is the authorization accepted flag. Figure 5. ADDRESS REGISTERS overflow has not occurred, the partial Byte flag (PF) is set. ending offset/data status Byte (E/S) followed by the scratchpad data beginning at the Byte offset (T4: T0). The user can read data until the end of the scratchpad, after which the data read is all logic 1’s.
Copy Scratchpad [55h] This command is used to copy data from the scra tchpad to memory. After issuing the copy scratchpad command, the user must provide a 3-byte authorization pattern. This pattern must exactly match the data contained in the three address regi sters (TA1, TA2, E/S, in that orde r). If the pattern matches, the AA (Authorization Accepted) flag is set and the copy begi ns. A logic 0 is transmitted after the data has been copied until the user issues a rese t pulse. Any attempt to reset the part is ignored while the copy is in progress. Copy typically takes 30μs. The data to be copied is determined by the thr ee address registers. The scratchpad data from the beginning offset through the ending offset is copied to memory, star ting at the target address. Anywhere from 1 to 32 Bytes can be copied to memory with this command. Whole Bytes are copied even if only partially written. The AA flag is cleared only by executing a write scratchpad command. Read Memory [F0h] The read memory command can be used to read the entire memory. After issuing the command, the user must provide the 2-Byte target address. After the two Bytes, the user reads data beginning from the target address and may continue until the e nd of memory, at which point logic 1’s are read. It is important to realize that the target address regi sters contains the addr ess provided. The ending offset/data status Byte is unaffected. The hardware of the DS1992/DS1993 provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simu ltaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically stor e a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple tim es to determine if the received data is correct or not. (See Application Note 114 for the recommended file structure to be used with the 1-Wire environment.)
Figure 6. MEMORY FUNCTIONS FLOW CHART
Figure 6. MEMORY FUNCTIONS FLOW CHART (Continued)
Example: Write two data Bytes to memory locations 0026h and 0027h (t he seventh and eighth Bytes of page 1). Read entire memory. MASTER MODE DATA (LSB FIRST) COMMENTS TX Reset Reset pulse (480μs to 960μs) RX Presence Presence pulse TX CCh Issue skip ROM command TX 0Fh Issue write scratchpad command TX 26h TA1, beginning offset = 6 TX 00h TA2, address = 0026h TX <2 data Bytes> Write 2 Bytes of data to scratchpad TX Reset Reset pulse RX Presence Presence pulse TX CCh Issue skip ROM command TX Aah Issue read scratchpad command RX 26h Read TA1, beginning offset = 6 RX 00h Read TA2, address = 00 26h RX 07h Read E/S, ending offset = 7, flags = 0 RX <2 data Bytes> Read scratchpad data and verify TX Reset Reset pulse RX Presence Presence pulse TX CCh Issue skip ROM command TX 55h Issue copy scratchpad command TX 26h TX 00h TX 07h TA1 TA2 AUTHORIZATION CODE E/S TX Reset Reset pulse RX Presence Presence pulse TX CCh Issue skip ROM command TX F0h Issue read memory command TX 00h TA1, beginning offset = 6 TX 00h TA2, address = 0000h RX <128 Bytes (DS1992)> <512 Bytes (DS1993)> Read entire memory TX Reset Reset pulse RX Presence Presence pulse, done
from responding in real-time. the bus is left low for more than 120μs, one or more of the devices on the bus may be reset. Figure 8. HARDWARE CONFIGURATION
slave(s). The presence pulse lets the bus master know that the DS199_ is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the four ROM function commands. All ROM function commands are 8 bits l ong. A list of these commands follows (see the flow chart in Figure 9). Read ROM [33h] This command allows the bus master to read the DS199_’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command should only be used if there is a single DS199_ on the bus. If more than one slave is present on the bus, a data col lision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). Th e resultant family code and 48-bit serial number usually result in a mismatch of the CRC. Match ROM [55h] The match ROM command, followed by a 64-bit ROM se quence, allows the bus master to address a specific DS199_ on a multidrop bus. Only the DS199_ that exactly matches the 64-bit ROM sequence will respond to the following memory function co mmand. All slaves that do not match the 64-bit ROM sequence wait for a reset pulse. This command can be used with single or multiple devices on the bus. Skip ROM [CCh] This command can save time in a single drop bus sy stem by allowing the bus master to access the memory functions without providing the 64-bit ROM c ode. If more than one slave is present on the bus and, for example, a read command is issued follow ing the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultane ously (open-drain pulldowns produce a wired-AND result). Search ROM [F0h] When a system is initially brought up, the bus master may not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The search ROM co mmand allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simp le, 3-step routine on each b it of the ROM. After one complete pass, the bus master knows the 64-bit ROM c ode of one device. Additional passes will identify the ROM codes of the remaining devices . See Chapter 5 of the Book of DS19xx i Button Standards for a comprehensive discussion of a search ROM, including an actual example. 1-WIRE SIGNALING The DS199_ require strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, and read data. The bus master initiates all these signals except presence pulse. The initialization sequence required to begin any communication with the DS199_ is shown in Figure 10. A reset pulse followed by a presence pulse indicates the DS199_ is ready to send or receive data given the correct ROM command and memory function command. The bus master transmits (Tx) a reset pulse (tRSTL, minimum 480μs). The bus master then releases the line and goes into receive mode (Rx). The 1-Wire bus is pulled to a high state through the pullup resistor. After detecting the rising edge on the data line, the DS199_ waits (tPDH, 15μs to 60μs) and then transmits the presence pulse (tPDL, 60μs to 240μs).
Figure 9. ROM FUNCTIONS FLOW CHART
6 Bytes
1 Byte
Figure 11. READ/WRITE TIMING DIAGRAM (continued)
Size See mechanical drawing Weight 3.3 grams (F5 package) Expected Service Life 10 years at +25 °C Safety Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Concept for use in Class I, Division 1, Group A, B, C and D Locations ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground -0.5V to +7.0V Operating Temperature Range -40 °C to +70°C Storage Temperature Range -40 °C to +70°C * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (-40°C to +70°C.) PARAMETER SYMBOL MIN TYP MAX UNITS 1-Wire Pullup Voltage (Notes 1, 3) VPUP 2.8 6.0 V Logic 1 (Notes 1, 2) V IH 2.2 V Logic 0 (Note 1) V IL -0.3 +0.3 V Output Logic Low at 4mA (Note 1) V OL 0.4 V Input Load Current (Note 4) IL 5 μA CAPACITANCE ( T A = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS I/O (1-Wire) (Notes 5, 6) C IN/OUT 100 800 pF AC ELECTRICAL CHARACTERISTICS (VPUP = 2.8V to 6.0V; -40°C to +70°C.) PARAMETER SYMBOL MIN TYP MAX UNITS Time Slot tSLOT 60 120 μs Write 1 Low Time tLOW1 1 15 μs Write 0 Low Time tLOW0 60 120 μs Read Data Valid tRDV exactly 15 μs Release Time tRELEASE 0 15 45 μs Read Data Setup (Note 7) tSU 1 μs Recovery Time tREC 1 μs Reset Time High (Note 8) tRSTH 480 μs Reset Time Low (Note 9) tRSTL 480 960 μs Presence Detect High tPDH 15 60 μs Presence Detect Low tPDL 60 240 μs
Note 1: All voltages are referenced to ground. Note 2: VIH is a function of the external pullup resistor and the VCC power supply. Note 3: V PUP = external pullup voltage. Note 4: Input load is to ground. Note 5: Capacitance on the data line could be 800pF when power is first applied. If a 5k Ω resistor is used to pull up the data line to VPUP, 5μs after power has been applied, the parasite capacitance does not affect normal communications. Note 6: Guaranteed by design, not production tested. Note 7: Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1μs of this falling edge, and remains valid for 14μs minimum (15μs total from falling edge on 1-Wire bus). Note 8: An additional reset or communication sequence cannot begin until the reset high time has expired. Note 9: The reset low time (t RSTL) should be restricted to a maximum of 960μs, to allow interrupt signaling; otherwise, it could mask or conceal interrupt pulses.
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
REVISION HISTORY
071508 Updated the F5 MicroCan face brand with the latest per PCN H020201. 1 Change the last sentence of the Parasite Power section to “The advantages of parasite power are two-fold: 1) by parasiting off this input, battery power is not consumed for 1-Wire ROM function commands, and 2) if the battery is exhausted for any reason, the ROM may still be read normally. The remaining circuitry of the DS1992 and DS1993 is solely operated by battery energy.” 101408 In the DC Electrical Characteristics section, relocated VPUP from the header to the EC table, changed VILMAX from 0.8V to 0.3V, and removed the VOH parameter for the 1-Wire pin.