DS1977 MAXIM | Alldatasheet
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19-4890; 11/09 DS1977 Password-Protected 32KB EEPROM i 1 of 29 iButton DESCRIPTION The DS1977 is a 32KB EEPROM in a rugged, iButton® enclosure. Access to the memory can be password-protected with different passwords for read-only and full access. Data is transferred serially through the 1-Wire ® protocol, which requires only a single data lead and a ground return. Every DS1977 is factory lasered with a guaranteed unique 64-bit registration number that allows for absolute traceability. The dura ble stainless-steel i Button package is highly resistant to environmental hazards such as dirt, moisture, and shock. Accessories permit the DS1977 i Button to be mounted on almost any object, including containers, pallets, and bags.
APPLICATIONS
Maintenance/Inspection Data Storage Medical Data Carrier Health Data Carrier Audit Data Storage and Carrier F5 MicroCAN IO GND 0.51 5.89 16.25 17.35FC 37 000000FBC52B 1-Wire All dimensions are shown in millimeters. SPECIAL FEATURES 32KB EEPROM Organized as Pages of 64 Bytes Each Optional Password Protection with Different 64- Bit Passwords for Read and Full Access Communicates to Host with a Single Digital Signal at Up to 15.3kbps at Standard Speed or Up to 125kbps in Overdrive Mode Using 1-Wire Protocol Operating Range: 2.8V to 5.25V, -40 C to +85C Minimum 100k Write Cycles Endurance 15kV Built-in ESD Protection COMMON iButton FEATURES Unique Factory-Lasered 64-Bit Registration Number Assures Error-Free Device Selection and Absolute Traceability Because No Two Parts are Alike Built-In Multidrop Controller for 1-Wire Net Chip-Based Data Carrier Stores Digital Identification and Information, Armored in a Durable Stainless-Steel Case Data can be Accessed While Affixed to Object Button Shape is Self-Aligning with Cup-Shaped Probes Easily Affixed with Self-Stick Adhesive Backing, Latched by its Flange, or Locked with a Ring Pressed onto its Rim Presence Detector Acknowledges when Reader First Applies Voltage
ORDERING INFORMATION
DS1977-F5# -40C to +85C F5 iButton #Denotes an RoHS-compliant device that may include lead(Pb) that is exempt under the RoHS requirements. EXAMPLES OF ACCESSORIES PART DESCRIPTION DS9096P Self-Stick Adhesive Pad DS9101 Multipurpose Clip DS9093RA Mounting Lock Ring DS9093A Snap-In Fob DS9092 i Button Probe Button www.maxim-ic.com iButton and 1-Wire are registered trademarks of Maxim Integrated Products, Inc.
Size See mechanical drawing Weight DS1977 Ca. 3.3g ABSOLUTE MAXIMUM RATINGS I/O Voltage to GND -0.3V, +5.5V I/O Sink Current 20mA Junction Temperature +150°C Storage Temperature Range -40°C to +85°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
ELECTRICAL CHARACTERISTICS
(VPUP = 2.8V to 5.25V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I/O Pin General Data 1-Wire Pullup Resistance RPUP (Notes 1, 2) 0.6 2.2 k Input Capacitance CIO (Note 3) 5 nF Input Load Current IL I/O pin at VPUP 1 10 µA High-to-Low Switching Threshold VTL (Notes 4, 5) 0.5 3.2 V Input Low Voltage VIL (Notes 1, 6) 0.30 V Low-to-High Switching Threshold VTH (Notes 4, 7) 0.7 3.4 V Switching Hysteresis VHY (Note 8) 0.15 N/A V Output-Low Voltage at 4mA VOL (Note 9) 0.4 V Standard speed, RPUP= 2.2k (Note 1) 5 Overdrive speed, RPUP= 2.2k (Note 1) 2 Recovery Time tREC Overdrive speed, directly prior to reset pulse; RPUP= 2.2k (Note 1) µs Standard speed (Note 10) 0.5 5 Rising-Edge Hold-off Time tREH Overdrive speed (Note 10) 0.5 2 µs Standard speed (Note 1) 65 Timeslot Duration tSLOT Overdrive speed (Note 1) 8 µs I/O Pin, 1-Wire Reset, Presence Detect Cycle Standard speed (Note 1) 480 640 Reset Low Time tRSTL Overdrive Speed (Note 1) 48 80 µs Standard speed (Note 11) 15 60 Presence Detect High Time tPDH Overdrive speed (Note 11) 2.5 6.5 µs Standard speed, VPUP > 4.5V (Note 12) 1.5 5 Standard speed (Note 12) 1.5 8 Presence Detect Fall Time t FPD Overdrive speed (Note 12) 0.15 1 µs Standard speed 60 240 Presence Detect Low Time t PDL Overdrive speed 8 24 µs
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Standard speed, VPUP > 4.5V (Note 1) 65 75 Standard speed (Note 1) 68 75 Presence Detect Sample Time tMSP Overdrive speed (Note 1) 7.5 10.5 µs I/O Pin, 1-Wire Write Standard speed (Notes 1, 13) 60 120 Write-0 Low Time tW0L Overdrive speed (Notes 1, 13) 6 16 µs Standard speed (Notes 1, 13) 5 15 Write-1 Low Time tW1L Overdrive speed (Notes 1, 13) 1 2 µs I/O Pin, 1-Wire Read Standard speed (Notes 1, 14) 5 15 - Read Low Time tRL Overdrive speed (Notes 1, 14) 1 2 - µs Standard speed, VPUP > 4.5V (Notes 1, 14) tRL + 20 Standard speed (Notes 1, 14) tRL + 15 Read Sample Time tMSR Overdrive speed (Notes 1, 14) tRL + 2 µs I/O Pin, Strong Pullup Strong Pullup Read tSPUR (Note 1) 2.64 ms Strong Pullup Write tSPUW (Note 1) 22.46 ms Strong Pullup password verification tSPUV (Note 1) 0.62 ms EEPROM Programming Current ILPROG 7 mA Write/Erase Cycles NCYCLE 100k — Data Retention tRET 10 years Note 1: System requirement. Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required. Note 3: Capacitance on the data pin could be 5nF when power is first applied. Note 4: VTL and VTH are functions of the internal supply voltage, which is a function of VPUP and the 1-Wire recovery times. The VTH and VTL maximum specifications are valid at VPUPMAX (5.25V). In any case, VTL < VTH < VPUP. Note 5: Voltage below which, during a falling edge on I/O, a logic '0' is detected. Note 6: The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line low. Note 7: Voltage above which, during a rising edge on I/O, a logic '1' is detected. Note 8: After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to be detected as logic '0'. Note 9: The I-V characteristic is linear for voltages less than 1V. Note 10: The earliest recognition of a negative edge is possible at tREH after VTH has been reached before. Note 11: Highlighted numbers are NOT in compliance with the published iButton standards. See comparison table below. Note 12: Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of VPUP. Note 13: in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - and tW0LMAX + tF - respectively. Note 14: in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. Standard Values DS1977 Values Standard Speed Overdrive Speed Standard Speed Overdrive Speed Parameter Name min max min max min max min max tRSTL 480µs (undef.) 48µs 80µs 480µs 640µs 48µs 80µs tPDH 15µs 60µs 2µs 6µs 15µs 60µs 2.5µs 6.5µs tPDL 60µs 240µs 8µs 24µs 60µs 240µs 8µs 24µs tW0L 60µs 120µs 6µs 16µs 60µs 120µs 6µs 16µs 1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.
processing. Software for communication with the DS1977 is available for free download from the iButton website. 32KB EEPROM, and 4) two password buffers. The passwords can only be written and verified, but never be read. described in Figure 7. All data is read and written least significant bit first. Figure 1. DS1977 BLOCK DIAGRAM
This password only applies to the function "Read Memory with Password”. If passwords are enabled (EPW = AAh, see Password Control register), the 64-bit data pattern t hat the 1-Wire master has to transmit with the command flow is compared to the passwords stored in the DS1977 i Button. The DS1977 delivers the requested data only if the password transmitted by the master was correct or if password checking is not enabled. Read Access Password Register ADDR b7 b6 b5 b4 b3 b2 b1 b0 7FC0h RP7 RP6 RP5 RP 4 RP3 RP2 RP1 RP0 7FC1h RP15 RP14 RP13 RP 12 RP11 RP10 RP9 RP8 — — — 7FC6h RP55 RP54 RP53 RP 52 RP51 RP50 RP49 RP48 7FC7h RP63 RP62 RP61 RP 60 RP59 RP58 RP57 RP56 There is only write access to this register. The Read Access Password needs to be transmitted exactly in the sequence RP0, RP1… RP62, RP63. Full Access Password This password applies to the functions "Read Memory with Password” and "Copy Scratchpad with Password”. If passwords are enabled (EPW = AAh, see Password Control register), the 64-bit data pattern that the 1-Wire master has to transmit with the command flow is compared to the passwords stored in the DS1977 i Button. The DS1977 executes the command only if the password transmitted by the master was correct or if password checking is not enabled. Full Access Password Register ADDR b7 b6 b5 b4 b3 b2 b1 b0 7FC8h FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 7FC9h FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 — — — 7FCEh FP55 FP54 FP53 FP52 FP51 FP50 FP49 FP48 7FCFh FP63 FP62 FP61 FP60 FP59 FP58 FP57 FP56 There is only write access to this register. The Full Access Password needs to be transmitted exactly in the sequence FP0, FP1… FP62, FP63. Password Control Register The data pattern stored in the Password Control Register determines whether password checking is enabled. If password checking is enabled, the password transmitted is compared to the passwords stored in the device. Reading from or writing to the scratchpad does not require a password. Password Control Register Bitmap ADDR b7 b6 b5 b4 b3 b2 b1 b0 7FD0h EPW Register Details BIT DESCRIPTION BIT(S) DEFINITION EPW: Enable Passwords b0 to b7 This byte enables or disables the password protection, which applies to reading from and writing to the memory except for the scratchpad. If the EPW bits form a pattern of 10101010 (AAh), the device will execute these commands only if the correct password is transmitted. The default pattern of EPW is different from AAh. To enable password checking, the EPW bits need to form a binary pattern of 10101010 (AAh). If the EPW pattern is different from AAh, any password will be accepted, as l ong as it has a length of exactly 64 bits. Before enabling
current full-access password. automatically use the appropriate software driver in case of different logical behavior. Bits 0 to 4 have no function. They always read 0. (N/A) b0 to b4 These bits are all 0. Figure 6. ADDRESS REGISTERS
To write data to the DS1977 , the scratchpad has to be used as intermediate storage. First the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. Under certain conditions (see Write Scratchpad command) the ma ster will receive an inverted CRC16 of the command, address and data at the end of the write scratchpad command sequence. Knowing this CRC value, the master can compare it to the value it has calculated itself to decide whether the communication was successful and proceed to the Copy Scratchpad command. If the master could not receive the CRC16, it has to send the Read Scratchpad command to read back the scratc hpad to verify data integrity. As preamble to the scratchpad data, the DS1977 repeats the target address TA1 and TA2 and sends the cont ents of the E/S register. If the PF flag is set, data did not arrive correctly in the sc ratchpad or there was a loss of power since data was last written to the scratchpad. The master does not need to cont inue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag together with a clea red PF flag indicates that the Write command was not recognized by the device. If everything went correctly, both flags are clea red and the ending offset indicates the address of the last byte written to t he scratchpad; the master can continue reading and verifying every data byte. After the master has verified the data, it has to se nd the Copy Scratchpad command. This command must be followed exactly by the data of the three address registers TA1, TA2, and E/S. The master may obtain the contents of these registers by reading the scratchpad or derive it from the target address and the amount of data to be written. As soon as the DS1977 has received these bytes correctly and t he master has provided an acceptable password, the DS1977 will copy the scratchpad data to the requested location beginning at the target address. MEMORY FUNCTION COMMANDS The “Memory Function Flow Chart” (Figure 7) describes the protocols necessary for accessing the memory and the special function registers of the DS19 77. Examples on how to use these functions to operate the DS1977 are included at the end of this document, preceding the Electr ical Characteristics section. The communication between master and DS1977 takes place either at standard speed (default, OD = 0) or at Overdrive Speed (OD = 1). If not explicitly set into the Overdrive mode the DS1977 assumes regular speed. Write Scratchpad Command [0Fh] This command is used to specify the target address and to write data to the scratchpad for verification before the transfer to the EEPROM can be initiated. After issuing the write scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scr atchpad. The data will be written to the scratchpad starting at the byte offset (T5:T0). The ending offset (E5: E0) will be the byte offset at which the master stops writing data. Only full data bytes ar e accepted. If the last data byte is incomplete its content will be ignored and the partial byte flag PF will be set. When writing to a pa ssword address, internal circuitry of the chip will force the 3 least significant address bits to 0. Only full 8-byte passwords are accepted. The ending offset will be 07 or 0F, depending on the password(s) to be changed. When executing the Write Scratchpad command the CRC g enerator inside the DS1977 (Figure 13) calculates an inverted CRC over the entire data stream, starting at the command code and ending at the last data byte sent by the master. This CRC is generated using the CRC16 pol ynomial by first clearing the CRC generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target Addresses TA1 and TA2 as supplied by the master and all the data bytes. The ma ster may end the Write Scratchpad command at any time. However, if the ending offset is 3Fh, the master ma y send 16 read-time slots and will receive the CRC generated by the DS1977 . The memory address range of the DS1977 is 0000h to 7 FFFh (Figure 5). There is no user-access to the address range 7FD1h to 7FFFh. If the master sends a target address higher than this, the internal circuitry of the chip will set the most significant address bit to zero as it is sh ifted into the internal address register. The Read Scratchpad command will reveal the target address as it will be used by the DS1977 . The master will identify such address modifications by comparing the target address read back to the target address transmitted. If the master does not read the scratchpad, a subsequent copy scratchpad command will not work since the most significant bits of the target address the master sends will not match the value the DS1977 expects. Read Scratchpad Command [AAh] This command is used to verify scratchpad data and target address. After issuing the Read Scratchpad command, the master begins reading. The first 2 bytes will be the target address. The next byte will be the ending offset/data status byte (E/S) followed by the scr atchpad data beginning at the byte offs et (T5:T0), as shown in Figure 6.
Regardless of the actual ending offset the master may continue reading data until t he end of the scratchpad after which it will receive an inverted CRC16 of the command co de, Target Addresses TA1 and TA2, the E/S byte, and the scratchpad data starting at the byte offset, which is determined by the target addr ess. After the CRC is read, the bus master will read logical 1s from the DS1977 until a reset pulse is issued. Copy Scratchpad with Password [99h] This command is used to transfer data from the scra tchpad to the memory. After issuing the copy scratchpad command, the master must provide a 3-byte author ization pattern, which can be obtained by reading the scratchpad for verification. This pattern must exactly matc h the data contained in the three address registers (TA1, TA2, E/S, in that order). Next the master must send a valid full-access password, or, if passwords are not enabled, 8 dummy bytes. Now the master must provide power by bypassing the 1-Wire pullup resistor with an electronic switch, generating a "strong pullup". If authorization pa ttern and password are accepted, the AA (Authorization Accepted) flag will be set and the copy will begin. Copy takes 10ms maximum during which the voltage on the 1- Wire bus must not fall below 2.8V. After the copy is co mpleted, the master turns off the strong pullup and begins reading from the 1-Wire. A pattern of alternating 1’s and 0’s will indicate that the copy command was executed successfully. If the copy command was disturbed due to lack of power or for other reasons (see Figure 7-2, "strong pullup valid?"), the master will read a co nstant stream of FFh bytes until it sends a 1-Wire reset pulse. In this case the destination memory may be incompletely programme d requiring a write scratchpad and copy scratchpad be repeated to ensure proper programmi ng of the EEPROM. This requires care ful consideration when designing application software that writes to the DS1977 in an intermittent contact environment. The data to be copied is determined by the three address registers (TA1, TA2, E/S). The scratchpad data from the beginning offset through the ending offset will be copied to memory, starting at the target address. Anywhere from 1 to 64 bytes may be copied to memory with this command. Read Memory with Password [69h] This command is used to read the entire memory, except for the passwords. After issuing the command, the master must provide the 2-byte target address. Next t he master must send a valid read access password, or, if passwords are not enabled, 8 dummy bytes. Now the master must provide power by bypassing the 1-Wire pullup resistor with an electronic switch, generating a "s trong pullup". If the password was accepted, EEPROM data beginning at the specified target address and ending at the page boundary will be loaded into the scratchpad starting at the beginning offset. This transfer takes 5 ms maximum during which the voltage on the 1-Wire bus must not fall below 2.8V. After the transfer is completed, the master turns off the strong pullup and begins reading from the 1-Wire. When the end of the memory page (end of scratchpad) is reached , the master will re ceive an inverted CRC16 of the command, target address and page data. If t he master wants to read more data and the end of the memory is not yet reached, it again has to activate the strong pullup. This will tran sfer a full 64-byte page of memory data to the scratchpad from where the master can re ad it by issuing read-time slots. This transfer only takes place if the DS1977 receives enough power through t he 1-Wire line (see Figure 7-3, "strong pullup valid?"). The loop of strong pullup and reading 64 bytes can be repeated until the end of the memory is reached, at which point the master will read logic 1's. Verify Password [C3h] This command allows the user to verify whether the process of updating a password was successful, eliminating the risk of a weak programming of the memory cells t hat actually store the password. The command allows verifying one password at a time. After issuing the comm and code, the master must send the memory address of the password to be verified. Next the master transmits the password itself and generates a strong pullup to provide the power for the password comparison. This takes 5ms maximum, during which the voltage on the 1-Wire bus must not fall below 2.8V. After the comparison is comp leted, the master turns off the strong pullup and begins reading from the 1-Wire line. A pattern of alternating 1's and 0's indicates that the verification was successful, i. e., the password supplied by the master matches the one st ored in the DS1977. If the passwords do not match, the master will read a constant stream of FFh bytes until it sends a reset pulse. Before changing a password, first disable the use of passwords. Then using Write Scratchpad, Read Scratchpad and Copy Scratchpad, write the new password to its resp ective memory location. Now use Verify Password to double-check whether the password reads correctly from t he EEPROM memory. If the verification is successful, it is safe to again enable passwords.
Figure 7-1. MEMORY/CONTROL FUNCTION FLOW CHART N Master TX Memory Function Command 0Fh Write Scratchpad Master TX TA1 (T7:T0), TA2 (T15:T8) DS1977 sets Scratch- pad Offset = (T5:T0) and Clears (PF, AA) Master TX Data Byte to Scratchpad Offset DS1977 sets (E5:E0) = Scratchpad Offset Master TX Reset? Scratch- pad Offset = 3Fh? Master RX CRC16 of Command, Address Data DS1977 Incre- ments Scratch- pad Offset Master RX "1"s Master TX Reset? Master TX Reset? Partial Byte Written? PF = 1 AAh Read Scratchpad Master RX TA1 (T7:T0) Master RX TA2 (T15:T8) Master RX Ending Offset with Data Status (E/S) Master TX Reset? Scratch- pad Offset = 3Fh? Master RX CRC16 of Command, Address Data, E/S Byte, and Data Starting at the Target Address DS1977 Incre- ments Scratch- pad Offset Master RX "1"s Master TX Reset? DS1977 sets Scratch- pad Offset = (T5:T0) Master RX Data Byte from Scratchpad Offset From ROM Functions Flow Chart (Figure 9) To ROM Functions Flow Chart (Figure 9) N Y N Y N Y N Y N Y N Y N Y N Y N Y N Y Address of Password? DS1977 sets Scratchpad Offset = (T5:T3,0,0,0) and Clears (PF, AA, T2:T0) Y Master TX one or both 8-byte passwords To Figure 7 nd Part From Figure 7 nd Part
Figure 7-2. MEMORY/CONTROL FUNCTION FLOW CHART 99h Copy Scrpad. [w/PW] Master TX E/S Byte Authorization Code Match? DS1977 Copies Scratchpad Data or Data from Password Holding Register (if Password Address) to Memory Strong Pull- up Valid? Master TX Reset? AA = 1 Master TX TA1 (T7:T0), TA2 (T15:T8) Master TX 64-Bits [Password] Password Accepted? DS1977 TX "0" DS1977 TX "1" Master TX Reset? N Y N Y N Y Y N Master TX Reset? Master RX "1"s N Y N Y N Y Authorization Code Master Activates Strong Pullup N Address of Password? Y Read- Access Passw.? Save to Read Password Holding Register YN Save to Full- Access Password Holding Register More data in SP? Y N To Figure 7 3rd Part From Figure 7 3rd Part From Figure 7 1st Part To Figure 7 st Part NOTE: The strong pullup must be activated within 40µs after the last bit of the password is transmitted. Pullup duration: see t SPUW
Figure 7-3. MEMORY/CONTROL FUNCTION FLOW CHART 69h Read Mem. [w/PW] Master TX 64-Bits [Password] Master TX Reset? CRC OK? Master RX "1"s DS1977 sets Memory Address = (T15:T0) Master RX Data Byte from Memory Address or FFh if Password Address Master TX TA1 (T7:T0), TA2 (T15:T8) Password Accepted? DS1977 Incre- ments Address Counter End of Page? Master RX CRC16 of Command, Address, Data st Pass); CRC16 of Data (Subsequent Passes) End of Memory? Master TX Reset N Y N Y N Y N Y N Y N Y N Y Decision made by DS1977 Decision made by Master Master Activates Strong Pullup DS1977 Incre- ments Address Counter Master Activates Strong Pullup Strong pull- up valid? Y N Master TX Reset? To Figure 7 th Part From Figure 7 th Part From Figure 7 nd Part To Figure 7 nd Part NOTE: The strong pullup must be activated within 40µs after the last bit of the password is transmitted. Pullup duration: see t SPUR To continue reading the next memory page, the strong pullup must be activated within 40µs after the last bit of the CRC16 is read. See Note
Figure 7-4. MEMORY/CONTROL FUNCTION FLOW CHART Master TX TA1 (T7:T0), TA2 (T15:T8) C3h Verify Password N Y N Y Master TX Password to verify DS1977 sets Memory Address = (T15:T3, 0, 0, 0) Password Match? N Y Master Activates Strong Pullup Master TX Reset? Address of Password? Y N Master RX AAh byte Master RX FFh byte N Y Master TX Reset? From Figure 7 3rd Part To Figure 7 3rd Part CCh Read Version Y N Master TX two bytes 00h Master RX two copies of Version Register NOTE: The strong pullup must be activated within 40µs after the last bit of the password is transmitted. Pullup duration: see t SPUV
Read Version Command [CCh] This command allows the master to read the chip revi sion code of the DS1977. After issuing the command code, the master sends two 00h-bytes to access the version regist er. With the next 16 time slots the master receives two copies of the content of the version re gister. Additional read-time slots will read logic 1's. Only t he upper 3 bits of the version register are valid. The lower 5 bits will all read 0. 1-Wire BUS SYSTEM The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the DS1977 is a slave device. The bus master is typically a microcon troller or PC. For small configurations the 1-Wire communication signals can be generated under software control using a single port pin. A second port pin is required to control the strong pullup to supply power for the commands Copy Scratchpad with Password, Read Memory with Password and Verify Password. Alternatively, the DS2480B 1-Wi re line driver chip or serial port adapters based on this chip (DS9097U series) are can be used. This simplifies the hardware design and frees the microprocessor from responding in real-time. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire pr otocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards. HARDWARE CONFIGURATION The 1-Wire bus has only a single line by definition; it is impo rtant that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attach ed to the 1-Wire bus must have open drain or tri-state outputs. The 1-Wire port of the DS1977 is open-drain with an internal circuit equivalent to that shown in Figure 8. A multi-drop bus consists of a 1-Wire bus with multiple slaves attached. At standar d speed the 1-Wire bus has a maximum data rate of 15.3 kbits per second. The speed can be boosted to 125 kbits per second by activating the Overdrive mode. The value of the pullup resistor primar ily depends on the network size and load conditions. For most applications the optimal value of the pullup resistor will be approximately 2.2k for standard speed and 1.5k for Overdrive speed. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs (Overdrive speed) or more than 120µs (standard speed), one or more devices on the bus may be reset. TRANSACTION SEQUENCE The protocol for accessing the DS1977 through the 1-Wire port is as follows: Initialization ROM Function Command Memory Function Command Transaction/Data Illustrations of the transaction sequence for the various memory function commands are found later in this document. INITIALIZATION All transactions on the 1-Wire bus begin with an initializat ion sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presen ce pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS1977 is on t he bus and is ready to operate. For more details, see the 1- Wire Signaling section. 1-Wire ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can is sue one of the eight ROM function commands. All ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure 9).
Figure 8. HARDWARE CONFIGURATION AND result). The resultant family code and 48-bit serial number will result in a mismatch of the CRC. pulse. This command can be used with a single or multiple devices on the bus. transmit simultaneously (open drain pulldowns will produce a wired-AND result).
Figure 9-1. ROM FUNCTIONS FLOW CHART From Figure 9 nd PartTo Memory Functions Flow Chart (Figure 7) Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 Bit 63 Match ? RC = 0 DS1977 TX Bit 0 DS1977 TX Bit 0 Master TX Bit 0 DS1977 TX Bit 1 DS1977 TX Bit 1 Master TX Bit 1 DS1977 TX Bit 63 DS1977 TX Bit 63 Master TX Bit 63 RC = 1 Bit 1 Match ? Bit 0 Match ? Y N Y N Y NBit 63 Match ? RC = 0 RC = 1 Bit 1 Match ? Bit 0 Match ? Y N Y N Y N RC = 0 DS1977 TX CRC Byte DS1977 TX Serial Number (6 Bytes) DS1977 TX Family Code (1 Byte) RC = 0 To Figure 9 nd PartNF0h Search ROM Command ? N55h Match ROM Command ? N CCh Skip ROM Command ? YY YY N33h Read ROM Command ? To Figure 9 nd Part From Memory Functions Flow Chart (Figure 9) Bus Master TX ROM Function Command DS1977 TX Presence Pulse OD Reset Pulse ? N Y OD = 0 Bus Master TX Reset Pulse From Figure 9, 2 nd Part
Figure 9-2. ROM FUNCTIONS FLOW CHART To Figure 9 1st Part From Figure 9 1st Part From Figure 9 1st Part To Figure 9, 1st Part Y NA5h Resume Command ? RC = 1 ? Y N3Ch Overdrive Skip ROM ? RC = 0 ; OD = 1 Master TX Reset ? Y N N Y Master TX Reset ? N Y Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 Bit 63 Match ? RC = 0 ; OD = 1 RC = 1 Bit 1 Match ? Y N Y N Bit 0 Match ? Y N Y N69h Overdrive Match ROM ?
RESUME COMMAND [A5h] The Resume Command function maximizes the data throughput in a multidrop environment. This function checks the status of the RC bit and, if it is set, directly transfers control to the Memory/Control functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM or Overdrive Match ROM command. Once the RC bit is se t, the device can repeatedly be accessed through the Resume Command function. Accessing another device on the bus will cl ear the RC bit, prev enting two or more devices from simultaneously responding to the Resume Command function. OVERDRIVE SKIP ROM [3CH] On a single-drop bus this command can save time by a llowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the norm al Skip ROM command, the Overdrive Skip ROM sets the DS1977 in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a reset pulse of minimum 480µs duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus this command will set a ll Overdrive-supporting devices into Overdrive mode. To subsequently address a specific Overdr ive-supporting device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This will speed up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a Read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). OVERDRIVE MATCH ROM [69H] The Overdrive Match ROM command followed by a 64-bit RO M sequence transmitted at Overdrive Speed allows the bus master to address a specific DS1977 on a multidro p bus and to simultaneously set it in Overdrive mode. Only the DS1977 that exactly matches the 64-bit ROM se quence will respond to the subsequent memory function command. Slaves already in Overdrive mode from a previo us Overdrive Skip or Match command will remain in Overdrive mode. All overdriv e-capable slaves will return to standard speed at the next Reset Pulse of minimum 480µs duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus. 1-Wire SIGNALING The DS1977 requires strict protocols to ensure data integrity. The protocol consists of five types of signaling on one line: Reset Sequence with Reset Pulse and Presence Puls e, Write-Zero, Write-One Read-Data, and strong pullup to supply power over the 1-Wire line. Ex cept for the presence pulse the bus ma ster initiates all these signals. The DS1977 can communicate at two differ ent speeds, standard speed and Overdrive Speed. If not explicitly set into the Overdrive mode, the DS1977 will co mmunicate at standard speed. While in Overdrive mode the fast timing applies to all waveforms. To get from idle to active, the voltage on the 1-Wire line needs to fall from V PUP below the threshold V TL. To get from active to idle, the voltage needs to rise from V ILMAX past the threshold V TH. The time it takes for the voltage to make this rise, in Figure 10 as , and its duration depends on the pullup re sistor (RPUP) used and capacitance of the 1-Wire network attached. The voltage V ILMAX is relevant for the DS1977 when determining a logical level, not triggering any events. The initialization sequence required to begin any communi cation with the DS1977 is shown in Figure 10. A Reset Pulse followed by a Presence Pulse indicates the DS1977 is ready to receive data, given the correct ROM and memory function command. If the bus master uses slew-rat e control on the falling edge, it must pull down the line for t RSTL + tF to compensate for the edge. A t RSTL duration of 480µs or longer will exit the Overdrive mode returning the device to standard speed. If t he DS1977 is in Overdrive Mode and t RSTL is no longer than 80µs the device will remain in Overdrive mode.
Figure 11. READ/WRITE TIMING DIAGRAM (continued) data line low; its internal timing generator determines wh en this pulldown ends and the voltage starts rising again. recovery time tREC for the DS1977 to get ready for the next time slot. The 1-Wire front end of the DS1977 differs from traditional slave devices in four characteristics.
which has different values for standard and Overdrive speed. 2) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed. below VTH - VHY, it will not be recognized (Figure 12, Case A). The hysteresis is effective at any 1-Wire speed. out and will be taken as beginning of a new time slot (Figure 12, Case C, tGL tREH). Figure 12. NOISE SUPPRESSION SCHEME received in the true (non-inverted) form. It is computed at the factory and lasered into the ROM. CRC that is the result of clearing the CRC generator and then shifting in the data bytes. location within the scratchpad. regardless of the actual ending offset. For more information on generating CRC values see Application Note 27.
Figure 13. CRC16 HARDWARE DESCRIPTION AND POLYNOMIAL
COMMAND-SPECIFIC 1-WIRE COMMUNICATION PROTOCOL—COLOR CODES Master to slave Slave to master Strong Pullup WRITE SCRATCHPAD, REACHING THE END OF THE SCRATCHPAD (CANNOT FAIL) RST PD Select WS TA <data to EOS> CRC16\\ FF loop WRITE SCRATCHPAD, NOT REACHING THE END OF THE SCRATCHPAD (CANNOT FAIL) RST PD Select WS TA <data> RST PD READ SCRATCHPAD (CANNOT FAIL) RST PD Select RS TA-E/S <data to EOS> CRC16\\ FF loop COPY SCRATCHPAD WITH PASSWORD (SUCCESS) RST PD Select CPS TA-E/S <PW/dummy> Strong Pullup AA loop COPY SCRATCHPAD WITH PASSWORD (FAIL TA-E/S OR PASSWORD) RST PD Select CPS TA-E/S <PW/dummy> Strong Pullup FF loop READ MEMORY WITH PASSWORD (SUCCESS) RST PD Select RM TA <PW/dummy> Strong Pullup <data to EOP> CRC16\\ Strong Pullup <64 bytes> CRC16\\ FF loop READ MEMORY WITH PASSWORD (FAIL PASSWORD) Loop RST PD Select RM TA <PW/dummy> Strong Pullup FF loop
VERIFY PASSWORD (SUCCESS) RST PD Select VP TA Password Strong Pullup AA loop VERIFY PASSWORD (FAIL ADDRESS OR PASSWORD) RST PD Select VP TA Password Strong Pullup FF loop READ VERSION (CANNOT FAIL) RST PD Select RV 00h 00h Version Version FF loop COMMUNICATION EXAMPLES The examples in this section demonstrate the use of the memory functions in typical situations. The first example shows how to read the ROM and the version register. In t he second example, passwords are installed. The third example shows how to write a couple of bytes and how to read adjacent memory pages. EXAMPLE 1 Task: Read the ROM and the version register With only a single DS1977 connected to the bus master, the communication is as follows: MASTER MODE DATA (LSB FIRST) COMMENTS TX (Reset) Reset Pulse RX (Presence) Presence Pulse TX 33h Issue Read ROM Command RX <8 Bytes ROM ID> Read ROM ID TX CCh Issue Read Version Register Command TX 00h, 00h Write Two 00h Bytes RX <Version>, <Version> Read Chip Version Code Twice RX FFh Additional Reads Result in FFh Bytes TX (Reset) Reset Pulse RX (Presence) Presence pulse EXAMPLE 2 Task: Install and activate passwords; passwords are currently not activated This task is broken into the following steps: 1. Write new passwords to scratchpad 2. Read Scratchpad 3. Copy scratchpad 4. Verify new passwords 5. Activate password
With only a single DS1977 connected to the bus master, the communication is as follows: MASTER MODE DATA (LSB FIRST) COMMENTS Step 1 TX (Reset) Reset Pulse RX (Presence) Presence Pulse TX CCh Issue Skip ROM Command TX 0Fh Issue Write Scratchpad Command TX C0h TA1, Target Address = C0h (Password Start Address) TX 7Fh TA2, Target Address = 7FC0h TX <Read Password> Write 8-Byte Read Password to Scratchpad TX <Full-Access Password> Write 8-Byte Full-Access Password to Scratchpad TX (Reset) Reset Pulse RX (Presence) Presence Pulse Step 2 TX CCh Issue Skip ROM Command TX AAh Issue Read Scratchpad Command RX C0h Read TA1, Target Address = C0h RX 7Fh Read TA2, Target Address = 7FC0h RX 0Fh Read E/S-Byte RX <16 Bytes> Read Both Passwords from Scratchpad and Compare to what was Written TX (Reset) Reset Pulse RX (Presence) Presence Pulse Step 3 TX CCh Issue Skip ROM Command TX 99h Issue Copy Scratchpad with Password Command TX C0h TA1, Target Address = C0h TX 7Fh TA2, Target Address = 7FC0h TX 0Fh E/S-byte TX <8 Bytes> Transmit 8 Dummy Bytes as Password, Because Passwords are Not Yet Enabled (—) (Activate Strong Pullup for tPROG) Supply Power for Programming RX AAh Read to Check for Programming Success; AAh Means Success TX (Reset) Reset Pulse RX (Presence) Presence Pulse Step 4 TX CCh Issue Skip ROM Command TX C3h Issue Verify Password Command TX C0h TA1, Target Address = C0h (Read Password Address) TX 7Fh TA2, target address = 7FC0h TX <Read Password> Transmit Read Password (—) (Activate Strong Pullup for tPROG) Supply Power for Password Comparison RX AAh Check for Password Match; AAh = Match TX (Reset) Reset Pulse RX (Presence) Presence Pulse TX CCh Issue Skip ROM Command TX C3h Issue Verify Password Command TX C8h TA1, Target Address = C8h (Full-Access
MASTER MODE DATA (LSB FIRST) COMMENTS Password Address) TX 7Fh TA2, Target Address = 7FC8h TX <Full-Access Password> Transmit Full-Access Password (—) (Activate Strong Pullup for tPROG) Supply Power for Password Comparison RX AAh Check for Password Match; AAh = Match TX (Reset) Reset Pulse RX (Presence) Presence Pulse Step 5 TX CCh Issue Skip ROM Command TX 0Fh Issue Write Scratchpad Command TX D0h TA1, Target Address = D0h (Password Control Register Address) TX 7Fh TA2, Target Address = 7FD0h TX AAh Write Password Enabling Pattern TX (Reset) Reset Pulse RX (Presence) Presence Pulse TX CCh Issue Skip ROM Command TX AAh Issue Read Scratchpad Command RX D0h Read TA1, Target Address = D0h RX 7Fh Read TA2, Target Address = 7FD0h RX 10h Read E/S-Byte RX AAh Verify Password Enabling Pattern TX (Reset) Reset Pulse RX (Presence) Presence Pulse TX CCh Issue Skip ROM Command TX 99h Issue Copy Scratchpad with Password Command TX D0h TA1, Target Address = D0h TX 7Fh TA2, Target Address = 7FD0h TX 10h E/S-Byte TX <8 Bytes> Transmit 8 Dummy Bytes as Password, Because Passwords are Not Yet Enabled (—) (Activate Strong Pullup for tPROG) Supply Power for Programming RX AAh Read to Check for Programming Success; AAh Means Success TX (Reset) Reset Pulse RX (Presence) Presence Pulse Instead of always using Skip ROM, one could use Read ROM first to learn the device's ROM identification (see Example 1). For the next access one would use the Match ROM command and send the correct ROM identification to address the device. Subsequent accesses could use the Resume command. This procedure ensures that devices cannot be swapped during a communication session. EXAMPLE 3 Task: write 10 data bytes starting at address 00A0h in page 2; read memory pages 2 and 3. The device has passwords installed and activated. This task is broken into the following steps: 1. Write data to scratchpad 2. Read Scratchpad 3. Copy scratchpad 4. Read the entire memory page 3 5. Continue reading through the end of page 4
With only a single DS1977 connected to the bus master, the communication is as follows: MASTER MODE DATA (LSB FIRST) COMMENTS Step 1 TX (Reset) Reset Pulse RX (Presence) Presence Pulse TX CCh Issue Skip ROM Command TX 0Fh Issue Write Scratchpad Command TX A0h TA1, Target Address = A0h (Start Address) TX 00h TA2, Target Address = 00A0h TX <10 Data Bytes> Write Data Bytes to Scratchpad TX (Reset) Reset Pulse RX (Presence) Presence Pulse Step 2 TX CCh Issue Skip ROM Command TX AAh Issue Read Scratchpad Command RX A0h Read TA1, Target Address = A0h RX 00h Read TA2, Target Address = 00A0h RX 29h Read E/S-Byte RX <10 Bytes> Read from Scratchpad and Compare to what was Written TX (Reset) Reset Pulse RX (Presence) Presence Pulse Step 3 TX CCh Issue Skip ROM Command TX 99h Issue Copy Scratchpad with Password Command TX A0h TA1, Target Address = A0h TX 00h TA2, Target Address = 00A0h TX 29h E/S-Byte TX <Full-Access Password> Transmit Full-Access Password (8 Bytes) (—) (Activate Strong Pullup for tPROG) Supply Power for Programming RX AAh Read to Check for Programming Success; AAh Means Success TX (Reset) Reset Pulse RX (Presence) Presence Pulse Step 4 TX CCh Issue Skip ROM Command TX 69h Issue Read Memory with Password Command TX 80h TA1, Target Address = 80h TX 00h TA2, Target Address = 0080h TX <Read Password> Transmit Read Password (8 Bytes) (—) (Activate Strong Pullup for tPROG) Supply Power for Reading RX <64 Bytes> Read Data from Page 2 RX <2 Bytes CRC16> Read Inverted CRC16 Step 5 (—) (Activate Strong Pullup for tPROG) Supply Power for Reading RX <64 Bytes> Read Data from Page 3 RX <2 Bytes CRC16> Read Inverted CRC16 TX (Reset) Reset Pulse RX (Presence) Presence Pulse
REVISION HISTORY
Added the # sign to the PART number in the Ordering Information table, indicating an RoHS-compliant product. 8/09 Removed the UL#913 bullet from the Common iButton Features section. Applied EC table note 13 to t W0L. Deleted from the tW1L spec in the EC table. V TL/VTH clarification: Added to EC table note 4 the text ", which is a function of ..." Added to EC table notes 13 and 14 the reference to Figure 11 and the text "The actual maximum duration...." Added to the write zero time slot graphic in Figure 11. 3, 21