DS1964S MAXIM | Alldatasheet

Document overview

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Technical content

Features

  • Symmetric-Key-Based Bidirectional Secure Authentication Model Based on SHA-256
  • Strong Authentication with a High-Bit-Count User-Programmable Secret and Input Challenge
  • 512 Bits of User EEPROM Partitioned Into Two Pages of 256 Bits
  • User-Programmable and Irreversible EEPROM Protection Modes Including Write and Read Protect and OTP/EPROM Emulation
  • Unique Factory-Programmed, 64-Bit Identification Number
  • Single-Contact 1-Wire Interface
  • Operating Range: -40°C to +85°C
  • ±8kV HBM ESD Protection (typ)
  • Durable Stainless-Steel Enclosure Withstands Harsh Environments and Conditions Typical Application Circuit Ordering Information appears at end of data sheet. DeepCover, iButton, and 1-Wire are registered trademarks of Maxim Integrated Products, Inc.. 19-100347; Rev 0; 6/18 Examples of Accessories DS1964S DeepCover Secure Authenticator iButton with SHA-256 PART ACCESSORY DS9093RA Mounting Lock Ring DS9093A Snap-in FOB DS9092 iButton Probe DS1402D-DR8+ Blue Dot Receptor Cable µC RPUP GPIO VCC 9E E2 1-Wire® 000000FBC52B 4S6

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Electrical Characteristics

(TA = -40NC to +85NC, unless otherwise noted.) (Note 1) DS1964S DeepCover Secure Authenticator iButton with SHA-256 www.maximintegrated.com Maxim Integrated │ 2 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: GENERAL DATA 1-Wire Pullup Voltage VPUP (Note 2) 2.97 3.63 V 1-Wire Pullup Resistance RPUP VPUP = 3.3V ±10% (Note 3) 300 1500 I Input Capacitance CIO (Notes 4, 5) 1500 pF Input Load Current IL IO pin at VPUP 5 19.5 µA High-to-Low Switching Threshold VTL (Notes 6, 7) 0.65 x VPUP V Input Low Voltage VIL (Notes 2, 8) 0.3 V Low-to-High Switching Threshold VTH (Notes 6, 9) 0.75 x VPUP V Switching Hysteresis VHY (Notes 6, 10) 0.3 V Output Low Voltage VOL IOL = 4mA (Note 11) 0.4 V Recovery Time tREC RPUP = 1500Ω (Notes 2, 12) 5 µs Time Slot Duration tSLOT (Notes 2, 13) 13 µs IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE Reset Low Time tRSTL (Note 2) 48 80 µs Reset High Time tRSTH (Note 14) 48 µs Presence-Detect Sample Time tMSP (Notes 2, 15) 8 10 µs IO PIN: 1-Wire WRITE Write-Zero Low Time tW0L (Notes 2, 16) 8 16 µs Write-One Low Time tW1L (Notes 2, 16) 1 2 µs IO PIN: 1-Wire READ Read Low Time tRL (Notes 2, 17) 1 2 - d µs Read Sample Time tMSR (Notes 2, 17) tRL + d 2 µs

Note 1: Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed. Note 2: System requirement. Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. Note 4: Typical value represents the internal parasite capacitance when V PUP is first applied. Once the parasite capacitance is charged, it does not affect normal communication. Note 5: Guaranteed by design and/or characterization only. Not production tested. Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of V PUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected. Note 8: The voltage on IO must be less than or equal to V IL(MAX) at all times the master is driving IO to a logic 0 level. Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected. Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least V HY to be detected as logic 0. Note 11: The I-V characteristic is linear for voltages less than 1V. Note 12: Applies to a single device attached to a 1-Wire line. Note 13: Defines maximum possible bit rate. Equal to 1/(t W0L(MIN) + tREC(MIN)). Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired. Note 15: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS1964S present. The power-up pres - ence detect pulse could be outside this interval but will be complete within 2ms after power-up. Note 16: ε in Figure 6 represents the time required for the pullup circuitry to pull the voltage on IO up from V IL to VTH. The actual maximum duration for the master to pull the line low is t W1L(MAX) + tF - ε and tW0L(MAX) + tF - ε, respectively. Note 17: d in Figure 6 represents the time required for the pullup circuitry to pull the voltage on IO up from V IL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is t RL(MAX) + tF. Note 18: Current drawn from IO during the EEPROM programming interval or SHA-256 computation. The pullup circuit on IO during the programming interval or SHA-256 computation should be such that the voltage at IO is greater than or equal to 2.0V. Note 19: The tPRD interval begins immediately after the trailing rising edge on IO for the last time slot of the release byte for a valid Write Memory and Write Block Protection sequence. The interval ends once the device’s self-timed EEPROM program - ming cycle is complete and the current drawn by the device has returned from I PROG to IL. Note 20: The tPRS interval begins immediately after the trailing rising edge on IO for the last time slot of the release byte for a valid Load and Lock Secret sequence and immediately after the second t CSHA for a valid Compute and Lock Secret sequence. The interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from IPROG to IL. Refer to the Security Users Guide for more details on the Load and Lock Secret and Compute and Lock Secret commands. Note 21: Write-cycle endurance is tested in compliance with JESD47G. Note 22: Not 100% production tested; guaranteed by reliability monitor sampling. Electrical Characteristics (continued) (TA = -40NC to +85NC, unless otherwise noted.) (Note 1) DS1964S DeepCover Secure Authenticator iButton with SHA-256 www.maximintegrated.com Maxim Integrated │ 3 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EEPROM Programming Current IPROG VPUP = 3.63V (Notes 5, 18) 1 mA Programming Time for a 32-Bit Segment or Page Protection tPRD (Note 19) 10 ms Programming Time for the Secret tPRS (Note 20) 100 ms Write/Erase Cycling Endurance NCY TA = +85°C (Notes 21, 22) 100k — Data Retention tDR TA = +85°C (Notes 23, 24, 25) 10 Years SHA-256 ENGINE Computation Current ICSHA VPUP = 3.63V (Notes 5, 18) 1 mA Computation Time tCSHA (Note 26) 3 ms

Electrical Characteristics (continued) (TA = -40NC to +85NC, unless otherwise noted.) (Note 1) Note 23: Data retention is tested in compliance with JESD47G. Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. Note 25: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated temperatures is not recommended. Note 26: The tCSHA interval begins immediately after the trailing rising edge on IO for the last time slot of the Release byte for a valid Compute and Lock Secret sequence, immediately after the trailing rising edge on IO for the last time slot of the first CRC-16 of a Compute and Read Page MAC sequence. Interval ends once the device’s self-timed SHA-256 computation cycle is complete and the current drawn by the device has returned from I CSHA to IL. The commands Compute and Read Page MAC and Compute and Lock Secret require 2 x t CSHA. Pin Configuration Pin Description DS1964S DeepCover Secure Authenticator iButton with SHA-256 www.maximintegrated.com Maxim Integrated │ 4 NAME FUNCTION IO Input/Output GND Ground 9E E2 1-Wire® 16.25mm 5.89mm 0.51mm 17.35mm BRANDING F5 SIZE GND IO 000000FBC52B 4S6

The DS1964S combines a SHA-256 engine with a 256-bit secret, 512 bits of user EEPROM organized as two 256- bit pages, 8 bytes of status memory, and a 64-bit ROM ID in a single chip. A 256-bit scratchpad assists when installing a new secret or stores the challenge when com- puting a page MAC. Data is transferred serially through the 1-Wire protocol, which requires only a single data lead and a ground return. There are multiple programmable options for the 512 bit user array including unrestricted read/write and four protection modes: 1) read protection, 2) write protec - tion and 3) EPROM emulation mode. Read protection prevents user read-access to the memory, which effec - tively converts the protected memory into a secret. The data remains accessible only for the SHA-256 engine. Write protection prevents changes to the memory data. EPROM emulation mode logically ANDs memory data with incoming new data, which allows changing bits from 1 to 0, but not vice versa. By changing one bit at a time this mode could be used to create a nonvolatile nonreset- table counter. EPROM emulation mode requires that the memory is not write protected. In addition to its important use as a unique data value in cryptographic SHA-256 computations, the device’s 64-bit ROM ID can be used to electronically identify the equipment in which the DS1964S is used. The ROM ID guarantees unique identification and is also used to address the device in a multidrop 1-Wire network envi - ronment, where multiple devices reside on a common 1-Wire bus and operate independently of each other. trol of consumables. Overview The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS1964S. The DS1964S has six main data compo - nents: two 256-bit pages of user EEPROM, one 256-bit EEPROM secret, eight bytes of status memory, a 512- bit SHA-256 engine, a 64-bit ROM ID and a 256-bit scratchpad. Figure 2 shows the hierarchic structure of the 1-Wire protocol. The bus master must first provide one of the five ROM function commands: Read ROM, Match ROM, Search ROM, Skip ROM, and Resume Communication. The protocol required for these ROM function commands is described in Figure 4 . After a ROM function command is successfully executed, the memory and SHA-256 functions become accessible and the master can provide any one of the available memory and SHA function commands. The function protocols are described in the Security Users Guide. All data is read and written least significant bit first. DS1964S DeepCover Secure Authenticator iButton with SHA-256 www.maximintegrated.com Maxim Integrated │ 5

Figure 1. Block Diagram Figure 2. Hierarchical Structure for 1-Wire Protocol REFER TO THE SECURITY USERS GUIDE FOR DETAILS.

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1-Wire ROM Function Commands Once the bus master has detected a presence, it can issue one of the five ROM function commands that the DS1964S supports. All ROM function commands are 8 bits long. A list of these commands follows (see the flow- chart in Figure 4). Read ROM [33h] The Read ROM command allows the bus master to read the DS1964S’s ROM ID (8-bit family code, unique 48-bit serial number, and 8-bit CRC). This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result).The family code and 48-bit serial number as read by the master are unlikely to match the CRC. Match ROM [55h] The Match ROM command, followed by a 64-bit ROM ID, allows the bus master to address a specific DS1964S on a multidrop bus. Only the DS1964S that exactly matches the 64-bit ROM ID responds to the following memory or SHA function command. All other slaves wait for a reset pulse. This command can be used with a single or mul - tiple devices on the bus. Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their ROM ID numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the ID of all slave devices. For each bit of the ID number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its ID number bit. On the second slot, each slave device participating in the search outputs the complemented value of its ID number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the search tree. After one complete pass, the bus master knows the ROM ID number of a single device. Additional passes identify the ID numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. Skip ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory or SHA functions without providing the 64-bit ROM ID. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM com - mand, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). Resume Command [A5h] To maximize the data throughput in a multidrop environ - ment, the Resume command is available. This command checks the status of the RC bit and, if it is set, directly transfers control to the memory and SHA functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM or Search ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume command. Accessing another device on the bus clears the RC bit, preventing two or more devices from simulta - neously responding to the Resume command. DS1964S DeepCover Secure Authenticator iButton with SHA-256 www.maximintegrated.com Maxim Integrated │ 8

Figure 4. ROM Functions Flowchart (Refer to the Security Guide for Memory and SHA Function Commands Details)

Figure 6. Read/Write Timing Diagrams

A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below V TL until the read low time tRL is expired. During the tRL window, when responding with a 0, the DS1964S starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS1964S does not hold the data line low at all, and the voltage starts rising as soon as tRL is over. The sum of tRL + d (rise time) on one side and the internal timing generator of the DS1964S on the other side define the master sampling window (tMSR(MIN) to tMSR(MAX)), in which the master must perform a read from the data line. For the most reliable communication, t RL should be as short as permissible, and the master should read close to but no later than t MSR(MAX). After reading from the data line, the master must wait until tSLOT is expired. This guarantees sufficient recovery time tREC for the DS1964S to get ready for the next time slot. Note that t REC speci- fied herein applies only to a single DS1964S attached to a 1-Wire line. For multidevice configurations, tREC must be extended to accommodate the additional 1-Wire device input capacitance. Improved Network Behavior (Switchpoint Hysteresis) In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and topology of the network, reflections from end points and branch points can add up or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the 1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the master and, consequently, result in a Search ROM command coming to a dead end or cause a device-specific function command to abort. The DS1964S uses a 1-Wire front-end with built-in hysteresis at the low-to-high switching threshold V TH. If a negative glitch crosses VTH but does not go below VTH - VHY, it is not recognized (Figure 7). Figure 7. Noise Suppression Scheme

Ordering Information

Package Information

For the latest package outline information and land patterns (foot- prints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. +Denotes a lead(Pb)-free/RoHS-compliant package.. DS1964S DeepCover Secure Authenticator iButton with SHA-256 www.maximintegrated.com Maxim Integrated │ 12 PART TEMP RANGE PIN-PACKAGE DS1964S-F5+ -40°C to +85°C F5 iButton PACKAGE TYPE PACKAGE CODE OUTLINE NO. iButton F5 Can IB+5NT 21-0266 VPUP VTH VHY

Revision History

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2018 Maxim Integrated Products, Inc. │ 13 DS1964S DeepCover Secure Authenticator iButton with SHA-256 REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 6/18 Initial release — For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.