DS1961S-F3

DS1961S MAXIM | Alldatasheet

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1kb Protected EEPROM iButton With SHA-1 Engine www.maxim-ic.com SPECIAL FEATURES /g167 1128 Bits of 5V EEPROM Memory Partitioned into Four Pages of 256 Bits, a 64- Bit Write-Only Secret, and up to Five General-Purpose Read/Write Registers /g167 Write Access Requires Knowledge of the Secret and the Capability of Computing and Transmitting a 160-Bit MAC (Message Authentication Code) as Authorization /g167 Secret and Data Memory can be Write- Protected (All or Page 0 Only) or put in EPROM-Emulation Mode (“Write to 0”, Page /g167 On-Chip, 512-Bit SHA-1 Engine to Compute 160-Bit MACs and Generate Secrets /g167 Reads and Writes Over a Wide 2.8V to 5.25V Voltage Range from -40°C to +85°C /g167 Communicates to Host with a Single Digital Signal at 14.1kbps using 1-Wire ® Protocol /g167 On-Chip, 16-Bit Cyclic Redundancy Check (CRC) Generator for Safeguarding Data Transfers /g167 Overdrive Mode Boosts Communication Speed to 125kbps /g167 Operating Temperature Range from -40°C to +85°C /g167 Minimum 10 Years of Data Retention at +85°C COMMON iButton FEATURES /g167 Unique, Factory-Lasered and Tested 64-Bit Registration Number (8-Bit Family Code + 48-Bit Serial Number + 8-Bit CRC Tester) Assures Absolute Traceability Because No Two Parts are Alike /g167 Multidrop Controller for 1-Wire Net /g167 Digital Identification and Information by Momentary Contact /g167 Chip-Based Data Carrier Compactly Stores Information /g167 Data can be Accessed While Affixed to Object /g167 Button Shape is Self-Aligning with Cup- Shaped Probes /g167 Durable Stainless-Steel Case Engraved with Registration Number Withstands Harsh Environments /g167 Easily Affixed with Self-Stick Adhesive Backing, Latched by its Flange, or Locked with a Ring Pressed onto its Rim /g167 Presence Detector Acknowledges when Reader First Applies Voltage /g167 Meets UL#913 (4th Edit.). Intrinsically Safe Apparatus: Approved Under Entity Concept for use in Class I, Division 1, Groups A, B, C, and D Locations (Application Pending) F5 MicroCan IO GND 0.36 0.51 5.89 © 1993 YYWW REGISTERED RR xx 33 000000FBD8B3 16.25 17.35 F3 MicroCan IO GND 0.36 © 1993 YYWW REGISTERED RR xx 33 000000FBC52B 16.25 17.35 0.51 3.10 All dimensions are shown in millimeters. iButton, 1-Wire, and MicroCan are registered trademarks of Dallas Semiconductor.

ORDERING INFORMATION

DS1963S SHA Coprocessor and Button DS9096P Self-Stick Adhesive Pad DS9101 Multipurpose Clip DS9093RA Mounting Lock Ring DS9093A Snap-In Fob DS9092 iButton Probe iButton DESCRIPTION The DS1961S combines 1024 bits of EEPROM, a 64-bit secret, an 8-byte register/control page with up to five user-read/write bytes, a 512-bit SHA-1 engine, and a fully featured 1-Wire interface in a rugged iButton. Data is transferred serially through the 1- Wire protocol, which require s only a single data lead and a ground return. The DS1961S has an additional memory area called th e scratchpad that acts as a buffer when writing to the main memory, the register page, or when installing a new secret. Data is first written to the scratchpad from where it can be read back. After the data has been verified, a copy scratchpad command transfers the da ta to its final memory location, provided that the DS1961S receives a matching 160-bit MAC. The computation of the MAC involves the secret and a dditional data stored in the DS1961S including the device’s identity register. Only a new secret can be loaded without providing a MAC. The SHA-1 engine can also be activated to compute 160-bit MACs when reading a memory page or to compute a new secret, instead of loading it. The DS1961S understands a unique command "Refresh Sc ratchpad." Proper use of a refresh sequence after a copy scratchpad operation reduces the number of weak bit failures in a touch environment (see the Writing with Verification section). The refresh sequence also pr ovides a means to restore functionality in a device with bits in a weak state. Each DS1961S has its own 64-bit ROM registration num ber that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability. The durable stainless-steel package is highly resistant to environmental hazards such as dirt, moisture, and shock. Its compact coin-shaped profile is self-aligning with mating receptacles, allowing the DS1961S to be easily used by human operators. Accessories permit the DS1961S to be m ounted on almost any surface including plastic key fobs and photo-ID badges.

APPLICATIONS

The DS1961S can be used for different purposes such as secure access control, user/product authentica- tion, after-market management of c onsumables, and as monetary toke ns in electronic payment systems. As carrier of electronic cash (eCash ), the DS1961S can store up to three monetary files or "purses" of a single service provider, which make the device well suited for company-sized single-secret applications such as cafeteria, copy machines, and access control at entertainment parks or private clubs. For increased security or if the processing power of the host mic rocontroller is insufficient, a DS1963S can be used as secure coprocessor to verify MACs generated by the DS1961S or to compute MACs needed for writing to the DS1961S. OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS1961S. The DS1961S has five main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3) four 32-byte pages of EEPROM, 4) 64-bit register page, 5) 64-b it secrets memory, and 6) a 512-bit

Figure 2. The bus master must first provide one of the seven ROM function commands, 1) Read ROM, 2) speed, the device enters overdrive mode where all subsequent communication occurs at a higher speed. function commands is described in Figure 7. All data is read and written LSB first. Figure 1. DS1961S BLOCK DIAGRAM

4 Pages of

Dallas 1-Wire CRC is available in The Book of DS19xx iButton Standards from Dallas Semiconductor. time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all zeros.

read directly; only the SHA engine has access to it for computing message authentication codes. activating EPROM mode for data memory page 1 only, and 4) write-protecting data memory page 0 only. a logic 1 to a logic 0, provided that the data memory is not write protected. of the applicable secret. To setup and register a manufacturer ID contact the factory. customization contact the factory. Figure 6. ADDRESS REGISTERS and TA2 must be loaded with the target address to which the data is written or from which data is read. Register E/S is a read-only transfer-status register, used to verify data integrity with write commands. three bits of TA1 are forced to 0 and the lower three bits of the E/S register (ending offset) always read 1.

This indicates that all the data in the scratchpad is used for a subsequent copying into main memory or secret. Bit 5 of the E/S register, called PF or partial byte flag, is a logic-1 if the number of data bits sent by the master is not an integer multiple of eight or if the data in the scratchpad is not valid due to a loss of power. A valid write to the scratchpad clears the PF bit. Bits 3, 4, and 6 have no function; they always read 1. The partial flag supports the master check ing the data integrity after a write command. The highest valued bit of the E/S register is called the AA or authorization accepted flag, which indicates that the data stored in the scratchpad has already been copied to the target memory address. Writing data to the scratchpad clears this flag. WRITING WITH VERIFICATION To write data to the DS1961S, the sc ratchpad has to be used as interm ediate storage. First the master issues the write scratchpad command, which specifies the desired target address and the data to be written to the scratchpad. Note that writes to data memory must be performed on 8-byte boundaries with the three LSBs of the target address T2–T0 equal to 000b. Theref ore, if T2–T0 are sent with non-zero values, the device sets these bits to zero and uses the modified address as the target address. The master should always send eight complete data bytes. After the eight bytes of data have been transmitted, the master can elect to receive an inve rted CRC16 of the write scratchpad command, the address as sent by the master, and the data as sent by the master. The master can compare the CRC to the value it has calculated itself in order to determine if the communication was successful. After the scratchpad has been written, the master should always perform a read scratchpad to verify th at the intended data was in fact written. During a read scratchpad, the DS1961S repeats the target addr ess TA1 and TA2 and sends the contents of the E/S register. The partial flag (bit 5 of the E/S register) is set to 1 if the last data byte the DS1961S received during a write scratchpad or refresh scratchpad command was incomplete, or if there was a loss of power since data was last written to the scratchpad. The authorization-accepted (AA) flag (bit 7 of the E/S register) is normally cleared by a write scratchpad or refresh scratchpad; therefore, if it is set to 1, it indicates that the DS1961S did not understand the proceeding write (o r refresh) scratchpad command. In either of these cases, the master should rewrite the sc ratchpad. After the master receives the E/S register, the scratchpad data is received. The descriptions of write scratchpad and refresh scratchpad provide clarification of what changes can occur to the sc ratchpad data under certain conditions. An inverted CRC of the read scratchpad command, target address, E/S register, and scra tchpad data follows the scratchpad data. As with the write scratchpad command, this CRC can be compared to the value the master has calculated itself in order to determine if the communication was successful. After the master has verified the data, it can send the copy scratchpad to copy the scratchpad to memory. Alternatively, the load first secret or compute next secret command can be issued to change the secret. See the descriptions of these commands for more information. In a touch environment the quality of the electr ical contact cannot be guaranteed. With poor or intermittent contact it is possible for a copy scratchpad command to complete with insufficient energy, leaving the floating gate voltage of an EEPROM bit in the area of the threshold between 0 and 1. When this occurs, the logical value of the bit is not assured. Depending on voltage and/or temperature conditions, the same bit can be read by the host as on e polarity and then by the internal SHA-1 engine as the opposite polarity. This becomes a fatal lockup mode because the host cannot formulate a proper SHA- 1 MAC to enable the bit to be rewritten. To repair poorly written bits and thereby restore the device to functionality, the refresh scratchpad command was introduced. Combined with the load first secret command, refresh scratchpad provides a means to re store the EEPROM bits to normal values, removing lockup conditions and allowing the device to be written again. To prevent the occurrence of poorly written bits, a refresh sequence should be performed after each copy scratchpad command. A refresh sequence is defined as a refresh scratchpad (to the same target address as the previous copy scratchpad), followed by a load fi rst secret. The EN_LFS flag is set by the refresh

scratchpad command. The EN_LFS flag enables the use of load first secret to addresses 0000h–007Fh. Using load first secret allows the master to copy the scratchpad to memory without the MAC computation necessary during a copy scratchpad. If the master attempts any command after refresh scratchpad that could change the scratchpad data or the target address, EN_LFS is reset to 0. This prevents the use of load first secret to load any data other than the refreshed memory data to any location other than the one specified during refresh scratchpad. Refresh scratchp ad behaves exactly as write scratchpad does for target addresses 0080h and above . In this case the EN_LFS flag is not set, so it is not possible to refresh the data in the secret (0080h) or in the register page (0088h). This prevents the secret from being revealed by a refresh scratchpad followed by a read scratchpad. MEMORY AND SHA FUNCTION COMMANDS Due to its design as a secure devi ce, the DS1961S has to behave differently from other memory iButtons. Although most of the memory of the DS1961S can be read the same way as any other memory iButton, attempts to read the secret results in FFh-bytes rather than real data. The Memory and SHA Function Flow Chart (Figure 7) describes the protocols necessary for accessing the memory and operating the SHA engine. The communication between master and DS1961S takes place either at regular speed (default, OD = 0) or at overdrive speed (OD = 1). If not ex plicitly set into overdrive mode the DS1961S assumes regular speed. Write Scratchpad [0Fh] The write scratchpad command applies to the data memory, the secret and the writeable addresses in the register page. If the bus master sends a target address higher than 90h, the command is not executed. After issuing the write scratchpad command, the master must first pr ovide the 2-byte target address, followed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the beginning of the scratchpad. Note that the ending o ffset (E2..E0, see Figure 6) is always 111b regardless of the number of bytes that the master has trans mitted. For this reason the master should always send eight bytes, especially if the data is to be loaded as a secret. If the master sends less than eight data bytes and does not read back the scratchpad for verification, parts of the new secret can be random data that is unknown to the master. Only full data bytes are accepted. If the last data byte is incomplete its content is ignored and the partial byte flag (PF) is set. When executing the write scratchpad command the CRC generator inside the DS1961S (see Figure 12) calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte as sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0Fh) of the write scratchpad command, the target addresses (TA1 and TA2), and all the data bytes. Note that the CRC16 calculation is performed with the actual TA1 sent by the master even though the DS1961S sets TA1 bits T2..T0 to 000b for the actual write scratchpad command. The master can end the write scratchpad command at any time. However, if the scratchpad is filled to its capacity, the master can send 16 read-time slots and receives the CRC generated by the DS1961S. If the master continues reading after the CRC all data is be FFh. After receiving the target addresses (TA1 and TA 2), the DS1961S clears the EN_LFS flag. If EPROM mode is active and a write scratchpad is attempted within page 1 (0020h–003Fh), the scratchpad is loaded with the logical AND of the scratchpad data sent by the master and the current content of the target memory location. If a write scratc hpad is attempted to the register page (0088h–008Fh), any bytes that are write-protected overwrite the corresponding scratchpa d data byte sent by the master with the existing value. In all other cases, the data sent by the master is written to the scratchpad unaltered.

Read Scratchpad [AAh] The read scratchpad command allows verifying the target address and the integrity of the scratchpad data. After issuing the command code, the master begins reading. The first two bytes is the target address with T2 to T0 = 0. The next byte is the ending offset/data status byte (E/S) followed by the scratchpad data, which may be different from what the master has originally sent. This is of particular importance if the target address is the secret, the register page, page 1 (in EPROM mode), or if refresh was used to load the scratchpad. In these cases, the scratchpad can contain data other than that which was sent during either the write scratchpad or refresh sc ratchpad commands. The master should read through the end of the scratchpad after which it receives the inverted CRC that is computed with the data as sent by the DS1961S. If the master continues reading after the CRC all data is FFh. The scratchpad can be loaded using the write scra tchpad or refresh scratchpad command. The data found in the scratchpad depends on the command used, the target address, and whether or not EPROM mode is active. See the descriptions of write scratchpad and refresh scratchpad for clarification. Load First Secret [5Ah] The load first secret command has two modes of ope ration, which are controlled by the EN_LFS flag. With EN_LFS = 0, the command replaces the device’s current secret with the contents of the scratchpad, provided that the secret is not write-protected. With EN_LFS = 1, the command allows to rewrite memory data (addresses 0000h to 007Fh), bypassing th e SHA-1 computation that is required when doing the same through the copy scratchpad command. The EN _LFS flag is 0 unless it has been set to 1 by executing the refresh scratchpad command prior to load first secret. Case EN_LFS = 0 Before the load first secret command can be used in this mode, the master must have written the new secret to the scratchpad using the starting address of the secret (0080h). After issuing the load first secret command, the master must provide a 3-byte authorization pattern (TA 1, TA2, E/S, in that order), that should have been obtained by an immediately preced ing read scratchpad command. This 3-byte pattern must exactly match the data contained in the three address registers (see Figure 6). If the pattern matches and the secret is not write-protected, the AA flag is set and the copy begins. All eight bytes of scratchpad contents are copied to the secret’s memory location. Case EN_LFS = 1 To use the load first secret command in this m ode, the refresh scratchpa d command must have been executed to load eight bytes of memory data (a ddress range 0000h to 007Fh) into the scratchpad, which sets the EN_LFS flag to 1. After issuing the load first secret command, the master must provide a 3-byte authorization pattern (TA1, TA2, E/S, in that order), that can be obtained by an immediately preceding read scratchpad command without affecting the EN_LFS flag. This 3-byte pattern must exactly match the data contained in the three address registers (see Figure 6). If the pattern matches and the memory is not write-protected, the AA flag is set and the copy begins . All eight bytes of scratchpad contents are copied to the memory location. Regardless of the mode used, the dur ation of the copy operation is t PROG during which the voltage on the 1-Wire bus must not fall below 2.8V. The master should read at least one byte at the conclusion of the copy delay. Reading AAh indicates that the copy was successful, while reading FFh indicates that the copy was not successful. Instead of using load first secret with EN_LFS = 0, a new secret can alternatively be loaded with the copy scratchp ad command. However, this approach requires the knowledge of the current secret and the computation of a 160-bit MAC.

Figure 7-1. MEMORY AND SHA FUNCTIONS FLOW CHART 0Fh Write Scratch- pad ? Master TX Reset ? Master TX Data Byte To Scratchpad Bus Master TX TA1 (T7:T0), TA2 (T15:T8) Y N N YN Address < 90h ? Y Bus Master RX “1”s Master TX Reset ? Y N DS1961S Sets Scratchpad Byte Counter = 0, Clears PF, AA, Sets T2:T0 = 0, 0, 0, Sets E2:E0 = 1, 1, 1 Byte Counter = 7 ? DS1961S TX CRC16 of Command, Address, Data Bytes as They Were Sent by the Bus DS1961S Increments Byte Counter Master TX Reset ? Y NBus Master RX “1”s Partial Byte ? PF = 1 Y NN Y To Figure 7 2nd Part From Figure 7 2nd Part Bus Master TX Memory Function Command To ROM Functions Flow Chart (Figure 9) From ROM Functions Flow Chart (Figure 9) DS1961S Sets EN_LFS = 0 Note: See the Write Scratchpad Description for Additional Information.

Figure 7-2. MEMORY AND SHA FUNCTIONS FLOW CHART (continued) AAh Read Scratch- Pad ? DS1961S Sets Scratchpad Byte Counter = 0 Bus Master RX TA1 (T7:T0), TA2 (T15:T8) and E/S Byte Bus Master RX Data Byte from Scratchpad Bus Master RX CRC16 of Command, Address, E/S Byte, Data Bytes as Sent by the DS1961S Y Bus Master RX “1”s Master TX Reset ? Y N Master TX Reset ? DS1961S Increments Byte Counter Byte Counter = 7 ? Y Y N N N From Figure 7 1st Part To Figure 7 1st Part To Figure 7 3rd Part From Figure 7 3rd Part Note: See the Read Scratchpad Description for Additional Information.

Figure 7-3. MEMORY AND SHA FUNCTIONS FLOW CHART (continued) * 1-Wire Idle High for Power From Figure 7 2nd Part To Figure 7 2nd Part To Figure 7 4th Part From Figure 7 4th Part 5Ah Load First Secret ? Bus Master TX TA1 (T7:T0), TA2 (T15:T8) and E/S Byte Y N Bus Master RX “1”s Master TX Reset ? Y N Note: The 8-Byte Secret Must First be Written to the Scratchpad. YAuth. Code Match ? N Address of Secret ? YN N Write- Protected ? Y DS1961S Copies Scratch- Pad Data to Address AA = 1 DS1961S TX “0” Master TX Reset ? Master TX Reset ? Y N DS1961S TX “1” N Y Address <7Fh ? N Y EN_LFS Flag = 1 ? N Y Duration: tPROG

Figure 7-4. MEMORY AND SHA FUNCTIONS FLOW CHART (continued) 33h Compute Next Secret ? Y N * 1-Wire Idle High for Power Note: The Master Must First Load the Scratchpad With a Partial Secret of 8 Bytes From Figure 7 3rd Part To Figure 7 3rd Part From Figure 7 5th Part To Figure 7 5th Part Valid Data Address ? Y Bus Master RX “1”s Master TX Reset ? Y N N N SHA Engine Computes Message Authentication Code of Current Secret, Page Data, and 8 Byte Partial Secret in Scratchpad DS1961S Copies a Partial MAC to the Secret Register Master TX Reset ? Master TX Reset ? Y N DS1961S TX “1” DS1961S TX “0” N Y DS1961S Fills Scratchpad With AAh Write- Protected ? Y Bus Master TX TA1 (T7:T0), TA2 (T15:T8) DS1961S Sets EN LFS = 0 Duration: tCSHA Duration: tPROG

Figure 7-5. MEMORY AND SHA FUNCTIONS FLOW CHART (continued) 55h Copy Scratch- pad ? Y N Bus Master TX TA1 (T7:T0), TA2 (T15:T8), E/S Byte Auth. Code Match ? N Y Bus Master RX “1”s Master TX Reset ? Y N AA = 1 DS1961S Copies Scratch- pad Data to Memory Master TX Reset ? Master TX Reset ? Y N DS1961S TX “1” DS1961S TX “0” N Y MAC Code Match ? Y N N DS1961S TX “0”s Master TX Reset ? Y * 1-Wire Idle High for Power SHA Engine Computes Message Authentication Code of Secret, 28 Bytes of Page Data, Scratchpad Data, and Device Identity Register Bus Master Computes MAC and Sends it to DS1961S From Figure 7 4th Part To Figure 7 4th Part To Figure 7 6th Part From Figure 7 6th Part Bus Master Waits 10ms Write- Protected ? Y N Note: This Command is Applicable to all R/W Memory Addresses. Duration: tCSHA Duration: tPROG

Figure 7-6. MEMORY AND SHA FUNCTIONS FLOW CHART (continued) A5h Read Auth. Page ? Y N * 1-Wire Idle High for Power Note: Three Bytes of the Scratchpad Contents are Taken as a Challenge to the DS1961S. The Master can Specify the Challenge or Accept the Current Scratchpad Contents Instead. Y N Address < 80h ? N Bus Master RX “1”s Master TX Reset ? Y DS1961S sets Memory Address = (T15:T0) Master TX Reset ? Y N Bus Master RX CRC16 of Command, Address, Data, and FFh Byte DS1961S Increments Address Counter Master TX Reset ? Master RX Data Byte From Memory Address N Y End Of Page ? N Y Master RX One Byte FFh Master TX Reset ? Master TX Reset ? Y N DS1961S TX “1” DS1961S TX “0” N Y SHA Engine Computes Message Authentication Code of Secret, Data of Selected Page, Device Identity Register and 3-Byte Challenge Bus Master RX 160-Bit Message Auth. Code Bus Master RX CRC16 of Message Auth. Code From Figure 7 5th Part To Figure 7 5th Part To Figure 7 7th Part From Figure 7 7th Part Bus Master TX TA1 (T7:T0), TA2 (T15:T8) DS1961S Sets EN_LFS = 0 Duration: tCSHA

Figure 7-7. MEMORY AND SHA FUNCTIONS FLOW CHART (continued) A3h Refresh Scratch- pad ? Y N Bus Master TX TA1 (T7:T0), TA2 (T15:T8) YN Bus Master RX “1”s Master TX Reset ? Y N Master TX Reset ? Master TX Data Byte; DS1961S Loads Memory Byte to Scratchpad N Y DS1961S Sets Scratch- pad Byte Counter = 0, Clears PF, AA, Sets T2:T0 = 0, 0, 0, Sets E2:E0 = 1, 1, 1 Byte Counter = 7 ? DS1961S Increments Byte Counter Partial Byte ? PF = 1 Y NN Y To Figure 7 8th Part From Figure 7 8th Part From Figure 7 6th Part To Figure 7 6th Part DS1961S Sets EN_LFS = 0 EN_LFS = 1 DS1961S TX CRC16 of Command, Address, Data Bytes as They Were Sent by the Bus Master Master TX Reset ? Y NBus Master RX “1”s The Flag is Set Only if Target Address is /g163 7Fh. Address < 90h ? Note: See the Refresh Scratchpad Description for Additional Information.

Figure 7-8. MEMORY AND SHA FUNCTIONS FLOW CHART (continued) F0h Read Memory ? Y N From Figure 7 7th Part To Figure 7 7th Part Address < 98h ? Y N Y N Address Of Secret DS1961S Sets Memory Address = (T15:T0) DS1961S Increments Address Counter Bus Master RX “1”s N Address < 97h ? Master TX Reset ? Y N Y Master TX Reset ? Bus Master RX Data Byte from Memory Address Bus Master RX FFh Byte Y N N Bus Master RX “1”s Master TX Reset ? Y Bus Master TX TA1 (T7:T0), TA2 (T15:T8) DS1961S Sets EN LFS = 0

then overwrite the existing secret. Table 1. SHA-1 INPUT DATA FOR COMPUTE NEXT SECRET COMMAND

indicates that the copy was not successful because of an incorrect address or because of write protection. into the SHA engine. The SHA computation algorithm is explained later in this document. Table 2. MESSAGE AUTHENTICATION CODE TRANSMISSION SEQUENCE The transmission is least significant bit first starting with register E.

not fall below 2.8V. If the MAC generated by the DS 1961S matches the MAC that the master computed, the DS1961S sets its AA flag, and copy the entire sc ratchpad contents to the data EEPROM. The master should read at least one byte at the conclusion of the copy delay. Reading AAh indicates that the copy was successful. Reading 00h indicates that the copy was not successf ul because the computed MAC did not match the MAC sent by the master. Reading FFh indicates that the copy was not successful because of write protection or because of an incorrect authorization pattern. Table 3a. SHA-1 INPUT DATA FOR COPY SCRATCHPAD COMMAND WHEN COPYING TO A DATA MEMORY PAGE M13[31:24] = FFh M13[23:16] = FFh M13[15:8] = FFh M13[7:0] = 80h M14[31:24] = 00h M14[23:16] = 00h M14[15:8] = 00h M14[7:0] = 00h M15[31:24] = 00h M15[23:16] = 00h M15[15:8] = 01h M15[7:0] = B8h Legend Mt Input Buffer of SHA Engine 0 /g163 t /g163 15; 32-Bit Words (SS + N) Byte N of Secret; Secret Begins at Address 0080h (see Memory Map) (PP + N) Byte N of Memory Page; Memory Pages Begin at 0000h, 0020h, 0040h and 0060h (see Memory Map) (SP + N) Byte N of Scratchpad MP MP[7:3] = 00000b, MP[2:0] = T7:T5 (ID + N) Byte N of Identity Register The Last Byte of the Identity Register is Not Used. Special attention is required when copying data to the register page. In order to prevent unintentional locking of a special function register or user byte it is recommended to first read the register page and then write it with all intended modifications to the scratchpad. When copying data to the register page (or the secret using copy scratchpad), the input data for M1 to M7 of the SHA engine is the current secret (M1, M2), the current content of the register page (M3, M4), the full content of the identity register (M5, M6), and 4 bytes FFh (M7), as shown in Table 3B. As a consequence, when using a DS1963S as coprocessor to compute the MAC to transfer data from the scratchpad to the register page, the secret must be used as page data. This precludes the use of partial (computed) secrets if writing to the register page is

required. For practical use of the DS1961S as a monetary token, partia l secrets are more critical than being able to write-protect the secret or other areas of the device. Table 3b. SHA-1 INPUT DATA FOR COPY SCRATCHPAD COMMAND WHEN COPYING TO THE REGISTER PAGE OR SECRET M7[31:24] = FFh M7[23:16] = FFh M7[15:8] = FFh M7[7:0] = FFh M13[31:24] = FFh M13[23:16] = FFh M13[15:8] = FFh M13[7:0] = 80h M14[31:24] = 00h M14[23:16] = 00h M14[15:8] = 00h M14[7:0] = 00h M15[31:24] = 00h M15[23:16] = 00h M15[15:8] = 01h M15[7:0] = B8h Legend Mt Input Buffer of SHA Engine 0 /g163 t /g163 15; 32-Bit Words (SS + N) Byte N of Secret; Secret Begins at Address 0080h (see Memory Map) (RP + N) Byte N of Register Page; Page Begins at 0088h (see Memory Map) (SP + N) Byte N of Scratchpad MP MP[7:0] = 04h (ID + N) Byte N of Identity Register Read Authenticated Page [A5h] The read authenticated page command provides the master with the data of a full or partial memory page plus a MAC. The MAC allows the master to determin e whether the secret stored in the DS1961S is valid within the application. The DS1961S computes the MAC from its secret, all the data of the selected memory page, the first seven bytes of the identity register and a 3-byte challenge, which the master should write to the scratchpad prior to issuing th e read authenticated page command. To do this, the master can use the write scratchpad command with any target address within the data memory. The relevant portions of the challenge are the 5th, 6 th, and 7th bytes. Alternatively, the master can accept the data that happens to reside in the scratchpad from a previous command as a challenge. The 160-bit MAC is transmitted in the same way as with the copy scratchpad command, Table 2, but the data flows from the DS1961S to the master. The data input to the SHA engine as it applies to the read authenticated page command is shown in Table 4.

received, the master waits for tCSHA during which the voltage on the 1-Wire bus must not fall below 2.8V. means to safeguard the data transfer. If the master continues reading after the CRC it receives AAh. Table 4. SHA-1 INPUT DATA FOR READ AUTHENTICATED PAGE COMMAND The Last Byte of the Identity Register is Not Used.

Refresh Scratchpad [A3h] Refresh scratchpad loads memory data to the scratchpad and sets the EN_LFS flag, which enables the use of the load first secret command to re-write the data that was just read from the memory, bypassing the MAC computation of copy scratchpad. The command flow chart of refresh scratchpad is very similar to write scratchpad. If the target address is between 0000h–007Fh, there are two primary differences. 1) The data bytes that the master transmits following the target address are discarded; instead, the scratchpad is loaded with the unaltered memory data located at the target address, even if the memory page is in EPROM mode. 2) After the master has transmitted the eight dummy bytes, the EN_LFS flag is set to 1. The EN_LFS flag is cleared to 0 after receiving TA1 and TA2 during a write scratchpad, compute next secret, read authenticated page, refresh scratch, read memory, or by a power-on reset, because these commands can change the target address and/or the data in the scratchpad. When applied to addresses 0080h–008Fh, the refres h scratchpad command beha ves the same way as write scratchpad. This protects the secret from being exposed by a subsequent read scratchpad command. Read Memory [F0h] The read memory command can be used to read all memory except for the secret. Attempting to read the secret results in FFh bytes instead of the actual secret. After the master has issued the command code and specified the target addresses (TA1 and TA2), the DS1961S first clears the EN _LFS flag. If the target address is valid, the master reads data beginning from the target address and can continue until address 0097h. If the master continues reading, the result is lo gic 1s. It is important to realize that the target address registers point to the last byte read. The ending offset/data status byte and the scratchpad are unaffected. The hardware of the DS1961S provides a means to ac complish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet typically stores a master-calculated 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (Refer to Application Note 114 for the recommended file structure, which is also referred to as TMEX Format.)

SHA-1 COMPUTATION ALGORITHM This description of the SHA com putation is adapted from the Secure Hash Standard SHA-1 document takes as its input data sixteen 32-bit words M t (0 /g163 t /g163 15), as shown in Tables 1, 3A, 3B, and 4 for the compute next secret, copy scratchpad, and read authenticated page command, respectively. The SHA computation involves a sequence of eighty 32-bit words called W t (0 /g163 t /g163 79), a sequence of eighty 32- bit words called Kt (0 /g163 t /g163 79), a Boolean function ft (B, C, D) (0 /g163 t /g163 79) with B, C, and D being 32-bit words, and three more 32-bit words called A, E, and TMP. The operations required for the SHA computation are arithmetic addition without carry (“+”), logical inve rsion or 1’s complement (“\\”), EXCLUSIVE OR (“/g197”), logical AND (“ /g217”), logical OR (“ /g218”), assignment (“:=”), and circular shifting within a 32-bit word. The expression “S n(X)” represents a circular shift of X by n positions to the left, with X being a 32-bit word. The function ft is defined as follows: B /g197 C /g197 D (20 /g163 t /g163 39) (B /g217 C) /g218 (B /g217 D) /g218 (C /g217 D) (40 /g163 t /g163 59) B /g197 C /g197 D (60 /g163 t /g163 79) The sequence Wt (0 /g163 t /g163 79) is defined as follows: Wt := M t (0 /g163 t /g163 15) S1(Wt-3 /g197 Wt-8 /g197 Wt-14 /g197 Wt-16) (16 /g163 t /g163 79) The sequence Kt (0 /g163 t /g163 79) is defined as follows: Kt := 5A827999h (0 /g163 t /g163 19) 6ED9EBA1h (20 /g163 t /g163 39) 8F1BBCDCh (40 /g163 t /g163 59) CA62C1D6h (60 /g163 t /g163 79) The variables A, B, C, D, E are initialized as follows: A := 67452301h B := EFCDAB89h C := 98BADCFEh D := 10325476h E: = C 3 D 2 E 1 F 0 h The 160-bit MAC is the concatenation of A, B, C, D, and E after looping through the following set of computations for t = 0 to 79 (discarding any carry-out): TMP := S 5(A) + ft(B,C,D) + Wt + Kt + E E: = D D: = C C: = S 30(B) B: = A A: = T M P

The master can read the MAC with the read authenticated page command in a register and bit sequence as shown in Table 3. With the copy scratchpad command the bit transmission sequence is the same, however, the master has to compute the MAC and se nd it to the DS1961S. With the compute next secret command the MAC is not exposed. Instead, the contents of the D and E SHA computation registers are directly copied to the secret, as shown in Table 1. 1-WIRE BUS SYSTEM The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the DS1961S is a slave device. The bus ma ster is typically a microcontroller. For small configurations the 1- Wire communication signals can be generated under so ftware control using a single port pin. For larger configurations, the DS2480B 1-Wire line driver chip or serial port adapters based on this chip (DS9097U series) are recommended. This simplifies the hardware design and frees the microprocessor from responding in real-time. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. For a more detailed protoc ol description, refer to Chapter 4 of The Book of DS19xx iButton Standards. HARDWARE CONFIGURATION The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open- drain or tri-state outputs. The 1-Wire port of the DS1961S is open drain with an internal circuit equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At standard speed the 1-Wire bus has a maximum data rate of 16.3kbps. The speed can be boosted to 142kbps by activating the overdrive mode. The DS1961S is not guaranteed to be fully co mpliant to the iButton st andard. Its maximum data rate in standard speed mode is 14.1kbps and 125kbps in overdrive. The DS1961S requires a 1-Wire pullup resistor of maximum 2.2k /g87 for executing any of its memory and SHA function commands at any speed. When communicating with several DS1961S simu ltaneously, e.g., to inst all the same secret in several devices, the resistor should be bypassed by a low-impedance pullup to V PUP while the device transfers data from the scratchpad to the EEPROM. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs (overdrive speed) or more than 120µs (regular speed), one or more devices on the bus can be reset. With the DS1961S the bus must be le ft low for no longer than 15.2µs at overdrive speed to ensure that none of the slave devices on the 1-Wi re bus performs a rese t. Despite of its limited compliance, the DS1961S communicat es properly when used in conjunction with a DS2480B 1-Wire driver and serial port adapters that are based on this driver chip.

Figure 8. HARDWARE CONFIGURATION operate. For more details, see the 1-Wire Signaling section. number responds to the following memory function command. All other slaves wait for a reset pulse. This command can be used with single or multiple devices on the bus.

Figure 9-1. ROM FUNCTIONS FLOW CHART From Figure 9 2nd PartTo Memory Functions Flow Chart (Figure 7) Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 Bit 63 Match ? RC = 0 DS1961S TX Bit 0 DS1961S TX Bit 0 Master TX Bit 0 DS1961S TX Bit 1 DS1961S TX Bit 1 Master TX Bit 1 DS1961S TX Bit 63 DS1961S TX Bit 63 Master TX Bit 63 RC = 1 Bit 1 Match ? Bit 0 Match ? Y N Y N Y NBit 63 Match ? RC = 0 RC = 1 Bit 1 Match ? Bit 0 Match ? Y N Y N Y N RC = 0 DS1961S TX CRC Byte DS1961S TX Serial Number (6 Bytes) DS1961S TX Family Code (1 Byte) RC = 0 To Figure 9 2nd PartNF0h Search ROM Command ? N55h Match ROM Command ? N CCh Skip ROM Command ? YY YY N33h Read ROM Command ? To Figure 9 2nd Part From Memory Functions Flow Chart (Figure 9) Bus Master TX ROM Function Command DS1961S TX Presence Pulse OD Reset Pulse ? N Y OD = 0 Bus Master TX Reset Pulse From Figure 9, 2nd Part

Figure 9-2. ROM FUNCTIONS FLOW CHART To Figure 9 1st Part From Figure 9 1st Part From Figure 9 1st Part To Figure 9, 1st Part Y NA5h Resume Command ? RC = 1 ? Y N3Ch Overdrive Skip ROM ? RC = 0 ; OD = 1 Master TX Reset ? Y N N Y Master TX Reset ? N Y Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 Bit 63 Match ? RC = 0 ; OD = 1 RC = 1 Bit 1 Match ? Y N Y N Bit 0 Match ? Y N Y N69h Overdrive Match ROM ?

Search ROM [F0h] When a system is initially brought up, the bus master may not know the number of devices on the 1-Wire bus or their 64-bit registration numbers. The sear ch ROM command allows the bus master to use a process of elimination to identify the 64-bit numbers of all slave devices on the bus. The search ROM process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this 3-step routine on each bit of the registration number. After one complete pass, the bus master knows the 64-bit number of one device. Additional passes will identify the registration numbers of the remaining devices. Refer to Chapter 5 of The Book of DS19xx iButton Standards for a detailed discussion of a search ROM, including an actual example. Skip ROM [CCh] This command can save time in a single drop bus system by allowing the bus master to access the memory and SHA functions without providing the 64-bit registration number. If more than one slave is present on the bus and, for example, a read comma nd is issued following the skip ROM command, data collision occurs on the bus as multiple slaves tran smit simultaneously (open-drain pulldowns produce a wired-AND result). Resume Command [A5h] In a typical application the DS1961S needs to be acce ssed several times to write a full 32-byte page. In a multidrop environment this means that the 64-bit registration number of a match ROM command has to be repeated for every access. To maximize the da ta throughput in a multidrop environment the resume command function was impleme nted. This function checks the status of the RC bit and, if it is set, directly transfers control to the memory and S HA functions, similar to a skip ROM command. The only way to set the RC bit is through successfully executing the match ROM, search ROM, or overdrive match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the resume command function. Accessing another device on the bus clears the RC bit, preventing two or more devices from simultaneously responding to the resume command function. Overdrive Skip ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory and SHA functions without providing the 64-bit regist ration number. Unlike the normal skip ROM command the overdrive skip ROM sets the DS1961S in the overdrive mode (OD = 1). All communication following this command code has to occur at overdrive speed until a reset pulse of minimum 480µs duration resets all devices on the bus to regular speed (OD = 0). When issued on a multidrop bus this command sets all overdrive-supporting devices into overdrive mode. To subsequently address a specific overdrive- supporting device, a reset pulse at overdrive speed ha s to be issued followed by a match ROM or search ROM command sequence. This speeds up the search process. If more than one slave supporting overdrive is present on the bus and the overdrive skip ROM command is followed by a read command, data collision occurs on the bus as multiple slaves tran smit simultaneously (open-drain pulldowns produce a wired-AND result). Overdrive Match ROM [69h] The overdrive match ROM command, followed by a 64- bit registration number transmitted at overdrive speed, allows the bus master to address a specifi c DS1961S on a multidrop bus and to simultaneously set it in overdrive mode. Only the DS1961S that ex actly matches the 64-bit number responds to the subsequent memory or SHA function command. Slav es already in overdrive mode from a previous overdrive skip or a successful overdrive match command will remain in overdrive mode. All overdrive- capable slaves return to regular speed at the ne xt reset pulse of minimum 480µs duration. The overdrive match ROM command can be used with single or multiple devices on the bus.

signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, and read data. To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL. VILMAX is relevant for the DS1961S when determining a logical level, but not for triggering any events.

1. A reset pulse followed by a presence pulse indicat es the DS1961S is ready to receive data, given the

exceed the maximum value specified for overdrive speed. Figure 10. INITIALIZATION PROCEDURE (RESET AND PRESENCE PULSES) tPDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP.

Data communication with the DS1961S takes place in time slots that car ry a single bit each. Write-time slots transport data from bus master to slave. Read-time slots transfer data from slave to master. The definitions of the write- and read-time slots are illustrated in Figure 11. All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the threshold V TL, the DS1961S starts its internal time base. The tolerance of the slave time base creates a slave-sampling window that stretches from t SLSMIN to tSLSMAX. The voltage on the data line at the sampling point determines whether the DS1961S decodes the time slot as 1 or 0. For reliable communication the voltage has to be either below the V ILMAX or above the maximum V TH value during the entire sampling window. Master-to-Slave For a write-one time slot, the master pulldown time (t MPD1 = tW1L -/g101 + t F) must be short enough to allow the voltage on the 1-Wire line to reach VTH at tSLSMIN, the earliest sampling point of a DS1961S. After the latest sampling point (tSLSMAX) there needs to be a recovery time (tREC) before the next time slot can start. For a write-zero time slot, the master pulldown time (t MPD0 = tW0L + tF) must be long enough to keep the voltage on the data line below VILMAX at the sampling point of a slow DS1961S, which is t SLSMAX. Before the next time slot can start, the voltage on the data line first needs to rise above V TH and remain there until the recovery time tREC is expired. Slave-to-Master A read-data time slot is very similar to a write-one time slot. The master begins a read-data time slot with pulling the data line low. As the voltage on the 1-Wire line falls below the threshold V TL, the DS1961S starts its internal time base. The master pulldown time (tMPDR = tRL + tF) must be long enough to cover the setup time t SU, after which the DS1961S delivers a bit to its 1-Wire port. When transmitting a 0, the DS1961S holds the data line low for t SPD. If the data bit is a 1, the DS1961S does not hold the data line low at all. The master samples the data line at tMSR, inside a window that is determined by the sum of tRL and the rise time (/g100) on one side and t SPDMIN on the other side. The optimum sample point for a read-zero case is no later than tSPDMIN. In case of a read-one, the voltage on the 1-Wire line must be able to reach V IHMASTER at tMSR. This condition determines the maximum duration of the master pulldown time. For reliable communication, the master pulldown time should be as short as possible, maximizing the time for the data line to reach VIHMIN. Before the next time slot can start, t SPDMAX needs to be over and the voltage on the data line must have risen above VTH and remained there until the recovery time tREC is expired.

Figure 11. READ/WRITE TIMING DIAGRAMS

operation or to re-read the portion of the data with the CRC error. transmits this CRC only if the reading continues through the end of the scratchpad. byte into the cleared CRC generator, followed by the two address bytes, the data bytes, and the FFh byte. MAC in the same bit sequence as the master receives it. software, refer to The Book of DS19xx iButton Standards. Figure 12. CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL

ABSOLUTE MAXIMUM RATINGS* I/O Voltage to GND -0.5V, +6V I/O Sink Current 20mA Temperature Range -40°C to +85°C Junction Temperature +150°C Storage Temperature Range -55°C to +85°C * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Operating Temperature T A All, except EEPROM programming -40 85 /g176C 1 All -20 85 1-Wire Pullup V PUP Standard speed 2.8 5.25 V 1 Overdrive speed 3.3 5.25 I/O PIN GENERAL DATA 1-Wire Pullup Resistance RPUP 2.2 k/g87 1, 2 Input Capacitance C IO 100 800 pF 3, 14 Input Load Current I L I/O pin at VPUP 11 0 µ A 4 High-to-Low Switching Threshold VTL 1.5 V 5, 6, 7, Input Low Voltage V IL 0.30 V 1, 5, 8 Low-to-High Switching Threshold V TH 1.5 V 5, 6, 9, Output Low Voltage at 4mA V OL 0.4 V 5, 10 Recovery Time t REC Standard speed, RPUP = 2.2k/g87 5 µs 1, 14 Overdrive speed, RPUP = 2.2k/g87 2 Overdrive speed, directly prior to reset pulse; RPUP = 2.2k/g87 Timeslot Duration t SLOT Standard Speed 65 µs 1, 13 Overdrive speed, VPUP > 4.5V 7 Overdrive speed 9 I/O PIN, 1-WIRE RESET, PRESENCE DETECT CYCLE Reset Low Time t RSTL Standard speed, VPUP > 4.5V 480 640 µs 1, 13 Standard speed 720 960 Overdrive speed, VPUP > 4.5V 60 80 Overdrive speed 68 80

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Presence Detect High t PDH Standard speed 15 60 µs 13 Time Overdrive speed, VPUP > 4.5V 1 5 Overdrive speed 1 6.7 Presence Detect Low t PDL Standard speed 60 285 µs 13 Time Overdrive speed, VPUP > 4.5V 7.3 24 Overdrive speed 7.3 28 Presence Detect t MSP Standard speed 60 75 µs 1, 14 Sample Time Overdrive speed, VPUP > 4.5V 5 8.3 Overdrive speed 6.7 8.3 I/O PIN, 1-WIRE WRITE Write-0 Low Time t W0L Standard speed 60 120 13, 1 Overdrive speed, VPUP > 4.5V 5 14 Overdrive speed 7 14 Write-1 Low Time t W1L Standard speed 5 15 - /g101µs 1, 11, 13 Overdrive speed, VPUP > 4.5V 1 2 - /g101 Overdrive speed 1 1.85 - /g101 Write Sample Time (Slave Sampling) tSLS Standard speed 15 60 µs 13 Overdrive speed, VPUP > 4.5V 25 Overdrive speed 1.85 7 I/O PIN, 1-WIRE READ Read Low Time t RL Standard speed 5 15 - /g100µs 1, 12,13 Overdrive speed, VPUP > 4.5V 1 2 - /g100 Overdrive speed 1 1.85 - /g100 Read-0 Low (Data from Slave) tSPD Standard speed 15 60 µs 13 Overdrive speed, VPUP > 4.5V 25 Overdrive speed 1.85 7 Read Sample Time t MSR Standard speed tRL + /g100 15 µs 1, 12, 13 Overdrive speed, VPUP > 4.5V tRL + /g100 2 Overdrive speed tRL + /g100 1.85 EEPROM Programming Current I LPROG 700 µA 14 Programming Time t PROG 10 ms Write/Erase Cycles N CYCLE 50k — 14 Data Retention t RET +85°C, not powered 10 years

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES SHA-1 ENGINE Computation Current I LCSHA 4.5 mA 14 Computation Time t CSHA 1.5 ms NOTES: 1) System requirement. 2) Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required. 3) Capacitance on the data pin could be 800pF when power is first applied. If a 5k/g87 resistor is used to pull up the data line to V PUP; the parasite capacitance does not affect normal communications 5µs after power has been applied. 4) Input load is to ground. 5) All voltages are referenced to ground. 6) V TL, VTH are a function of the internal supply voltage. 7) Voltage below which, during a falling edge on I/O, a logic 0 is detected. 8) The voltage on I/O needs to be less or equal to V ILMAX whenever the master drives the line low. 9) Voltage above which, during a rising edge on I/O, a logic 1 is detected. 10) The I-V characteristic is linear for voltages less than 1V. 11) /g101 is the time required for the pullup circuitry to pull the voltage on I/O up from V IL to VTH. 12) /g100 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high threshold of the bus master. 13) Highlighted numbers are not in compliance with the published iButton standards. See comparison table below. 14) Guaranteed by design, not production tested STANDARD VALUES DS1961S VALUES PARAMETER STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED NAME MIN MAX MIN MAX MIN MAX MIN MAX tRSTL 480µs (undef.) 48µs 80µs 720µs 960µs 68µs 80µs tPDH 15µs 60µs 2µs 6µs 15µs 60µs 1µs 6.7µs tPDL 60µs 240µs 8µs 24µs 60µs 285µs 7.3µs 24µs tW0L 60µs 120µs 6µs 16µs 60µs 120µs 7µs 14µs tSLS, tSPD 15µs 60µs 2µs 6µs 15µs 60µs 1.85µs 7µs