DS1805 MAXIM | Alldatasheet

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Technical content

Features

♦ 3V or 5V Operation ♦ Low Power Consumption ♦ One Digitally Controlled, 256-Position Potentiometer ♦ Compatible with DS1803-Based Designs ♦ 14-Pin TSSOP (173mil) and 16-Pin SO (150mil) Available for Surface-Mount Applications ♦ Three Address Inputs ♦ Serial 2-Wire Bus ♦ Operating Temperature Range Industrial: -40°C to +85°C ♦ Standard Resistance Values DS1805-010: 10kΩ DS1805-050*: 50kΩ DS1805-100*: 100kΩ DS1805 Addressable Digital Potentiometer VCC N.C. N.C. N.C.A2 TOP VIEW N.C. SDA SCLGND

14 TSSOP (173mil)

N.C. N.C. N.C. N.C. N.C. SDA SCL

16 SO (150mil)

N.C. GND DS1805Z Pin Configurations Ordering Information PART TEM P RANGE PIN- PACKAGE RESISTANCE ( KΩ) DS1805E-010 -40°C to +85°C 14 TSSOP (173mil) 10 DS1805E-050* -40°C to +85°C 14 TSSOP (173mil) 50 DS1805E-100* -40°C to +85°C 14 TSSOP (173mil) 100 DS1805Z-010 -40°C to +85°C 16 SO (150mil) 10 DS1805Z-050* -40°C to +85°C 16 SO (150mil) 50 DS1805Z-100* -40°C to +85°C 16 SO (150mil) 100 XX-XXXX; Rev 0; 4/02 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Add “/T&R” for tape-and-reel orders. *Future product.

Addressable Digital Potentiometer ABSOLUTE MAXIMUM RATINGS RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. J-STD-020A Specification PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC (Note 1) 2.7 5.5 V Resistor Inputs L, H, W (Note 1) -0.3 VCC + 0.3 V DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V to 5.5V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current Active I CC (Note 2) 200 µA Input Leakage I IL -1 +1 µA Wiper Resistance R W 400 1000 Ω Wiper Current I W 1m A Input Logic 1 V IH 0.7VCC VCC + 0.3 V Input Logic 0 V IL GND - 0.3 0.3VCC V Input logic 1 0.7VCC VCC + 0.3Input Logic Levels A0, A1, A2 (Note 3) Input logic 0 GND - 0.3 0 . 2 5 V C C V Input Current each I/O Pin (Note 4) 0.4V < VI/O < 0.9VCC -10 +10 µA Standby Current I STBY (Note 5) 20 40 µA VOL1 3mA sink current 0 0.4 VLow-Level Output Voltage VOL2 6mA sink current 0 0.6 V I/O Capacitance C I/0 10 pF Pulse Width of Spikes that Must be Suppressed by the Input Filter tSP Fast mode 0 50 ns

Addressable Digital Potentiometer ANALOG RESISTOR CHARACTERISTICS (VCC = 2.7V to 5.5V, TA = -40°C to +85°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS End-to-End Resistor Tolerance (Note 6) -20 +20 % Absolute Linearity (Note 7) -0.75 +0.75 LSB Relative Linearity (Note 8) -0.3 +0.3 LSB -3dB Cutoff Frequency fCUTOFF (Note 9) Hz Ratiometric Temperature Coefficient 8 ppm/°C End-to-End Temperature Coefficient 550 ppm/°C Capacitance CI 5p F AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V to 5.5V, TA = -40°C to +85°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Fast mode 0 400SCL Clock Frequency (Note 10) f SCL Standard mode 0 100 kHz Fast mode 1.3Bus Free Time Between STOP and START Condition (Note 10) tBUF Standard mode 4.7 µs Fast mode 0.6Hold Time (Repeated) START Condition (Notes 10, 11) tHD:STA Standard mode 4.0 µs Fast mode 1.3Low Period of SCL Clock (Note 10) tLOW Standard mode 4.7 µs Fast mode 0.6High Period of SCL Clock (Note 10) tHIGH Standard mode 4.0 µs Fast mode 0 0.9Data Hold Time (Notes 10, 12, 13) tHD:DAT Standard mode 0 0.9 µs Fast mode 100Data Setup Time (Note 10) tSU:DAT Standard mode 250 ns Fast mode 20 + 0.1CB 300Rise Time of Both SDA and SCL Signals (Notes 10, 14) tR Standard mode 20 + 0.1CB 1000 ns Fast mode 20 + 0.1CB 300Fall Time of Both SDA and SCL Signals (Notes 10, 14) tF Standard mode 20 + 0.1CB 300 ns Fast mode 0.6Setup Time for STOP Condition (Note 10) tSU:STO Standard mode 4.0 µs Capacitive Load for Each Bus Line (Note 14) CB 400 pF

Addressable Digital Potentiometer Note 1: All voltages are referenced to ground. Note 2: ICC specified with SDA pin open. SCL = 400kHz clock rate. Note 3: Address inputs A0, A1, and A2 should be connected to either VCC or GND, depending on the desired address selections. Note 4: I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off. Note 5: ISTBY specified with SDA = SCL = VCC = 5.0V. Note 6: Valid at +25°C only. Note 7: Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper position. Note 8: Relative linearity is used to determine the change in voltage between successive tap positions. Note 9: -3dB cutoff frequency characteristics for the DS1805 depend on potentiometer total resistance: DS1805-010, 1MHz; DS1805-50, 200kHz; DS1805-100, 100kHz. Note 10: A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. Note 11: After this period, the first clock pulse is generated. Note 12: The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 13: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. Note 14: CB—total capacitance of one bus line in picofarads, timing referenced to (0.9)(V CC) and (0.1)(VCC). AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V to 5.5V, TA = -40°C to +85°C)

Typical Operating Characteristics (VCC = 5.0V, TA = +25°C, unless otherwise noted.) DS1805 Addressable Digital Potentiometer VOLTAGE-DIVIDER ABSOLUTE LINEARITY vs. WIPER SETTING (10kΩ) DS1805 toc07 WIPER SETTING ABSOLUTE LINEARITY (LSB) 20015050 100 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.02 0 250 VOLTAGE-DIVIDER RELATIVE LINEARITY vs. WIPER SETTING (10kΩ) DS1805 toc08 WIPER SETTING RELATIVE LINEARITY (LSB) 20015010050 0.01 0.02 0.03 0.04 0.05 0.06 -0.01 0 250 ACTIVE SUPPLY CURRENT vs. SCL FREQUENCY DS1805 toc06 SCL FREQUENCY (kHz) ACTIVE SUPPLY CURRENT (µA) 300200100 0 400 SDA = VCC A0, A1, A2, L1 = GND W1, H1 = NO CONNECT END-TO-END RESISTANCE TEMPERATURE CHANGE vs. TEMPERATURE DS1805 toc05 TEMPERATURE (°C) END-TO-END RESISTANCE % CHANGE 6040-20 0 20 -40 80 TC = 530ppm/°C 10kΩ, WORST CASE VOLTAGE DIVIDER PERCENT CHANGE (FROM +25°C) vs. TEMPERATURE (RATIOMETRIC TC) DS1805 toc04 TEMPERATURE (°C) % CHANGE (FROM +25°C) 6040200-20 -0.04 -0.02 0.02 0.04 0.06 -0.06 -40 80 10kΩ POT WIPER = BFh WIPER = BFh WIPER = 3Fh WIPER = 3Fh WIPER = 7Fh TC = 1.3ppm/°C TC = 8.1ppm/°C WIPER RESISTANCE vs. WIPER VOLTAGE (10kΩ) DS1805 toc03 WIPER VOLTAGE (V) WIPER RESISTANCE (Ω) 4321 100 150 200 250 300 350 VCC = 3V VCC = 5V W-L RESISTANCE vs. WIPER SETTING DS1805 toc02 WIPER SETTING W-L RESISTANCE (kΩ) 225200175150125100755025 0 250 10kΩ POTENTIOMETER SUPPLY CURRENT vs. TEMPERATURE DS1805 toc01 TEMPERATURE (°C) SUPPLY CURRENT (µA) 6040200-20 -40 80 VCC = 5V VCC = 3V

single 256-position digitally controlled potentiometer. device that has a single 256-position potentiometer. Figure 1 shows a block diagram of the part. the device chip-select inputs A0, A1, and A2. Figure 1. Functional Diagram

11 H 1 High End of

23 L 1 Low End of

34 W 1 Wiper Terminal of

78 GND Ground

89 SCL Serial Clock Input

255), while the lowest setting, 00h, connects to L1. value to a desired position. data terminal, SDA, and the serial clock input, SCL. in the 2-Wire Serial Data Bus section. with A0, A1, and A2 being the address of the device. the industrial (-40°C to +85°C) temperature range. cannot exceed the operating power supply of the device. made through the open-drain I/O lines, SDA and SCL.

  • Data transfer can be initiated only when the bus is not busy.
  • During data transfer, the data line must remain sta- ble whenever the clock line is high. Changes in the data line while the clock line is high will be interpret- ed as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low while the clock is high defines a START condition. STOP CONDITION OR REPEATED START CONDITION REPEATED IF MORE BYTES ARE TRANSFERED ACKSTART CONDITION ACK ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SLAVE ADDRESS MSB SCL SDA R/W DIRECTION BIT 12 6 7 8 9 1 2 89 3–7

Figure 2. 2-Wire Data Transfer Overview

ble for the duration of the high period of the clock signal. W bit, two types of data transfer are possible. each receiver acknowledges with a ninth bit. defined. The DS1805 works in both modes. byte, a ‘not acknowledge’ is returned. by the DS1805 while the serial clock is input on SCL. beginning and end of a serial transfer. to select which of eight devices are to be accessed. Figure 3. Control Byte