DS1742 MAXIM | Alldatasheet
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Y2KC Nonvolatile Timekeeping RAM www.maxim-ic.com
FEATURES
Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit and Lithium Energy Source 1 of 16 REV: 102808 Clock Registers are Accessed Identically to the Static RAM; These Registers are Resident in the Eight Top RAM Locations Century Byte Register Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power BCD Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap Year Compensation Valid Up to the year 2100 Battery Voltage Level Indicator Flag Power-Fail Write Protection Allows for ±10% V CC Power Supply Tolerance Lithium Energy Source is Electrically Disconnected to Retain Freshness until Power is Applied for the First Time Standard JEDEC Bytewide 2k x 8 Static RAM Pinout Quartz Accuracy ±1 Minute a Month at +25°C, Factory Calibrated Underwriters Laboratories (UL®) Recognized PIN CONFIGURATION VCC WE OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ0 DQ1 DQ2 GND DS1742 ENCAPSULATED DIP TOP VIEW
ORDERING INFORMATION
PART VOLTAGE (V) TEMP RANGE PIN-PACKAGE TOP MARK DS1742-85 5.0 0°C to +70°C 24 EDIP (0.740a) DS1742-85 DS1742-85+ 5.0 0°C to +70°C 24 EDIP (0.740a) DS1742-85+ DS1742-100 5.0 0°C to +70°C 24 EDIP (0.740a) DS1742-100 DS1742-100+ 5.0 0°C to +70°C 24 EDIP (0.740a) DS1742-100+ DS1742-100IND 5.0 -40°C to +85°C 24 EDIP (0.740a) DS1742-100IND DS1742-100IND+ 5.0 -40°C to +85°C 24 EDIP (0.740a) DS1742-100IND+ DS1742W-120 3.3 0°C to +70°C 24 EDIP (0.740a) DS1742W-120 DS1742W-120+ 3.3 0°C to +70°C 24 EDIP (0.740a) DS1742W-120+ DS1742W-150 3.3 0°C to +70°C 24 EDIP (0.740a) DS1742W-150 DS1742W-150+ 3.3 0°C to +70°C 24 EDIP (0.740a) DS1742W-150+ +Denotes a lead-free/RoHS-compliant device. The top mark will include a “+” on lead-free devices. UL is a registered trademark of Underwriters Laboratories, Inc.
19 A10
9 DQ0
10 DQ1
11 DQ2
13 DQ3
14 DQ4
15 DQ5
16 DQ6
17 DQ7
12 GND Ground
18 CE Active-Low Chip-Enable Input
20 OE Active-Low Output-Enable Input
21 WE Active-Low Write-Enable Input
24 VCC Power-Supply Input
DESCRIPTION
The DS1742 is a full-function, ye ar 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 2k x 8 nonvolatile static RAM. User access to all registers within the DS1742 is accomplished with a bytewide interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations. The RTC regist ers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD fo rmat. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double-buffered to av oid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by acce ss to time register data. The DS1742 also contains its own power-fail circuitry, which deselects the device when the V CC supply is in an out-of-tolerance condition. Th is feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.
Figure 1. DS1742 BLOCK DIAGRAM Table 1. TRUTH TABLE
transfers those values to the actual clock counters and allows normal operation to resume. seconds registers, see Table 2. Setting it to a 1 stops the oscillator. seconds register remain valid and stable). the PCB layout. For additional information refer to Application Note 58. Table 2. REGISTER MAP
5 B B BB
Note: All indicated “X” bits are not used but must be set to “0” during write cycle to ensure proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK The DS1742 is in th e read mode whenever OE (output enable) is low, WE (write enable) is high, and CE (chip enable) is low. The device architec ture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within t AA after the last address input is stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and states are not met, valid data will be available at the latter of chip enable access (t CEA) or at output enable access time (t OEA). The state of the data input/output pins (DQ) is controlled by CE , and OE . If the outputs are activated before t AA, the data lines are driven to an intermediate state until t AA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK The DS1742 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE on CE . The addresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of t WR prior to the initiation of another r ead or write cycle. Data in must be valid t DS prior to the end of write and remain valid for t DH afterward. In a typi cal application, the OE signal will be hi gh during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs t WEZ after WE goes active. DATA RETENTION MODE The 5V device is fully accessible and data can be written or read only when V CC is greater than VPF. However, when V CC is below the pow er fail point, V PF, (point at which write protection occurs) the internal clock registers and SR AM are blocked from any access. When V CC falls below the battery switch point V SO (battery supply level), device power is switched from the V CC pin to the backup battery. RTC operation and SRAM data are main tained from the battery until VCC is returned to nominal levels. The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF. When VCC falls below the power fail point, V PF, access to the device is inhibited. If V PF is less than Vso , the device power is switched from V CC to the backup supply (VBAT) when VCC drops below VPF. If VPF is greater than Vso , the device power is switched from V CC to the backup supply (V BAT) when V CC drops below Vso . RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The DS1742 has a lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the V CC supply is not present. T he capability of this internal power supply is sufficient to power the DS1742 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscill ator running in the absence of V CC power. Each DS1742 is shipped from Dallas Semiconductor with its lith ium energy source disconnected, guaranteeing full energy capacity. When V CC is first applied at a level greater than V PF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1742 will be much longer than 10 years since no lithium battery energy is consumed when VCC is present. BATTERY MONITOR The DS1742 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of the day register is us ed to indicate the voltage level range of the battery. This bit is not writable and should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are questionable.
Voltage Range on Any Pin Relative to Ground……………………………………..-0.3V to +6.0V Soldering Temperature (EDIP, leads)..……………………..+260 °C for 10 seconds (See Note 7) This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operation sections of this specif ication is not implied. Exposure to absolute ma ximum rating conditions for extended periods of time may affect reliability. OPERATING RANGE RANGE TEMPERATURE VCC Commercial 0°C to +70°C (noncondensing) 3.3V ±10% or 5V ±10% Industrial -40°C to +85°C (noncondensing) 3.3V ±10% or 5V ±10% RECOMMENDED DC OPERATING CONDITIONS (Over the operating range) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES VCC = 5V ±10% VIH 2.2 VCC + 0.3V V 1 Logic 1 Voltage (All Inputs) VCC = 3.3V ±10% VIH 2.0 VCC + 0.3V V 1 VCC = 5V ±10% VIL -0.3 +0.8 V 1 Logic 0 Voltage (All Inputs) VCC = 3.3V DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±10%, Over the operating range.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current ICC 15 50 mA 2, 3 TTL Standby Current ( CE = VIH) ICC1 1 3 mA 2, 3 CMOS Standby Current ( CE ≥VCC - 0.2V) ICC2 1 3 mA 2, 3 Input Leakage Current (Any Input) IIL -1 +1 A Output Leakage Current (Any Output) IOL -1 +1 A Output Logic 1 Voltage (IOUT = -1.0mA) VOH 2.4 1 Output Logic 0 Voltage (IOUT = +2.1mA) VOL 0.4 1 Write Protection Voltage VPF 4.25 4.50 V 1 Battery Switchover Voltage VSO VBAT 1, 4
DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, Over the operating range.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current ICC 10 30 mA 2, 3 TTL Standby Current ( CE = VIH) ICC1 0.7 2 mA 2, 3 CMOS Standby Current ( CE ≥VCC - 0.2V) ICC2 0.7 2 mA 2, 3 Input Leakage Current (any input) IIL -1 +1 A Output Leakage Current (Any Output) IOL -1 +1 A Output Logic 1 Voltage (IOUT = -1.0mA) VOH 2.4 1 Output Logic 0 Voltage (IOUT =2.1mA) VOL 0.4 1 Write Protection Voltage VPF 2.80 2.97 V 1 Battery Switchover Voltage VSO VBAT or VPF V 1, 4 AC CHARACTERISTICS—READ CYCLE (5V) (VCC = 5.0V ±10%, Over the operating range.) 85ns ACCESS 100ns ACCESS UNITS PARAMETER SYMBOL MIN MAX MIN MAX Read Cycle Time tRC 85 100 ns Address Access Time tAA 85 100 ns CE to DQ Low-Z tCEL 5 5 ns CE Access Time tCEA 85 100 ns CE Data Off time tCEZ 30 35 ns OE to DQ Low-Z tOEL 5 5 ns OE Access Time tOEA 45 55 ns OE Data Off Time tOEZ 30 35 ns Output Hold from Address tOH 5 5 ns
AC CHARACTERISTICS—READ CYCLE (3.3V) (VCC = 3.3V ±10%, Over the operating range.) 120ns ACCESS 150ns ACCESS PARAMETER SYMBOL MIN MAX MIN MAX UNITS Read Cycle Time tRC 120 150 ns Address Access Time tAA 120 150 ns CE to DQ Low-Z tCEL 5 5 ns CE Access Time tCEA 120 150 ns CE Data Off time tCEZ 40 50 ns OE to DQ Low-Z tOEL 5 5 ns OE Access Time tOEA 100 130 ns OE Data Off Time tOEZ 35 35 ns Output Hold from Address tOH 5 5 ns READ CYCLE TIMING DIAGRAM
AC CHARACTERISTICS—WRITE CYCLE (5V) (VCC = 5.0V ±10%, Over the operating range.) 85ns ACCESS 100ns ACCESS PARAMETER SYMBOL MIN MAX MIN MAX UNITS Write Cycle Time tWC 85 100 ns Address Access Time tAS 0 0 ns WE Pulse Width tWEW 65 70 ns CE Pulse Width tCEW 70 75 ns Data Setup Time tDS 35 40 ns Data Hold time tDH 0 0 ns Address Hold Time tAH 5 5 ns WE Data Off Time tWEZ 30 35 ns Write Recovery Time tWR 5 5 ns AC CHARACTERISTICS—WRITE CYCLE (3.3V) (VCC = 3.3V ±10%, Over the operating range.) 120ns ACCESS 150ns ACCESS PARAMETER SYMBOL MIN MAX MIN MAX UNITS Write Cycle Time tWC 120 150 ns Address Setup Time tAS 0 0 ns WE Pulse Width tWEW 100 130 ns CE Pulse Width tCEW 110 140 ns Data Setup Time tDS 80 90 ns Data Hold Time tDH 0 0 ns Address Hold Time tAH 0 0 ns WE Data Off Time tWEZ 40 50 ns Write Recovery Time tWR 10 10 ns
WRITE CYCLE TIMING DIAGRAM— WRITE-ENABLE CONTROLLED WRITE CYCLE TIMING DIAGRAM—CHIP-ENABLE CONTROLLED
POWER-UP/POWER-DOWN CHARACTERISTICS (5V) (VCC = 5.0V ±10%, Over the operating range.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CE or WE at VIH, Before Power-Down tPD 0 μs VCC Fall Time: VPF(MAX) to VPF(MIN) tF 300 μs VCC Fall Time: VPF(MIN) to VSO tFB 10 μs VCC Rise Time: VPF(MIN) to VPF(MAX) tR 0 μs Power-Up Recover Time tREC 35 ms Expected Data Retention Time (Oscillator On) 10 tDR years 5, 6 POWER-UP/POWER-DOWN WAVEFORM TIMING (5V DEVICE)
POWER-UP/POWER-DOWN CHARACTERISTICS (3.3V) (VCC = 3.3V ±10%, Over the operating range.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CE or WE at VIH, Before Power- Down tPD 0 s VCC Fall Time: VPF(MAX) to VPF(MIN) tF 300 s VCC Rise Time: VPF(MIN) to VPF(MAX) tR 0 s Power-Up Recovery Time tREC 35 ms Expected Data Retention Time tDR 10 years 5, 6 (Oscillator On) POWER-UP/POWER-DOWN WAVEFORM TIMING (3.3V DEVICE) CAPACITANCE (TA = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Capacitance on All Input Pins CIN 7 pF Capacitance on All Output Pins CO 10 pF
Output Load: 100pF + 1TTL Gate Input Pulse Levels: 0.0 to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1) Voltage referenced to ground. 2) Typical values are at 25°C and nominal supplies. 3) Outputs are open. 4) Battery switchover occurs at the lower of either the battery voltage or VPF. 5) Data retention time is at 25°C. 6) Each DS1742 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as a cumulative time in the absence of VCC starting from the time power is first applied by the user. 7) Real-time clock modules can be successfully processed through conventional wave- soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post-solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used to prevent damage to the crystal.
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
REVISION HISTORY
Added “UL Recognized” bullet to Features and new Ordering Information table. 1 Added new Pin Description table. 2 Updated note for Table 2 4 041305 updated Operating Temperature Range for Absolute Maximum Ratings. 7
071905 Corrected 24-pin to 28-pin package and top mark items in
Ordering Information table. 1
060706 Removed reference to J-STD-020 and indicated the lead
soldering temperature of +260°C for 10 seconds max. 7
022207 Added DS1742-85, DS1742-85+ to the Ordering Information
table; removed DS1742P-100+ (PowerCap) package. 1
102808 Removed the –70 ordering numbers from the Ordering
Information table. 1