DS15BR400

DS15BR400 NSC | Alldatasheet

Document overview

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Technical content

Features

n DC to 2 Gbps low jitter, high noise immunity, low power operation n 6 dB of pre-emphasis drives lossy backplanes and cables n LVDS/CML/LVPECL compatible input, LVDS output n On-chip 100 Ω output termination, optional 100 Ω input termination n 15 kV ESD protection on LVDS inputs and outputs n Single 3.3V supply n Industrial -40 to +85˚C temperature range n Space saving LLP-32 or TQFP-48 packages n Evaluation Kit Available

Applications

n Cable extention applications n Signal repeating and buffering n Digital routers Typical Application 20188950 September 2006 DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis © 2006 National Semiconductor Corporation DS201889 www.national.com

Block and Connection Diagrams 20188901 DS15BR400 Block Diagram 20188903 DS15BR401 Block Diagram 20188902 TQFP Pinout - Top View 20188912 LLP Pinout - Top View DS15BR400/DS15BR401 www.national.com 2

Number I/O, Type Description DIFFERENTIAL INPUTS IN0+ IN0− I, LVDS Channel 0 inverting and non-inverting differential inputs. IN1+ IN1− I, LVDS Channel 1 inverting and non-inverting differential inputs. IN2+ IN2− I, LVDS Channel 2 inverting and non-inverting differential inputs. IN3+ IN3− I, LVDS Channel 3 inverting and non-inverting differential inputs. DIFFERENTIAL OUTPUTS OUT0+ OUT0− O, LVDS Channel 0 inverting and non-inverting differential outputs. (Note 2) OUT1+ OUT1− O, LVDS Channel 1 inverting and non-inverting differential outputs. (Note 2) OUT2+ OUT2− O, LVDS Channel 2 inverting and non-inverting differential outputs. (Note 2) OUT3+ OUT3- O, LVDS Channel 3 inverting and non-inverting differential outputs. (Note 2) DIGITAL CONTROL INTERFACE PWDN 12 8 I, LVTTL A logic low at PWDN activates the hardware power down mode (all channels). PEM 2 2 I, LVTTL Pre-emphasis Control Input (affects all Channels) POWER V DD 3, 4, 5, 7, 10, 11, 28, 29, 32, 3, 4, 6, 7, 20, 21 I, Power V DD = 3.3V, ±10% GND 8, 9, 17, 18, 23, 24, 37, 38, 43, 5 (Note 1) I, Ground Ground reference for LVDS and CMOS circuitry. For the LLP package, the DAP is used as the primary GND connection to the device in addition to the pin numbers listed. The DAP is the exposed metal contact at the bottom of the LLP-32 package. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance. 30, 31, 34, 35, 1, 17, 18,19,22, 23, 24 No Connect Note 1: Note that for the LLP package the GND is connected thru the DAP on the back side of the LLP package in addition to the actual pin numbers listed. Note 2: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15BR400 and DS15BR401 are optimized for point-to-point backplane and cable applications. DS15BR400/DS15BR401 www.national.com3

Absolute Maximum Ratings(Note 3) Supply Voltage (VDD) −0.3V to +4.0V CMOS Input Voltage −0.3V to (V DD+0.3V) LVDS Receiver Input Voltage −0.3V to (V DD+0.3V) LVDS Driver Output Voltage −0.3V to (V DD+0.3V) LVDS Output Short Circuit Current +40 mA Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Solder, 4sec) 260˚C Max Pkg Power Capacity @ 25˚C TQFP LLP 1.64W 4.16W Thermal Resistance (θ JA) TQFP LLP 76˚C/W 30˚C/W Package Derating above +25˚C TQFP LLP 13.2mW/˚C 33.3mW/˚C ESD Last Passing Voltage HBM, 1.5kΩ, 100pF 8 kV LVDS pins to GND only 15 kV EIAJ, 0Ω, 200pF 250V Charged Device Model 1000V Recommended Operating Conditions Supply Voltage (VCC) 3.0V to 3.6V Input Voltage (VI) (Note 4) 0V to V CC Output Voltage (VO) 0 Vt oV CC Operating Temperature (TA) Industrial −40˚C to +85˚C Note 3: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recom- mend operation of products outside of recommended operation conditions. Note 4: V ID max < 2.4V

Electrical Characteristics

Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note Max Units LVCMOS DC SPECIFICATIONS(PWDN, PEM) VIH High Level Input Voltage 2.0 V DD V VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current V IN =V DD = 3.6V (PWDN pin) −10 +10 µA IIHR High Level Input Current V IN =V DD = 3.6V (PEM pin) 40 200 µA IIL Low Level Input Current V IN =V SS,V DD = 3.6V −10 +10 µA CIN1 LVCMOS Input Capacitance Any Digital Input Pin to V SS 5.5 pF VCL Input Clamp Voltage I CL = −18 mA, V DD = 0V −1.5 −0.8 V LVDS INPUT DC SPECIFICATIONS(INn±) VTH Differential Input High Threshold (Note 6) VCM = 0.8V to 3.55V, VDD = 3.6V 0 100 mV VTL Differential Input Low Threshold (Note 6) VCM = 0.8V to 3.55V, VDD = 3.6V −100 0 mV VID Differential Input Voltage V CM = 0.8V to 3.55V, V DD = 3.6V 100 2400 mV VCMR Common Mode Voltage Range VID = 150 mV, V DD = 3.6V 0.05 3.55 V CIN2 LVDS Input Capacitance IN+ or IN− to V SS 3.0 pF IIN Input Current V IN = 3.6V, VDD = 3.6V −10 +10 µA VIN = 0V, VDD = 3.6V −10 +10 µA DS15BR400/DS15BR401 www.national.com 4

Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note Max Units LVDS OUTPUT DC SPECIFICATIONS(OUTn±) VOD Differential Output Voltage, 0% Pre-emphasis (Note 6) RL = 100Ω external resistor between OUT+ and OUT− Figure 1 250 360 500 mV ∆VOD Change in VOD between Complementary States −35 35 mV VOS Offset Voltage (Note 7) 1.05 1.18 1.475 V ∆VOS Change in VOS between Complementary States −35 35 mV COUT LVDS Output Capacitance OUT+ or OUT− to V SS 2.5 pF IOS Output Short Circuit Current OUT+ or OUT− Short to GND −21 −40 mA OUT+ or OUT− Short to VDD 6 40 mA SUPPLY CURRENT (Static) I CC Supply Current All inputs and outputs enabled and active, terminated with differential load of 100 Ω between OUT+ and OUT-. P E M=L 175 215 mA ICCZ Supply Current - Power Down Mode P W D N=L ,P E M=L 20 200 µA SWITCHING CHARACTERISTICS — LVDS OUTPUTS tLHT Differential Low to High Transition Time (Note 12) Use an alternating 1 and 0 pattern at 200 Mbps, measure between 20% and 80% of V OD. Figures 2, 4 170 250 ps tHLT Differential High to Low Transition Time (Note 12) 170 250 ps tPLHD Differential Low to High Propagation Delay Use an alternating 1 and 0 pattern at 200 Mbps, measure at 50% VOD between input to output. Figures 2, 3 1.0 2.0 ns tPHLD Differential High to Low Propagation Delay 1.0 2.0 ns tSKD1 Pulse Skew (Note 12) |t PLHD–tPHLD|1 0 6 0 p s tSKCC Output Channel to Channel Skew (Note 12) Difference in propagation delay (t PLHD or tPHLD) among all output channels. 25 75 ps tSKP Part to Part Skew (Note 12) Common edge, parts at same temp and V CC 550 ps tJIT Jitter (0% Pre-emphasis) (Note 8) RJ - Alternating 1 and 0 at 750 MHz (Note 9) 0.5 1.5 ps DJ - K28.5 Pattern, 1.5 Gbps (Note 10) 14 30 ps TJ - PRBS 2 23-1 Pattern, 1.5 Gbps (Note 11) 14 31 ps tON LVDS Output Enable Time Time from PWDN to OUT ± change from TRI-STATE to active. Figures 5, 6 20 µs tOFF LVDS Output Disable Time Time from PWDN to OUT ± change from active to TRI-STATE. Figures 5, 6 12 ns Note 5: Typical parameters are measured at V DD = 3.3V, TA = 25˚C. They are for reference purposes, and are not production-tested. Note 6: Differential output voltage V OD is defined as ABS(OUT+–OUT−). Differential input voltage V ID is defined as ABS(IN+–IN−). Note 7: Output offset voltage V OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Note 8: Jitter is not production tested, but guaranteed through characterization on a sample basis. Note 9: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. Stimulus and fixture Jitter has been subtracted. The inpu t voltage = VID = 500 mV, input common mode voltage = V ICM = 1.2V, 50% duty cycle at 750 MHz, t r =t f = 50 ps (20% to 80%). Note 10: Deterministic Jitter, or DJ, is a peak to peak value. Stimulus and fixture jitter has been subtracted. The input voltage = VID = 500 mV, input common mode Note 11: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been subtracted. The input voltage =V ID = 500 mV, input common mode voltage = V ICM = 1.2V, 223-1 PRBS pattern at 1.5 Gbps, t r =t f = 50 ps (20% to 80%). Note 12: Not production tested. Guaranteed by a statistical analysis on a sample basis at the time of characterization. DS15BR400/DS15BR401 www.national.com5

Application Information

The DS15BR400 has integrated termination resistors on both the input and outputs. The inputs have a 100 Ω resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the device. The LVDS outputs also contain an integrated 100 Ω ohm termi- nation resistor, this resistor is used to minimize the output return loss and does not take the place of the 100 ohm termination at the inputs to the receiving device. The inte- grated terminations improve signal integrity and decrease the external component count resulting in space savings. The DS15BR401 has 100 Ω output terminations only. OUTPUT CHARACTERISTICS The output characteristics of the DS15BRB400/DS15BR401 have been optimized for point-to-point backplane and cable applications, and are not intended for multipoint or multidrop signaling. POWERDOWN MODE The PWDN input activates a hardware powerdown mode. When the powerdown mode is active (PWDN=L), all input and output buffers and internal bias circuitry are powered off. When exiting powerdown mode, there is a delay associated with turning on bandgap references and input/output buffer circuits as indicated in the LVDS Output Switching Charac- teristics PRE-EMPHASIS Pre-emphasis dramatically reduces ISI jitter from long or lossy transmission media. One pin is used to select the pre-emphasis level for all outputs, off or on. The pre- emphasis boost is approximately 6 dB at 750 MHz. Pre-emphasis Control Selection Table PEM Pre-Emphasis 0O f f 1O n INPUT FAILSAFE BIASING External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to V DD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point ideally should be set to approximately 1.2V. Please refer to application note AN- 1194 “Failsafe Biasing of LVDS Interfaces” for more informa- tion. DECOUPLING Each power or ground lead of the DS15BR400 should be connected to the PCB through a low inductance path. For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally, via placement is immediately adjacent to the pin to avoid adding trace induc- tance. Placing power plane closer to the top of the board reduces effective via length and its associated inductance. Bypass capacitors should be placed close to VDD pins. Small physical size capacitors, such as 0402, X7R, surface mount capacitors should be used to minimize body induc- tance of capacitors. Each bypass capacitor is connected to the power and ground plane through vias tangent to the pads of the capacitor. An X7R surface mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above 30 MHz or so, X7R capacitors behave as low imped- ance inductors. To extend the operating frequency range to a few hundred MHz, an array of different capacitor values like 100 pF, 1 nF, 0.03 µF, and 0.1 µF are commonly used in parallel. The most effective bypass capacitor can be built using sandwiched layers of power and ground at a separa- tion of 2–3 mils. With a 2 mil FR4 dielectric, there is approxi- mately 500 pF per square inch of PCB. The center dap of the LLP package housing the DS15BR400 should be connected to a ground plane through an array of vias. The via array reduces the effective inductance to ground and enhances the thermal performance of the LLP package. DS15BR400/DS15BR401 www.national.com 8

Typical Performance Characteristics Power Supply Current vs. Data Rate 20188920 Total Jitter vs. Ambient Temperature 20188921 Total Jitter vs. Data Rate 20188922 Data Rate vs. Cable Length (0.25 UI Criteria) 20188923 Data presented in this graph was collected using the DS15BR400EVK, a pair of RJ-45 to SMA adapter boards and various length Belden 1700a cables. The maximum data rate was determined based on total jitter (0.25 UI criteria) measured after the cable. The total jitter was a peak to peak value measured with a histogram including 3000 window hits. Data Rate vs. Cable Length (0.5 UI Criteria) 20188924 Data presented in this graph was collected using the DS15BR400EVK, a pair of RJ-45 to SMA adapter boards and various length Belden 1700a cables. The maximum data rate was determined based on total jitter (0.5 UI criteria) measured after the cable. The total jitter was a peak to peak value measured with a histogram including 3000 window hits. DS15BR400/DS15BR401 www.national.com9

Physical Dimensions inches (millimeters) unless otherwise noted 48-TQFP Order Number DS15BR400TVS, DS15BR401TVS (250 piece Tray) Order Number DS15BR400TVSX, DS15BR401TVSX (1000 piece Tape and Reel) DS15BR400/DS15BR401 www.national.com 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 32-LLP (See AN-1187 for PCB Design and Assembly Recommendations) Order Number DS15BR400TSQ, DS15BR401TSQ (1000 piece Tape and Reel) DS15BR400TSQX, DS15BR401TSQX (4500 piece Tape and Reel) National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/quality/green. Lead free products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis