DS15BA101 TI | Alldatasheet
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150 Mbps
1.5 Gbps
100-ohm Differential Cable (i.e. CAT5e/6/7, Twinax) 50-ohm Coaxial Cable (i.e. Belden 9914) Max Cable Loss ~ 35 dB @ 750 MHz DS15BA101 www.ti.com SNLS234J –OCTOBER 2006–REVISED APRIL 2013 DS15BA1011.5GbpsDifferentialBufferwithAdjustableOutputVoltage Check forSamples: DS15BA101 1FEATURES DESCRIPTION The DS15BA101 isa high-speeddifferentialbufferfor 2• Data Rates from DC to1.5+Gbps cabledriving,leveltranslation,signalbuffering,and• Differentialor Single-endedInput signalrepeatingapplications.Its fullydifferential
- AdjustableOutput Amplitude signalpath ensures exceptionalsignalintegrityand noise immunity and itdrivesboth differentialand• Single3.3VSupply single-endedtransmissionlinesat data rates in• Industrial-40°C to+85°C Temperature excessof1.5Gbps.
- Low Power: 150 mW (typ)at1.5Gbps Output voltageamplitudeis adjustablevia a single• Space-saving3 x 3 mm WSON-8 Package externalresistorforleveltranslationand cabledriving applicationsinto50-ohm single-endedand 100-ohm APPLICATIONS differentialmode impedances.
- Cable ExtensionApplications The DS15BA101 is powered from a single3.3V
- LevelTranslation supplyand consumes 150 mW (typ)at 1.5 Gbps. It operates over the full−40°C to +85°C industrial• SignalBufferingand Repeating temperaturerangeand isavailableina space saving• SecurityCameras 3x3 mm WSON-8 package. TypicalApplication Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2006–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SNLS234J –OCTOBER 2006–REVISED APRIL 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1) SupplyVoltage −0.5Vto3.6V InputVoltage(allinputs) −0.3VtoVCC +0.3V OutputCurrent 28 mA StorageTemperatureRange −65°C to+150°C JunctionTemperature +150°C Lead Temperature (Soldering4 Sec) +260°C θJA WSON-8 +90.7°C/W Package ThermalResistance θJC WSON-8 +41.2°C/W ESD Rating(HBM) 5 kV ESD Rating(MM) 250V (1) "AbsoluteMaximum Ratings"arethoseparametervaluesbeyond whichthelifeand operationofthedevicecannotbe ensured.The statinghereinofthesemaximums shallnotbe construedtoimplythatthedevicecan orshouldbe operatedatorbeyond thesevalues. The tableof"ElectricalCharacteristics"specifiesacceptabledeviceoperatingconditions. Recommended OperatingConditions SupplyVoltage(VCC – GND): 3.3V±5% OperatingFreeAirTemperature(TA) DS15BA101SD −40°C to+85°C DC ElectricalCharacteristics Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified.(1)(2) Symbol Parameter Conditions Reference Min Typ Max Units VICM InputCommon Mode Voltage See Note(3) IN+,IN- VCC –0.8 VVID/2 VID DifferentialInputVoltageSwing 100 2000 mV P−P VOS OutputCommon Mode Voltage OUT+, OUT- VCC – VVOUT /2 VOUT OutputVoltage Single-ended,25Ω load 400 mV P-PR VO = 953Ω 1%, Single-ended,25Ω load 800 mV P-PR VO = 487Ω 1%, ICC SupplyCurrent See Note(4) 45 49 mA (1) Currentflowintodevicepinsisdefinedas positive.Currentflowoutofdevicepinsisdefinedas negative.Allvoltagesarestated referencedtoGND. (2) TypicalvaluesarestatedforVCC = +3.3V and TA = +25°C. (3) Specificationisensuredby characterization. (4) Maximum ICC ismeasured atVCC = +3.465V and TA = +70°C.
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(GND) DAP DS15BA101 www.ti.com SNLS234J –OCTOBER 2006–REVISED APRIL 2013 AC ElectricalCharacteristics Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified(1). Symbol Parameter Conditions Reference Min Typ Max Units DR MAX Maximum Data Rate See Note(2) IN+,IN- 1.5 2.0 Gbps tLHT OutputLow toHighTransition 20% – 80% (3) OUT+, OUT- 120 220 psTime tHLT OutputHightoLow Transition 120 220 psTime tPLHD PropagationLow toHighDelay See Note(2) 0.95 1.10 1.35 ns tPHLD PropagationHightoLow Delay See Note(2) 0.95 1.10 1.35 ns tTJ TotalJitter 1.5Gbps 26 psP-P (1) TypicalvaluesarestatedforVCC = +3.3V and TA = +25°C. (2) Specificationisensuredby characterization. (3) Specificationisensuredby characterizationand verifiedby test. CONNECTION DIAGRAM Figure1. 8-Pad WSON See NGQ Package PIN DESCRIPTIONS Pin # Name Description 1 IN+ Non-invertinginputpin. 2 IN- Invertinginputpin. 3 GND Circuitcommon (groundreference). 4 R VO Outputvoltageamplitudecontrol.Connecta resistortoVCC tosetoutputvoltage. 5 VCC Positivepower supply(+3.3V). 6 GND Circuitcommon (groundreference). 7 OUT- Invertingoutputpin. 8 OUT+ Non-invertingoutputpin. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS15BA101
50: 50: 100: Differential T-Line LVPECL 100: OUT+ OUT- DS15BA101 IN+ IN- 50:50: VCC CML3.3V or CML2.5V 100: 100: Differential T-Line OUT+ OUT- DS15BA101 IN+ IN- 100: 100: Differential T-Line LVDS DS15BA101 SNLS234J –OCTOBER 2006–REVISED APRIL 2013 www.ti.com DEVICE OPERATION INPUT INTERFACING The DS15BA101 acceptseitherdifferentialorsingle-endedinput.The inputsareself-biased,allowingforsimple AC orDC coupling.DC-coupledinputsmust be keptwithinthespecifiedcommon-mode range.The IN+ and IN- pinsare self-biasedat approximately2.1V withVCC = 3.3V.The followingthreefiguresillustratetypicalDC- coupledinterfacetocommon differentialdrivers. Figure2. TypicalLVDS DriverDC-Coupled InterfacetoDS15BA101 Input Figure3. TypicalCML DriverDC-Coupled InterfacetoDS15BA101 Input Figure4. TypicalLVPECL DriverDC-Coupled InterfacetoDS15BA101 Input OUTPUT INTERFACING The DS15BA101 uses currentmode outputs.Single-endedoutputlevelsare 400 mV P-P intoAC-coupled100Ω differentialcable(withR VO = 953Ω) or intoAC-coupled50Ω coaxialcable(withR VO = 487Ω).Outputlevelis controlledby thevalueoftheR VO resistorconnectedbetween theR VO and VCC . The R VO resistorshouldbe placedas closeas possibletotheR VO pin.Inaddition,thecopperintheplanelayers below the R VO networkshouldbe removed to minimizeparasiticcapacitance.The followingfigureillustrates typicalDC-coupled interfaceto common differentialreceiversand assumes thatthe receivershave high impedance inputs.Whilemost receivershave a common mode inputrangethatcan accomodate CML signals,it is recommended to check respectivereceiver'sdatasheetpriorto implementingthe suggested interface implementation.
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0.1 PF50:50:487:
100:
1 PF 1 PF
50: 1 PF OUT+ OUT- CAP+ CAP- 0.1 PF VCCVCC 25: 50: Coaxial Cable R VO DS15BA101 OUT- IN+ IN- OUT+
0.1 PF50:50:953:
100: 1 PF 1 PF 1 PF 1 PF DS15EA101 IN+ IN- 100: 1 PF OUT+ OUT- CAP+ CAP- 0.1 PF VCCVCC 100: Differential TP Cable R VO OUT+ OUT- CML or LVPECL or LVDS IN+ IN- 50:50: VCC 100: 100: Differential T-Line DS15BA101 DS15BA101 www.ti.com SNLS234J –OCTOBER 2006–REVISED APRIL 2013 Figure5. TypicalDS15BA101 Output DC-Coupled Interfacetoan LVDS, CML or LVPECL Receiver CABLE EXTENDER APPLICATION The DS15BA101 togetherwiththeDS15EA101 forma cableextenderchipsetoptimizedforextendingserialdata streams from serializer/deserializer(SerDes)pairsand fieldprogrammable gate arrays(FPGAs) over 100Ω differential(i.e.CAT5e/6/7and twinax)and 50Ω coaxialcables.SettingcorrectDS15BA101 outputamplitudeand propercableterminationare keys foroptimaloperation.The followingtwo figuresshow recommended chipset configurationfor100Ω differentialand 50Ω coaxialcables. Figure6. Cable ExtenderChipsetConnection Diagram for100Ω DifferentialCables Figure7. Cable ExtenderChipsetConnection Diagram for50Ω CoaxialCables Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS15BA101
SNLS234J –OCTOBER 2006–REVISED APRIL 2013 www.ti.com REFERENCE DESIGN There isa completereferencedesign(P/N:DriveCable02EVK)availableforevaluationof the cableextender chipset(DS15BA101 and DS15EA101). Formore information,visithttp://www.ti.com/tool/drivecable02evk. TypicalPerformance Figure8.1.5Gbps DifferentialDS15BA101 Output Figure9.1.5Gbps Single-endedDS15BA101 Output R VO = 953Ω,H:100 ps /DIV,V:100 mV /DIV R VO = 487Ω,H:100 ps /DIV,V:100 mV /DIV Figure10.2.0Gbps DifferentialDS15BA101 Output Figure11.2.0Gbps Single-endedDS15BA101 Output R VO = 953Ω,H:100 ps /DIV,V:100 mV /DIV R VO = 487Ω,H:100 ps /DIV,V:100 mV /DIV
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REVISION HISTORY
Changes from RevisionI(April2013)toRevisionJ Page Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS15BA101
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS15BA101SD/NOPB Active Production WSON (NGQ) | 8 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 BA101 DS15BA101SD/NOPB.A Active Production WSON (NGQ) | 8 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 BA101 DS15BA101SDE/NOPB Active Production WSON (NGQ) | 8 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 BA101 DS15BA101SDE/NOPB.A Active Production WSON (NGQ) | 8 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 BA101 DS15BA101SDX/NOPB Active Production WSON (NGQ) | 8 4500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 BA101 DS15BA101SDX/NOPB.A Active Production WSON (NGQ) | 8 4500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 BA101 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
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PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS15BA101SD/NOPB WSON NGQ 8 1000 208.0 191.0 35.0 DS15BA101SDE/NOPB WSON NGQ 8 250 208.0 191.0 35.0 DS15BA101SDX/NOPB WSON NGQ 8 4500 356.0 356.0 36.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 8X 0.3 0.2 2 0.1 8X 0.5 0.3 1.5 1.6 0.1 6X 0.5 0.8 0.7 0.05 0.00 B 3.1 2.9 A 3.1 2.9 (0.1) TYP WSON - 0.8 mm max heightNGQ0008A PLASTIC SMALL OUTLINE - NO LEAD 4214922/A 03/2018 PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MIN
0.07 MAX
(1.6) 6X (0.5) (2.8) 8X (0.25) 8X (0.6) (2) (R0.05) TYP ( 0.2) VIA TYP (0.75) WSON - 0.8 mm max heightNGQ0008A PLASTIC SMALL OUTLINE - NO LEAD 4214922/A 03/2018 SYMM 4 5 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN 8X (0.25) 8X (0.6) 6X (0.5) (1.79) (1.47) (2.8) (R0.05) TYP WSON - 0.8 mm max heightNGQ0008A PLASTIC SMALL OUTLINE - NO LEAD 4214922/A 03/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 9: 82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 4 5 SYMM METAL TYP9
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