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Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
FEATURES
Integrated NV SRAM, Real-Time Clock (RTC), Crystal, Power-Fail Control Circuit, and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM; These Registers Reside in the 16 Top RAM Locations Century Byte Register (i.e., Y2K Compliant) Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power Precision Power-On Reset Programmable Watchdog Timer and RTC Alarm BCD-Coded Year, Month, Date, Day, Hours, Minutes, and seconds with Automatic Leap- Year Compensation Valid Up to the Year 2100 Battery Voltage-Level Indicator Flag Power-Fail Write Protection Allows for 10% V CC Power-Supply Tolerance Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time Also Available in Industrial Temperature Range: -40°C to +85°C PIN CONFIGURATIONS DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM www.maxim-ic.com RST VCC A15 IRQ/FT WE A13 A11 OE A10 CE DQ7 DQ5 DQ6 DQ4 DQ3 A14 DQ1 DQ0 A16 A12 DQ2 GND Encapsulated DIP Maxim DS1556 TOP VIEW IRQ/FT 1 A15 A16 RST VCC OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND N.C. A14 A13 A12 A11 A10 34 N.C. X1 GND VBAT X2 PowerCap Module Board (Uses DS9034PCX PowerCap) WE Maxim DS1556 19-5500; Rev 9/10
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM 2 of 18 PIN DESCRIPTION A0–A16 - Address Input DQ0–DQ7 - Data Input/Outputs IRQ/FT - Interrupt, Frequency Test Output (Open Drain) RST - Power-On Reset Output (Open Drain) CE - Chip Enable OE - Output Enable WE - Write Enable V CC - Power Supply Input GND - Ground N.C. - No Connection X1, X2 - Crystal Connection V BAT - Battery Connection
ORDERING INFORMATION
(V) PIN-PACKAGE TOP MARK** DS1556-70+ 0°C to +70°C 5.0 32 EDIP (0.740a) DS1556+070 DS1556-70IND+ -40°C to +85°C 5.0 32 EDIP (0.740a) DS1556+070 IND DS1556P-70+ 0°C to +70°C 5.0 34 PowerCap* DS1556P+70 DS1556P-70IND+ -40°C to +85°C 5.0 34 PowerCap* DS1556P+70 IND DS1556W-120+ 0°C to +70°C 3.3 32 EDIP (0.740a) DS1556W+120 DS1556W-120IND+ -40°C to +85°C 3.3 32 EDIP (0.740a) DS1556W+120 IND DS1556WP-120+ 0°C to +70°C 3.3 34 PowerCap* DS1556WP+120 DS1556WP-120IND+ -40°C to +85°C 3.3 34 PowerCap* DS1556WP+120 IND +Denotes a lead(Pb)-free/RoHS-compliant package. *DS9034-PCX+ or DS9034I-PCX+ required (must be ordered separately). **A “+” in top mark denotes a lead(Pb)-free device. An “IND” anywh ere on the top mark indicates an industrial temperature grade device.
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM 3 of 18
DESCRIPTION
The DS1556 is a full-function, year-2000-compliant (Y2KC), real-time clock/ca lendar (RTC) with an RTC alarm, watchdog timer, power-on reset, battery monitor, and 128k x 8 nonvolatile static RAM. User access to all registers within the DS1556 is accomplished with a byte-wide interface as shown in Figure 1. The RTC registers contain century, year, month, date, day, hours, minut es, and seconds data in 24-hour BCD format. Corrections for day of month and leap year are made automatically. The RTC registers are double-buffered in to an internal and external set. The user has dir ect access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static da ta. Assuming the internal oscillator is turn ed on, the internal set of registers is continuously updated, which occurs regardless of extern al registers settings to guarantee that accurate RTC information is always maintained. The DS1556 has interrupt ( IRQ/FT) and reset ( RST) outputs which can be used to control CPU activity. The IRQ/FT interrupt output can be used to generate an external inte rrupt when the RTC register values match user programmed alarm values. The interrupt is always available while the device is powered from the system supply and can be programmed to occur when in the battery-backed state to serve as a system wake-up. Either the IRQ/FT or RST outputs can also be used as a CPU watchdog timer, CPU activity is monitored and an interrupt or reset output will be activ ated if the correct activity is not detected within programmed limits. The DS1556 power-on reset can be us ed to detect a system power down or failure and hold the CPU in a safe reset state until normal power returns and stabilizes; the RST output is used for this function. The DS1556 also contains its own power-fail circuitry, which automatically deselects the device when the V CC supply enters an out of tolerance condition. This feature provides a high de gree of data security during unpredictable system operation brought on by low VCC levels. PACKAGES The DS1556 is available in two pa ckages (32-pin DIP and 34-pin Po werCap module). The 32-pin DIP style module integrates the crystal, lithium energy s ource, and silicon all in one package. The 34-pin PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the DS1556P after the completion of the surface mount process. Mounting the PowerCap af ter the surface mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module board and PowerCap are ordered separately and shippe d in separate containers. The pa rt number for the PowerCap is DS9034PCX.
Figure 1. Block Diagram Table 1. Operating Modes
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM 5 of 18 a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the data bus can become active w ith read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. DATA-RETENTION MODE The 5V device is fully accessible and data can be written and read only when V CC is greater than V PF. However, when V CC is below the power-fail point V PF (point at which writ e protection occurs) the internal clock registers and SRAM are blocked from any access. When V CC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium battery. RTC operation and SRAM data are maintained from the battery until V CC is returned to nominal levels. The 3.3V device is fully accessible and data can be written and read only when V CC is greater than V PF. hen VCC falls below V PF, access to the device is inhibited. If V PF is less than V SO, the device power is switched from V CC to the internal backup lithium battery when V CC drops below V PF. If V PF is greater than VSO, the device power is switched from V CC to the internal backup lithium battery when V CC drops below V SO. RTC operation and SRAM data are maintained from the battery until V CC is returned to nominal levels. All control, data, and address signals must be powered down when V CC is powered down. BATTERY LONGEVITY The DS1556 has a lithium power source that is designe d to provide energy for the clock activity, and clock and RAM data retention when the V CC supply is not present. The capability of this internal power supply is sufficient to power the DS1556 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25 C with the internal clock oscillator running in the absence of V CC. Each DS1556 is shipped from Maxim with its lithium energy source disconnected, guaranteei ng full energy capacity. When V CC is first applied at a level greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1556 will be much longer than 10 years since no internal batter y energy is consumed when V CC is present. INTERNAL BATTERY MONITOR The DS1556 constantly monitors the battery voltage of the internal battery. The Battery Low Flag (BLF) bit of the Flags Register (B4 of 1FFF0h) is not writable and should always be a 0 when read. If a 1 is ever present, an exhausted lithium energy source is indi cated and both the contents of the RTC and RAM are questionable. POWER-ON RESET A temperature compensated comparator circuit monitors the level of V CC. When V CC falls to the power fail trip point, the RST signal (open drain) is pulled low. When V CC returns to nominal levels, the RST signal continues to be pulled low for a period of 40 ms to 200 ms . The power-on reset function is independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.
Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions. Table 2. Register Map oscillator. The DS1556 is shipped from Maxim with the clock oscillator turned off, OSC bit set to a 1.
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM 7 of 18 READING THE CLOCK When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC Registers. This puts the external re gisters into a static state allowing data to be read without register values changing during the read process. Normal updates to the internal registers continue while in this state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register (1FFF8h). As long as a 1 remains in the Control Regist er read bit, updating is halted. After a halt is issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command was issued. Normal updates to the external set of registers will resume within 1 second after the read bit is set to a 0 for a minimum of 500 s. The read bit must be a zero for a minimum of 500 s to ensure the external registers will be updated. SETTING THE CLOCK The MSB bit, B7, of the Control Register is the write bit. Setting the write bit to a 1, like the read bit, halts updates to the DS1556 (1FFF8h to 1FFFFh) registers. After setting the write bit to a 1, RTC Registers can be loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to a 0 then transfers the values written to the internal RTC Registers and allows normal operation to resume. CLOCK ACCURACY (DIP MODULE) The DS1556 is guaranteed to keep time accuracy to within 1 minute per month at 25 C. The RTC is calibrated at the factory by Maxim using nonvolatile tuning elements, and does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. The electrical environment also affects clock accuracy, and caution should be taken to place the RTC in the lowest-level EMI section of the PC board layout. For additional inform ation, refer to Application Note 58. CLOCK ACCURACY (PowerCap MODULE) The DS1556 and DS9034PCX are each individually tested for accuracy. Once mounted together, the module will typically keep time accuracy to within 1.53 minutes per month (35 ppm) at 25°C. The electrical environment also affects clock accuracy, and caution should be taken to place the RTC in the lowest-level EMI section of the PC board layout. For additi onal information, refer to Application Note 58. FREQUENCY TEST MODE The DS1556 frequency test mode uses the open drain IRQ/FT output. With the oscillator running, the IRQ/FT output will toggle at 512 Hz when the FT bit is a 1, the Alarm Flag Enable bit (AE) is a 0, and the Watchdog Steering bit (WDS) is a 1 or the Watchdog Register is reset (Register 1FFF7h = 00h). The IRQ/FT output and the frequency test mode can be used as a measure of the actual frequency of the 32.768 kHz RTC oscillator. The IRQ/FT pin is an open-drain output that requires a pullup resistor for proper operation. The FT bit is cleared to a 0 on power-up.
notify the user of an incorrect alarm setting. Table 3. Alarm Mask Bits signal is cleared by a read or write to the Flags Register (Addre ss 1FFF0h) as shown in Figure 2 and 3. read/write cycle and the IRQ/FT signal has been cleared. Figure 2. Clearing IRQ Waveforms
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM 10 of 18 USING THE WATCHDOG TIMER The watchdog timer can be used to detect an out- of-control processor. The user programs the watchdog timer by setting the desired amount of time-out into the 8-bit Watchdog Regist er (Address 1FFF7h). The five Watchdog Register bits BMB4 to BMB0 store a binary multiplier and the two lower order bits RB1 to RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The watchdog timeout value is then determined by the multip lication of the 5-bit multip lier value with the 2-bit resolution value. (For example: writing 00001110 in the Watchdog Register = 3 x 1 second or 3 seconds.) If the processor does not reset the timer within the specified period, the Watchdog Flag (WF) is set and a processor interrupt is generated and stay s active until either the Watc hdog Flag (WF) is read or the Watchdog Register (1FFF7h) is read or written. The most significant bit of the Wa tchdog Register is the Watchdog Steeri ng Bit (WDS). When set to a 0, the watchdog will activate the IRQ/FT output when the watchdog times out. When WDS is set to a 1, the watchd og will output a negative pulse on the RST output for a duration of 40ms to 200ms. The Watchdog Register (1FFF7h) and the FT bit will reset to a 0 at the end of a watchdog timeout when the WDS bit is set to a 1. The watchdog timer resets when the processor perfor ms a read or write of the Watchdog Register. The time-out period then starts over. The watchdog timer is disabled by writing a value of 00h to the Watchdog Register. The watchdog function is automati cally disabled upon power-up and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/FT output and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied. POWER-ON DEFAULT STATES Upon application of power to the device, the following register bits are set to a 0: WDS = 0, BMB0 to BMB4 = 0, RB0 to RB1 = 0, AE = 0, ABE = 0.
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM 11 of 18 ABSOLUTE MAXIMUM RATINGS Storage Temperature Range Note: EDIP is hand or wave-soldered only. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. OPERATING RANGE RANGE TEMP RANGE V CC Commercial 0°C to +70°C 3.3V 10% or 5V 10% Industrial -40°C to +85°C 3.3V 10% or 5V 10% RECOMMENDED DC OPERATING CONDITIONS (Over the Operating Range) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VIH VCC = 5V 10% 2.2 VCC + 0.3V V Logic 1 Voltage All Inputs (Note 1) VIH VCC = 3.3V 10% 2.0 VCC + 0.3V V VIL VCC = 5V 10% -0.3 +0.8 Logic 0 Voltage All Inputs (Note 1) VIL VCC = 3.3V 10% -0.3 +0.6 DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, Over the Operating Range.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Active Supply Current ICC (Notes 2, 3, 11) 30 85 mA TTL Standby Current (CE = VIH) ICC1 (Notes 2, 3) 4 6 mA CMOS Standby Current (CE VCC - 0.2V) ICC2 (Notes 2, 3) 2 6 mA Input Leakage Current (Any Input) IIL -1 +1 A Output Leakage Current (Any Output) I OL -1 +1 A Output Logic 1 Voltage OUT = -1.0 mA) VOH (Note 1) 2.4 V VOL1 IOUT = 2.1 mA, DQ0–7 Outputs (Note 1) 0.4 V Output Logic 0 Voltage VOL2 IOUT = 7.0 mA, IRQ/FT, and RST Outputs (Notes 1, 5) 0.4 V Write Protection Voltage V PF (Note 1) 4.20 4.50 V Battery Switchover Voltage V SO (Notes 1,4) V BAT V
Figure 5. Read Cycle Timing Diagram
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM 13 of 18 AC CHARACTERISTICS—READ CYCLE (Over the Operating Range) VCC = 5.0V 10% V CC = 3.3V 10% PARAMETER SYMBOL MIN MAX MIN MAX UNITS Read Cycle Time tRC 70 120 ns Address Access Time tAA 70 120 ns CE to DQ Low-Z tCEL 5 5 ns CE Access Time tCEA 70 120 ns CE Data Off Time tCEZ 25 40 ns OE to DQ Low-Z tOEL 5 5 ns OE Access Time tOEA 35 100 ns OE Data Off Time tOEZ 25 35 ns Output Hold from Address t OH 5 5 ns AC CHARACTERISTICS—WRITE CYCLE (Over the Operating Range) VCC = 5.0V 10% V CC = 3.3V 10% PARAMETER SYMBOL MIN MAX MIN MAX UNITS Write Cycle Time tWC 70 120 ns Address Access Time tAS 0 0 ns WE Pulse Width tWEW 50 100 ns CE Pulse Width tCEW 60 110 ns Data Setup Time tDS 30 80 ns Data Hold Time (Note 9) t DH1 5 5 ns Data Hold Time (Note 10) t DH2 5 5 ns Address Hold Time (Note 9) t AH1 5 0 ns Address Hold Time (Note 10) tAH2 5 5 ns WE Data Off Time tWEZ 25 40 ns Write Recovery Time tWR 5 10 ns
Figure 8. Power-Up/Down Waveform Timing (5V Device)
Figure 9. Power-Up/Down Waveform Timing (3.3V Device)
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM 17 of 18 AC TEST CONDITIONS Output Load: 50 pF + 1TTL Gate Input Pulse Levels: 0.0 to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5 ns NOTES: 1. Voltage referenced to ground. 2. Typical values are at +25C and nominal supplies. 3. Outputs are open. 4. Battery switchover occurs at the lower of either the battery voltage or VPF. 5. The IRQ/FT and RST outputs are open drain. 6. Data-retention time is at +25C. 7. Each DS1556 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined for DIP modules and PowerCap modules as a cumulative time in the absence of VCC starting from the time power is first applied by the user. 8. RTC modules (DIP) can be successf ully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85C. Post-solder cleaning with water-washing techni ques is acceptable, provided that ultrasonic vibration is not used. In addition, for the PowerCap: a. Maxim recommends that PowerCap Module bases experience one pass th rough solder reflow oriented with the label side up (“live-bug”). b. Hand soldering and touch-up: Do no t touch or apply the soldering ir on to leads for more than 3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove solder. 9. tAH1, tDH1 are measured from WE going high. 10. tAH2, tDH2 are measured from CE going high. 11. tWC = 200ns.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OU TLINE NO. LAND PATTERN NO.
32 EDIP MDF32+1 21-0245 —
34 PWRCP PC2+6 21-0246 —
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM 18 of 18 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim and the Dallas logo are registered trademarks of Maxim Integrated Products.
REVISION HISTORY
Updated the Ordering Information table to include only lead-free parts; updated the Absolute Maximum Ratings section to include the storage temperature range and lead and soldering temperatures for EDIP and PowerCap packages; added Note 11 to the ICC parameter in the DC Electrical Characteristics tables (for 5.0V and 3.3V) and the Notes section; replaced the package outline drawings with the Package Information table 2, 11, 12, 17