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Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS1553 is a full-function, year-2000- compliant (Y2KC) real-time clock/calendar (RTC) with an RTC alarm, watchdog timer, power-on reset, battery monitor, and 8k x 8 nonvolatile static RAM. User access to all registers within the DS1553 is accomplished with a byte-wide interface as shown in Figure 1. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for day of month and leap year are made automatically. Pin Configurations appear at end of data sheet.
FEATURES
Integrated NV SRAM, RTC, Crystal, Power-Fail Control Circuit, and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM; These Registers are Resident in the
16 Top RAM Locations
Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power Precision Power-On Reset Programmable Watchdog Timer and RTC Alarm BCD-Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap Year Compensation Valid Up to the Year 2100 Battery Voltage Level Indicator Flag Power-Fail Write Protection Allows for 10% V CC Power-Supply Tolerance Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time
ORDERING INFORMATION
PART VOLTAGE (V) TEMP RANGE PIN-PACKAGE TOP MARK** DS1553-85+ 5.0 0°C to +70°C 28 EDIP (0.740) DS1553+85 DS1553-100+ 5.0 0°C to +70°C 28 EDIP (0.740) DS1553+100 DS1553W-120+ 3.3 0°C to +70°C 28 EDIP (0.740) DS1553W+120 DS1553W-150+ 3.3 0°C to +70°C 28 EDIP (0.740) DS1553W+150 DS1553P-85+ 5.0 0°C to +70°C 34 PowerCap* DS1553P+85 DS1553P-100+ 5.0 0°C to +70°C 34 PowerCap* DS1553P+100 DS1553WP-120+ 3.3 0°C to +70°C 34 PowerCap* DS1553WP+120 DS1553WP-150+ 3.3 0°C to +70°C 34 PowerCap* DS1553WP+150 DS9034PCX+ 3 0°C to +70°C — DS9034PCX +Denotes a lead(Pb)-free/RoHS-compliant package. *PowerCap required, must be ordered separately **A “+” symbol anywhere on the top mark indicates a lead(Pb)-free package. DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM www.maxim-ic.com 19-5480; Rev 8/10
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 2 of 20 PIN DESCRIPTION PIN EDIP PowerCap NAME FUNCTION 1 2 RST Active-Low Power-On Reset Output (Open Drain) 2 30 A12 3 25 A7 4 24 A6 5 23 A5 6 22 A4 7 21 A3 8 20 A2 9 19 A1 10 18 A0 21 28 A10 23 29 A11 24 27 A9 25 26 A8 Address Inputs 11 16 DQ0 12 15 DQ1 13 14 DQ2 15 13 DQ3 16 12 DQ4 17 11 DQ5 18 10 DQ6 19 9 DQ7 Data Input/Outputs 20 8 CE Active-Low Chip Enable 22 7 OE Active-Low Output Enable 26 1 IRQ/FT Active-Low Interrupt/Frequency Test Output (Open Drain) 27 6 WE Active-Low Write Enable 28 5 V CC Power-Supply Input
17 GND Ground
— 2, 3, 31–34 N.C No Connection
that accurate RTC information is always maintained. The DS1553 has interrupt ( IRQ /FT) and reset ( RST ) outputs that can be used to control CPU activity. output is used for this function. during unpredictable system operation brought on by low VCC levels. separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX. Figure 1. Block Diagram
Table 1. Operating Modes output data hold time (tOH) but will then go indeterminate until the next address access. transition on WE will then disable the outputs tWEZ after WE goes active. The 5V device is fully accessible, and data can be written and read only when V CC is greater than V PF. The 3.3V device is fully accessible and data can be written and read only when V CC is greater than V PF.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 5 of 20 below V SO. RTC operation and SRAM data are maintained from the battery until V CC is returned to nominal levels. All control, data, and address signals must be powered down when VCC is powered down. BATTERY LONGEVITY The DS1553 has a lithium power sour ce that is designed to provide energy for the clock activity and clock and RAM data retention when the V CC supply is not present. The capability of this internal power supply is sufficient to power the DS1553 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at +25 C with the internal clock oscillator running in the absence of V CC. Each DS1553 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When V CC is first applied at a level greater than VPF, the lithium energy source is enabled for battery backup operation. INTERNAL BATTERY MONITOR The DS1553 constantly monitors the battery voltage of the internal battery. The Battery Low Flag (BLF) bit of the Flags register (B4 of 1FF0 h) is not writeable and should always be 0 when read. If a 1 is ever present, an exhausted lithium energy source is indi cated, and both the contents of the RTC and RAM are questionable. POWER-ON RESET A temperature-compensated comparator circuit monitors the V CC level. When V CC falls to the power-fail trip point, the RST signal (open drain) is pulled low. When V CC returns to nominal levels, the RST signal continues to be pulled low for 40ms to 200ms. The power-on reset function is independent of the RTC oscillator and is therefore operational whether or not the oscillator is enabled.
Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions. Table 2. Register Map
4 BMB3 BMB2 BMB
1 RB0 Watchdog
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 7 of 20 READING THE CLOCK When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC registers. This puts the external registers into a static state, allowing data to be read without register values changing during the read process. Normal updates to the internal registers continue while in this state. External updates are halted when a 1 is written into the read bit, B6 of the Control register (1FF8h). As long as a 1 remains in the Control register read bit, updating is halted. After a halt is issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command was issued. Normal updates to the extern al set of registers resume within 1 second after the read bit is set to 0 for a minimum of 500 s. The read bit must be 0 for a minimum of 500 s to ensure the external registers are updated. SETTING THE CLOCK The 8th bit, B7 of the Control regist er, is the write bit. Setting the write bit to 1, like the read bit, halts updates to the DS1553 (1FF8h–1FFFh) registers. After se tting the write bit to 1, RTC registers can be loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to 0 then transfers the values written to the internal RTC registers and allows normal operation to resume. CLOCK ACCURACY (DIP MODULE) The DS1553 is guaranteed to k eep time accuracy to within 1 minute per month at +25 C. The RTC is calibrated at the factory by Dallas Semiconductor usi ng nonvolatile tuning elements and does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. The electrical environment also affects clock accuracy and caution should be taken to place the RTC in the lowest level EMI section of the PC board layout. For additional information, refer to Application Note 58: Crystal Consider ations with Dallas Real-Time Clocks , available on our website at www.maxim-ic.com/appnoteindex.com. CLOCK ACCURACY (PowerCap MODULE) The DS1553 and DS9034PCX are each individually tested for accuracy. Once mounted together, the module typically keeps time accuracy to within 1.53 minutes per month (35ppm) at +25°C. The electrical environment affects clock accuracy and caution should be taken to place the RTC in the lowest level EMI section of the PC board layout. For additional information, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks , available on our website at www.maxim-ic.com/appnoteindex.com. FREQUENCY TEST MODE The DS1553 frequency test mode uses the open-drain IRQ /FT output. With the oscillator running, the IRQ /FT output toggles at 512Hz when the FT bit is 1, the Alarm Flag Enable bit (AE) is 0, and the Watchdog Steering bit (WDS) is 1 or the Watchdog re gister is reset (Register 1FF7h = 00h). The IRQ /FT output and the frequency test mode can be used as a measure of the actual frequency of the 32.768kHz RTC oscillator. The IRQ /FT pin is an open-drain output that requires a pullup resistor for proper operation. The FT bit is cleared to 0 on power-up.
notify the user of an incorrect alarm setting. Table 3. Alarm Mask Bits read/write cycle and the IRQ /FT signal has been cleared.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 10 of 20 USING THE WATCHDOG TIMER The watchdog timer can be used to detect an out- of-control processor. The user programs the watchdog timer by setting the desired amount of timeout into the 8-bit Watchdog register (Address 1FF7h). The five Watchdog register bits BMB4–BMB0 store a binary multiplier and the tw o lower-order bits RB1–RB0 select the resolution, where 00 = 1/ 16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The watchdog timeout value is then determined by the multiplication of the 5-bit multiplier value with the 2-bit resolution value. (For example: writing 00001110 in the Watchdog register = 3 x 1 second or 3 seconds.) If th e processor does not reset the timer within the specified period, the Watchdog Flag (WF) is set and a processor interrupt is generated and stays active until either the Watchdog Flag (WF) is read or the Watchdog register (1FF7) is read or written. The most significant bit of the Watchdog register is the Watchdog Steering Bit (WDS). When set to 0, the watchdog activates the IRQ /FT output when the watchdog times out. When WDS is set to 1, the watc hdog outputs a negative pulse on the RST output for 40ms to 200ms. The Watchdog register (1FF7) and the FT bit are reset to 0 at the end of a watchdog timeout when the WDS bit is set to 1. The watchdog timer resets when th e processor performs a read or write of the Watchdog register. The timeout period then starts over. Writing a value of 00h to the Watchdog register disables the watchdog timer. The watchdog function is automatically disa bled upon power-up and th e Watchdog register is cleared. If the watchdog functi on is set to output to the IRQ /FT output and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied. POWER-ON DEFAULT STATES Upon application of power to the device, the following register bits are set to 0: WDS = 0, BMB0–BMB4 = 0, RB0–RB1 = 0, AE = 0, and ABE = 0.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 11 of 20 ABSOLUTE MAXIMUM RATINGS Storage Temperature Range (Note: EDIP is hand or wave-soldered only.) (Note 8) This is a stress rating only and functional ope ration of the device at these or any ot her conditions above those indicated in t he operation sections of this specification is not im plied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. OPERATING RANGE RANGE TEMP RANGE V CC Commercial 0°C to +70°C 3.3V 10% or 5V 10% RECOMMENDED DC OPERATING CONDITIONS (TA = Over the operating range.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES VCC = 5V ±10% V IH 2.2 V CC + 0.3V V 1 Logic 1 Voltage All Inputs VCC = 3.3V ±10% V IH 2.0 V CC + 0.3V V 1 VCC = 5V ±10% V IL -0.3 +0.8 1 Logic 0 Voltage All Inputs V DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±10%, TA = Over the operating range.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current ICC 15 50 mA 2, 3 TTL Standby Current (CE = VIH) ICC1 1 3 mA 2, 3 CMOS Standby Current (CE VCC - 0.2V) ICC2 1 3 mA 2, 3 Input Leakage Current (Any Input) IIL -1 +1 A Output Leakage Current (Any Output) IOL -1 +1 A Output Logic 1 Voltage (IOUT = -1.0mA) VOH 2.4 V 1 IOUT = 2.1mA, DQ0-7 Outputs VOL1 0.4 V 1 Output Logic 0 Voltage IOUT = 7.0mA, IRQ/FT and RST Outputs VOL2 0.4 V 1, 5 Write Protection Voltage VPF 4.20 4.50 V 1 Battery Switchover Voltage VSO V BAT V 1, 4
Figure 5. Read Cycle Timing Diagram
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 13 of 20 READ CYCLE, AC CHARACTERISTICS (VCC = 5.0V ±10%, TA = Over the operating range.) 85ns ACCESS 100ns ACCESS PARAMETER SYMBOL MIN MAX MIN MAX UNITS Read Cycle Time tRC 85 100 ns Address Access Time tAA 85 100 ns CE to DQ Low-Z tCEL 5 5 ns CE Access Time tCEA 85 100 ns CE Data Off Time tCEZ 30 35 ns OE to DQ Low-Z tOEL 5 5 ns OE Access Time tOEA 45 55 ns OE Data Off Time tOEZ 30 35 ns Output Hold from Address tOH 5 5 ns READ CYCLE, AC CHARACTERISTICS (VCC = 3.3V ±10%, TA = Over the operating range.) 120ns ACCESS 150ns ACCESS PARAMETER SYMBOL MIN MAX MIN MAX UNITS Read Cycle Time tRC 120 150 ns Address Access Time tAA 120 150 ns CE to DQ Low-Z tCEL 5 5 ns CE Access Time tCEA 120 150 ns CE Data Off Time tCEZ 40 50 ns OE to DQ Low-Z tOEL 5 5 ns OE Access Time tOEA 100 130 ns OE Data Off Time tOEZ 35 35 ns Output Hold from Address t OH 5 5 ns
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 14 of 20 WRITE CYCLE, AC CHARACTERISTICS (VCC = 5.0V ±10%, TA = Over the operating range.) 85ns ACCESS 100ns ACCESS PARAMETER SYMBOL MIN MAX MIN MAX UNITS Write Cycle Time tWC 85 100 ns Address Access Time tAS 0 0 ns WE Pulse Width tWEW 65 70 ns CE Pulse Width tCEW 70 75 ns Data Setup Time tDS 35 40 ns Data Hold time tDH 0 0 ns Address Hold Time tAH 5 5 ns WE Data Off Time tWEZ 30 35 ns Write Recovery Time tWR 5 5 ns WRITE CYCLE, AC CHARACTERISTICS (VCC = 3.3V ±10%, TA = Over the operating range.) 120ns ACCESS 150ns ACCESS PARAMETER SYMBOL MIN MAX MIN MAX UNITS Write Cycle Time tWC 120 150 ns Address Setup Time tAS 0 0 ns WE Pulse Width tWEW 100 130 ns CE Pulse Width tCEW 110 140 ns Data Setup Time tDS 80 90 ns Data Hold Time tDH 0 0 ns Address Hold Time tAH 0 0 ns WE Data Off Time tWEZ 40 50 ns Write Recovery Time tWR 10 10 ns
Figure 8. Power-Up/Down Waveform Timing 5V Device
Figure 9. Power-Up/Down Waveform Timing 3.3V Device
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 18 of 20 AC TEST CONDITIONS Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0 to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1) Voltage referenced to ground. 2) Typical values are at +25C and nominal supplies. 3) Outputs are open. 4) Battery switch over occurs at the lower of either the battery voltage or VPF. 5) The IRQ /FT and RST outputs are open drain. 6) Data retention time is at +25C. 7) Each DS1553 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined for DIP modules as a cu mulative time in the absence of VCC starting from the time power is first applied by the user. 8) Real-time clock modules (DIP) can be successfu lly processed through conventional wave-soldering techniques as long as temperatur e exposure to the lithium energy s ource contained within does not exceed +85 C. Post solder cleaning with water-washing techniques is accep table, provided that ultrasonic vibration is not used. In addition, for the PowerCap: a. Maxim recommends that PowerCap Module bases experience one pass th rough solder reflow oriented with the label side up (“live-bug”). b. Hand soldering and touch-up: Do no t touch or apply the soldering ir on to leads for more than 3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove solder.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 19 of 20 PIN CONFIGURATIONS
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS stat us only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
28 EDIP MDP28+2 21-0241 —
34 PWRCP PC1+2 21-0246 —
1 IRQ/FT
N.C. N.C. RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND N.C. N.C. N.C. A12 A11 A10 34 N.C. X1 GND VBAT X2 34-Pin PowerCap Module Board (Uses DS9034PCX PowerCap) DS1553 28-Pin Encapsulated Package (700-mil Extended) VCC WE IRQ/FT A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 RST A12 DQ0 DQ1 DQ2 GND DS1553 TOP VIEW
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 20 of 20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Maxim and the Dallas logo are registered trademarks of Maxim Integrated Products, Inc.
REVISION HISTORY
Updated the Ordering Information table; updated the storage and soldering temperatures and added the lead temperature in the Absolute Maximum Ratings section; changed 70ns Access to 85ns Access in the Read Cycle, AC Characteristics (5V) table and updated the min/max values for tRC, tAA, tCEA, tCEZ, tOEA, and tOEZ; changed 70ns Access to 85ns Access in the Write Cycle, AC Characteristics (5V) table and updated the min/max values for tWC, tWEW, tCEW, tDS, and tWEZ; updated the Package Information table and removed the package drawings 1, 13, 14, 19