DS1501_09 MAXIM | Alldatasheet
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Y2K-Compliant Watchdog Real-Time Clocks GENERAL DESCRIPTION The DS1501/DS1511 are full-function, year 2000- compliant real-time clock/ca lendars (RTCs) with an RTC alarm, watchdog timer, power-on reset, battery monitors, 256 bytes NV SRAM, and a 32.768kHz output. User access to all registers within the DS1501/DS1511 is accomplished with a byte-wide interface, as shown in Figure 8 . The RTC registers contain century, year, m onth, date, day, hours, minutes, and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for day of month and leap year are made automatically.
APPLICATIONS
Pin Configurations and Typical Operating Circuit appear at end of data sheet.
FEATURES
BCD-Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap-Year Compensation Valid Up to the Year 2100 Programmable Watchdog Timer and RTC Alarm Century Register; Y2K-Compliant RTC +3.3 (W) or +5V (Y) Operation Precision Power-On Reset Power-Control Circuitry Support System Power-On from Date/Day/Time Alarm or Key Closure/Modem-Detect Signal 256 Bytes Battery-Backed SRAM Auxiliary Battery Input Accuracy of DS1511 Better than ±1 Minute/Month at +25°C Day-of-Week/Date Alarm Register Crystal Select Bit Allow RTC to Operate with 6pF or 12.6pF Crystal (DS1501) Battery Voltage-Level Indicator Flags Available as Chip (DS1501) or Stand-Alone Encapsulated DIP Module with Embedded Battery and Crystal (DS1511) Underwriters Laboratories (UL) Recognized
ORDERING INFORMATION
PART VOLTAGE (V) TEMP RANGE PIN-PACKAGE TOP MARK* DS1501W+ 3.3 0°C to +70°C 28 DIP (0.600) DS1501W DS1501WE+ 3.3 0°C to +70°C 28 TSOP DS1501WE DS1501WEN+ 3.3 -40°C to +85°C 28 TSOP DS1501WEN DS1501WEN+T&R 3.3 -40°C to +85°C 28 TSOP/Tape & Reel DS1501WEN DS1501WE+T&R 3.3 0°C to +70°C 28 TSOP/Tape & Reel DS1501WE +Denotes a lead(Pb)-free/RoHS-compliant package. *A “+” anywhere on the top mark denotes a lead(Pb)-free device. An N or IND denotes an industrial temperature device. Ordering Information continued at end of data sheet. 1 of 22 REV: 010909 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks 2 of 22 ABSOLUTE MAXIMUM RATINGS Soldering Temperature (SO, TSOP)…….………….….. See IPC/JEDEC J-STD-020 for surface-mount devices Stresses beyond those listed under “Absolute Maximum Ratings” may c ause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (VCC = 3.3V or 5V ±10%, TA = 0°C to +70°C; VCC = 3.3V or 5V ±10%, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Y 2.2 VCC + 0.3 Logic 1 Voltage All Inputs (Note 3) VIH W 2.0 VCC + 0.3 V Pullup Voltage, IRQ, PWR, and RST Outputs (Note 3) VPU 5.5 V Y -0.3 +0.8 Logic 0 Voltage All Inputs (Note 3) VIL W -0.3 +0.6 V Battery Voltage (Note 3) VBAT 2.5 3.0 3.7 V DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V or 5V ±10%, TA = 0°C to +70°C; VCC = 3.3V or 5V ±10%, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Y 15 Active Supply Current (Note 4) ICC W 10 mA Y 5 TTL Standby Current (CE = VIH) ICC1 W 4 mA Y 5 CMOS Standby Current (CE = VCC - 0.2V) ICC2 W 4 mA Input Leakage Current (Any Input) IIL -1 +1 μA Output Leakage Current (Any Output) IOL -1 +1 μA Output Logic 1 Voltage (IOUT = -1.0mA) VOH (Note 3) 2.4 V VOL1 (Note 3) 0.4 V Output Logic 0 Voltage (IOUT = 2.1mA, DQ0–7; IOUT = 5.0mA, IRQ, IOUT = 7.0mA, PWR and RST) VOL2 (Notes 3, 5) 0.4 V Y 2.0 Battery Low, Flag Trip Point (Note 2) VBLF W 1.9 V Y 4.20 4.50 Power-Fail Voltage (Note 2) VPF W 2.75 2.97 V Battery Switchover Voltage (Notes 3, 6) VSO VBAT, VBAUX, or VPF V Battery Leakage Current ILKG 100 nA
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks 3 of 22 DC ELECTRICAL CHARACTERISTICS (VCC = 0V; TA = 0°C to +70°C; VCC = 0V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Battery Current, BB32 = 0, EOSC = 0 IBAT1 (Note 7) 0.27 1.0 μA Battery Current, BB32 = 0, EOSC = 1 IBAT2 (Note 7) 0.01 0.1 μA VBAUX Current BB32 = 1, SQW Open IBAUX (Note 7) 2 μA CRYSTAL SPECIFICATIONS* PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Nominal Frequency fO 32.768 kHz Series Resistance ESR 45 kΩ Load Capacitance CL 6/12.5 pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. AC OPERATING CHARACTERISTICS (VCC = 5V ±10%, TA = 0°C to +70°C; VCC = 5V ±10%, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Read Cycle Time tRC 70 ns Address Access Time tAA 70 ns CE to DQ Low-Z tCEL (Note 8) 5 ns CE Access Time tCEA 70 ns CE Data-Off Time tCEZ (Note 8) 25 ns OE to DQ Low-Z (0°C to +85°C) tOEL (Note 8) 5 ns OE to DQ Low-Z (-40°C to 0°C) tOEL (Note 8) 2 ns OE Access Time tOEA 35 ns OE Data-Off Time tOEZ (Note 8) 25 ns Output Hold from Address tOH 5 ns Write Cycle Time tWC 70 ns Address Setup Time tAS 0 ns WE Pulse Width tWEW 50 ns CE Pulse Width tCEW 55 ns Data Setup Time tDS 30 ns Data Hold Time tDH 5 ns Address Hold Time tAH 0 ns WE Data-Off Time tWEZ (Note 8) 25 ns Write Recovery Time tWR 15 ns Pulse Width, OE, WE, or CE High PWHIGH 20 ns Pulse Width, OE, WE, or CE Low PWLOW 70 ns
Figure 1. Read Cycle Timing
Figure 4. Burst Mode Timing Waveform
Note: Time intervals shown above are referenced in Wakeup/Kickstart. Figure 7. Wakeup/Kickstart Timing Diagram Note 1: Limits at -40°C are not production tested and are guaranteed by design. provided that ultrasonic vibration is not used to prevent damage to the crystal. Note 3: Voltage referenced to ground. Note 5: The IRQ, PWR, and RST outputs are open drain. Note 7: VBAT or VBAUX current. Using a 32,768Hz crystal connected to X1 and X2. Note 8: These parameters are sampled with a 5pF load and are not 100% tested. Note 9: tDR is the amount of time that the internal battery can power the internal oscillator and internal registers of the DS1511. Note 10: If the oscillator is not enabled, the startup time of the oscillator after VCC1 is applied will be added to the wakeup/kickstart timeout. Note 11: Typical values are at +25°C, nominal (active) supply, unless otherwise noted.
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks 9 of 22 PIN DESCRIPTION PIN DIP, SO EDIP TSOP NAME FUNCTION 1 1 8 PWR Active-Low Power-On Output (Open Drain). This output, if used, is normally connected to power-supply control circuitry. This pin requires a pullup resistor connected to a positive supply to operate correctly. 2, 3 — 9, 10 X1, X2 Connections for Standard 32.768kHz Quartz Crystal. For greatest accuracy, the DS1501 must be used with a crystal that has a specified load capacitance of either 6pF or 12.5pF. The crystal select (CS) bit in control register B is used to select operation with a 6pF or 12.5pF crystal. The crystal is attached directly to the X1 and X2 pins. There is no need for external capacitors or resistors. An external 32.768kHz oscillator can also drive the DS1501. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. See Figure 9. An enable bit in the month register controls the oscillator. Oscillator startup time is highly dependent upon crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with the recommended characteristics and proper layout usually starts within one second. 4 4 11 RST Active-Low Reset Output. (Open Drain). This output, if used, is normally connected to a microprocessor-reset input. This pin requires a pull up resistor connected to a positive supply to operate correctly. When RST is active, the device is not accessible. 5 5 12 IRQ Active-Low Interrupt Output (Open Drain). This output, if used, is normally connected to a microprocessor interrupt input. This pin requires a pullup resistor connected to a positive supply to operate correctly. 6–10 6–10 13–17 A4–A0 Address Inputs. Selects one of 17 register locations. 11–13, 15–19 11–13, 15–19 18–20, 22–26 DQ0–DQ7 Data Input/Output. I/O pins for 8-bit parallel data transfer. 14, 21 14 21, 28 GND Ground. DC power is applied to the device on these pins. VCC is the positive terminal. When power is applied within the normal limits, the device is fully accessible and data can be written and read. When VCC drops below the normal limits, reads and writes are inhibited. As VCC drops below the battery voltage, the RAM and timekeeping circuits are switched over to the battery. 22 22 1 OE Output-Enable Input. Active-low input that enables DQ0–DQ7 for data output from the device. 20 20 27 CE Chip-Enable Input. Active-low input to enable the device. 23 23 2 SQW Square-Wave Output. When enabled, the SQW pin outputs a 32.768kHz square wave. If the square wave (E32K) and battery backup 32kHz (BB32) bits are enabled, power is provided by VBAUX when VCC is absent. 24 24 3 KS Active-Low Kickstart Input. This pin is used to wake up a system from an external event, such as a key closure. The KS pin is normally connected using a pullup resistor to VBAUX. If the KS function is not used, connect to ground. 25 — 4 VBAT Battery Input for Any Standard 3V Lithium Cell or Other Energy Source. Battery voltage must be held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse charging current when used with a lithium battery. www.maxim-ic.com/TechSupport/QA/ntrl.htm If not used, connect to ground. 26 26 5 VBAUX Auxiliary Battery Input for Any Standard 3V Lithium Cell or Other Energy Source. Battery voltage must be held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse charging current when used with a lithium battery. www.maxim-ic.com/TechSupport/QA/ntrl.htm If not used, connect to ground. 27 27 6 WE Write-Enable Input. Active-low input that enables DQ0–DQ7 for data input to the device. 28 28 7 VCC DC Power. VCC is the positive terminal. When power is applied within the normal limits, the device is fully accessible and data can be written and read. When VCC drops below the normal limits, reads and writes are inhibited. As VCC drops below the battery voltage, the RAM and timekeeping circuits are switched over to the battery. — 2, 3, 21, 25 — N.C. No Connect
Figure 8. Block Diagram
16 X 8
Figure 9. Typical Crystal Layout
fewer than 31 days, including corrections for leap year. occurs regardless of external register settings to guarantee that accurate RTC information is always maintained. system operation caused by low VCC levels. reset state until normal power returns and stabilizes; the RST output is used for this function. are the only components required to maintain time-of-day and memory status in the absence of power. Table 1. RTC Operating Modes but then goes indeterminate until the next address access (Table 1). referenced to the latter occurring transition of CE or WE. The addresses must be held valid throughout the cycle. defined by the address inputs. A low transition on WE then disables the outputs tWEZ after WE goes active (Table 1).
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks 12 of 22 DATA RETENTION MODE The DS1501/DS1511 are fully accessible, and data can be written and read only when V CC is greater than V PF. However, when V CC falls below the power-fail point V PF (point at which write protection occurs) the internal clock registers and SRAM are blocked from any access. While in the data retention mode, all inputs are don’t cares and outputs go to a high-Z state, with the possible exception of KS, PWR, SQW, and RST. If VPF is less than V BAT and VBAUX, the device power is switched from V CC to the greater of V BAT and VBAUX when VCC drops below VPF. If VPF is greater than VBAT and VBAUX, the device power is switched from VCC to the larger of VBAT and VBAUX when VCC drops below the larger of V BAT and V BAUX. RTC operation and SRAM data are maintained from the battery until V CC is returned to nominal levels ( Table 1). If the square-wave and battery-bac kup 32kHz functions are enabled, V BAUX always provides power for the square-wave output, when the device is in battery-backup mode. AUXILIARY BATTERY The VBAUX input is provided to supply power from an auxiliary battery for the DS1501/DS 1511 kickstart and square- wave output features in the absence of V CC. This power source must be avail able to use these auxiliary features when VCC is not applied to the device. This auxiliary battery can be used as the primary back up power source for maintaining the clock/calendar and external user RAM. This occurs if the V BAT pin is at a lower voltage than V BAUX. If the DS1501/DS1511 are to be backed up using a single battery with the auxiliary features enabled, then VBAUX should be used and VBAT should be grounded (DS1501). If VBAUX is not to be used, it must be grounded. OSCILLATOR CONTROL BIT When the DS1511 is shipped from the fact ory, the internal oscillator is turned off. This feature prevents the lithium energy cell from being used until it is installed in a sy stem. The oscillator is automatically enabled when power is first applied. POWER-ON RESET A temperature-compensated comparator circuit monitors the level of VCC. When VCC falls to the power-fail trip point, the RST signal (open drain) is pulled low. When VCC returns to nominal levels, the RST signal continues to be pulled low for a period of tREC. The power-on reset function is independent of the RTC oscillator and therefore operational whether or not the oscillator is enabled. TIME AND DATE OPERATION The time and date information is obtained by reading the appropriate register bytes. Table 2 shows the RTC registers. The time and date are set or initialized by writing the appropriate regi ster bytes. The contents of the time and date registers are in BCD format. Hours are in 24 -hour mode. The day-of-week register increments at midnight. Values that correspond to the day of week are user defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. READING THE CLOCK When reading the clock and calendar data, it is possible to access the registers while an update (once per second) occurs. There are three ways to avoid using invalid time and date data. The first method uses the transfer enable (TE) bit in the c ontrol B register. Transfers are halted when a 0 is written to the TE bit. Setting TE to 0 halts updates to the user-acc essible registers, while allowing the internal registers to advance. After the registers are read, the TE bit should be written to 1. TE must be kept at 1 for at least 366 μs to ensure a user register update. The time and date registers can be read and stored in temporary variables. The time and date registers are then read again, and compared to the first values. If the values do not match, the time and date registers should be read a third time and compared to the previous values. This should be done until two consecutive reads of the time and date registers match. The TE bit should always be enabled when using this method for reading the time and date,.
enabled. When the IRQ pin goes active, the time and date information does not change until the next update. It is recommended to halt updates to the external set of double-buffered RTC registers when writing to the clock. registers and allows normal operation to resume. oscillator circuit can result in the clock running fast. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for detailed information. Table 2. Register Map Note: 0 = 0 and are read only. power application; the DS1501/DS1511 should be properly configured/defined during initial configuration.
AM4 must be set as described below for the IRQ or PWR outputs to be activated for a matched alarm condition. occurs for the flags to be set. Table 3. Alarm Mask Bits The DS1501/DS1511 controls and status information for the features are maintained in the following register bits. rises above the power-fail voltage. battery-backup mode, if voltage is applied to VBAUX. default to the once-per-second mode to notify the user of an incorrect alarm setting. written to a 1, the alarm is the result of a match with the day of the week.
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks 15 of 22 Control A Register (0Eh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BLF1 BLF2 PRS PAB TDF KSF WDF IRQF BLF1, Valid RAM and Time Bit 1 (0Eh Bit 7); BLF2, Valid RAM and Time Bit 2 (0Eh Bit 6) These status bits give the condition of any batteries attached to the V BAT or V BAUX pins. The DS1501/DS1511 constantly monitor the battery voltage of the backup-battery sources (VBAT and VBAUX). The BLF1 and BLF2 bits are set to 1 if the battery voltages on V BAT and V BAUX are less than V BLF (typ), otherwise BLF1 and BLF2 bits are 0. BLF1 reflects the condition of VBAT with BLF2 reflecting VBAUX. If either bit is read as 1, the voltage on the respective pin is inadequate to maintain the RAM memory or clock functions. These bits are read only. PRS, Reset Select Bit (0Eh Bit 5) When set to 0, the PWR pin is set high-Z when the DS150/DS1511 go into power-fail. When set to 1, the PWR pin remains active upon entering power-fail. PAB, Power Active-Bar Control Bit (0Eh Bit 4) When this bit is 0, the PWR pin is in the active-low state. When this bit is 1, the PWR pin is in the high-impedance state. The user can write this bit to 1 or 0. If either TDF and TPE = 1 or KSF = 1, the PAB bit is cleared to 0. This bit can be read or written. TDF, Time-of-Day/Date Alarm Flag (0Eh Bit 3) A 1 in the TDF bit indicates that the current time has matched the alarm time. If the TIE bit is also 1, the IRQ pin goes low and a 1 appears in the IRQF bit. This bit is cleared by reading the register or writing it to 0. KSF, Kickstart Flag (0Eh Bit 2) This bit is set to a 1 when a kickstart condition occurs or when the user writes it to 1. If the KIE bit is also 1, the IRQ pin goes low and a 1 appears in the IRQF bit. This bit is cleared by reading the register or writing it to 0. WDF, Watchdog Flag (0Eh Bit 1) If the processor does not access the DS1501/DS1511 with a write within the period specified in addresses 0CH and 0DH, the WDF bit is set to 1. WDF is cleared by writing it to 0. IRQF, Interrupt Request Flag (0Eh Bit 0) The interrupt request flag (IRQF) bit is set to 1 when one or more of the following are true: TDF = TIE = 1 KSF = KIE = 1 WDF = WDE = 1 i.e., IRQF = (TDF x TIE) + (KSF x KIE) + (WDF x WDE) Any time the IRQF bit is 1, the IRQ pin is driven low. Clearing IRQ and Flags The time-of-day/date alarm flag (TDF), watchdog flag (WDF), kickstart flag (KSF), and interrupt request flag (IRQF) are cleared by reading the flag register (0EH). The address must be stable for a minimum of 15ns while CE and OE are active. After the address stable requirement has been met, either a change in address, a rising edge of OE, or a rising edge of CE causes the flags to be cleared. The IRQ pin goes inactive after the IRQF flag is cleared. TDF and WDF can also be cleared by writing to 0.
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks 16 of 22 Control B Register (0Fh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TE CS BME TPE TIE KIE WDE WDS TE, Transfer Enable Bit (0Fh Bit 7) When the TE bit is 1, the update transfer functions norm ally by advancing the count s once per second. When the TE bit is written to 0, any update transfer is inhibit ed and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be exec uted in a similar manner. TE is a read/write bit that is not modified by internal functions of the DS1501/DS1511. CS, Crystal Select Bit (0Fh Bit 6) When CS is set to 0, the oscillator is configured for operation with a cr ystal that has a 6pF specified load capacitance. When CS = 1, the oscillator is configured for a 12.5pF crystal. CS is disabled in the DS1511 module and should be set to CS = 0. BME, Burst-Mode Enable Bit (0Fh Bit 5) The burst-mode enable bit allows the extended user RAM address registers to automatically increment for consecutive reads and writes. When BME is set to 1, the automatic incrementing is enabled; when BME is set to 0, the automatic incrementing is disabled. TPE, Time-of-Day/Date Alarm Power-Enable Bit (0Fh Bit 4) The wakeup feature is controlled through the TPE bit. When the TDF flag bit is set to 1, if TPE is 1, the PWR pin is driven active. Therefore, setting TPE to 1 enables the wa keup feature. Writing a 0 to TPE disables the wakeup feature. TIE, Time-of-Day/Date Alarm Interrupt-Enable Bit (0Fh Bit 3) The TIE bit allows the TDF flag to assert an interrupt. When the TDF flag bit is set to 1, if TIE is 1, the IRQF flag bit is set to 1. Writing a 0 to the TIE bit prevents the TDF fl ag from setting the IRQF flag. This bit is automatically cleared to logic 0 by the internal power-on reset when power is applied and VCC rises above the power-fail voltage. KIE, Kickstart Enable-Interrupt Bit (0Fh Bit 2) The KIE bit allows the KSF flag to assert an interrupt. When t he KSF flag bit is set to 1, if KIE is a 1, the IRQF flag bit is set to 1. Writing a 0 to the KIE bit prevents the KSF flag from setting the IRQF flag. This bit is automatically cleared to logic 0 by the internal power-on reset when power is applied and VCC rises above the power-fail voltage. WDE, Watchdog Enable Bit (0Fh Bit 1) When WDE is set to 1, the watchdog function is enabled, and either the IRQ or RST pin is pulled active, based on the state of the WDS and WDF bits. This bit is automatica lly cleared to logic 0 to by the internal power-on reset when power is applied and VCC rises above the power-fail voltage. WDS, Watchdog Steering Bit (0Fh Bit 0) If WDS is 0 when the watchdog flag bit WDF is set to 1, the IRQ pin is pulled low. If WDS is 1 when WDF is set to 1, the watchdog outputs a negative pulse on the RST output. The WDE bit resets to 0 immediately after RST goes active. This bit is automatically cleared to logic 0 to by the internal power-on reset when power is applied and V CC rises above the power-fail voltage. CLOCK OSCILLATOR CONTROL The clock oscillator can be st opped at any time. To increase the shelf life of a backup lithium-battery source, the oscillator can be turned off to minimize current drain from the battery. The EOSC bit is used to control the state of the oscillator, and must be set to 0 for the oscillator to function. USING THE WATCHDOG TIMER The watchdog timer can be used to restart an out-of-cont rol processor. The watchdog timer is user programmable in 10ms intervals ranging from 0.01 seconds to 99.99 se conds. The user programs t he watchdog timer by writing the timeout value into the two BCD watchdog register s (0Ch and 0Dh). The watchdog reloads and restarts whenever the watchdog times out. Writing the timer will reoad and restart the timer. The timer runs while the device
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks 17 of 22 is powered by either V CC, VBAT, or V BAUX. If either watchdog register is nonzer o, a timeout sets the WDF bit to 1, regardless of the state of the watchdog enable (WDE) bit, to serve as an indication to the processor that a watchdog timeout has occurred. The watchdog timer operates in two modes, repetitive and single-shot. If WDE is 1 and the watchdog steering bit (WDS) is 0, the watchdog is in repetitive mode. When the watchdog times out, both WDF and IRQF are set. IRQ goes active and IRQF goes to 1. The watchdog timer is reloaded when the processor performs a write of the watchdog registers and the timeout period restarts. Reading control A register clears the IRQ flag. If WDE and WDS are 1, the watchdog is in si ngle-shot mode. When the watchdog times out, RST goes active for a period of 40ms to 200ms. When RST goes inactive, WDE resets to 0. Writing a value of 00h to both watchdog registers disables the watchdog timer. The watchdog function is automatically disabled upon power-up by the power-on reset setting WDE = 0 and WDS = 0. The watchdo g registers are not initializ ed at power-up and should be initialized by the user. Note: The TE bit must be used to disable transfers when writing to the watchdog registers. The following summarizes the configurations in which the watchdog can be used: WDE = 0 and WDS = 0: WDF is set. WDE = 0 and WDS = 1: WDF is set. WDE = 1 and WDS = 0: WDF and IRQF are set, and the IRQ pin is pulled low. WDE = 1 and WDS = 1: WDF is set, the RST pin pulses low, and WDE resets to 0. WAKEUP/KICKSTART The DS1501/DS1511 incorporate a wakeup feature, which powers on at a predetermined day/date and time by activating the PWR output pin. Additionally, the kickstart feature allows the system to be powered up in response to a low-going transition on the KS pin, without operating voltage applied to the V CC pin. As a result, system power can be applied upon such events as key closure or a mode m-ring-detect signal. To use either the wakeup or the kickstart features, the DS1501DS1511 must have an auxiliary battery connected to the VBAUX pin, and the oscillator must be running. The wakeup feature is controlled through the time-of- day/date power-enable bit (TPE). Setting TPE to 1 enables the wakeup feature. Transfers (TE) must be enabled for a wake up event to occur. Writing TPE to 0 disables the wakeup feature. The kickstart feature is always enabled as long as VBAUX is present. If the wakeup feature is enabled, while the system is powered down (no V CC voltage), the clock/calendar monitors the current day or date for a match condition with day/date alarm register (0Bh). With the day/date alarm register, the hours, minutes, and seconds alarm bytes in the cloc k/calendar register map (02h, 01h, and 00h) are also monitored. As a result, a wakeup occurs at the day or date and time specified by the day/date, hours, minutes, and seconds alarm register values. This additional alarm occurs regardless of the programming of the TIE bit. When the match condition occurs, the PWR pin is automatically driven low. This output can turn on the main system power supply that provides V CC voltage to the DS1501/DS1511, as well as the other major components in the system. Also at this time, the time-of-day/date alarm flag is set (TDF), indicating a wakeup condition has occurred. If VBAUX is present, while VCC is low, the KS input pin is monitored for a low-going transition of minimum pulse width tKSPW. When such a transition is detected, the PWR line is pulled low, as it is for a wakeup condition. Also at this time, KSF is set, indicating that a kickstart condition has occurred. The KS input pin is always enabled and must not be allowed to float. The timing associated with the wakeup and kickstarting seq uences is illustrated in Figu re 7. These functions are divided into five intervals, labeled 1 to 5 on the diagram. The occurrence of either a kickstart or wakeup condition causes the PWR pin to be driven low, as described above. During Interval 1, if the supply voltage on the V CC pin rises above V SO before the power-on timeout period (t POTO) expires, then PWR remains at the active-low level. If V CC does not rise above the V SO in this time, then the PWR output pin is turned off and returns to its high-impedance level. In this event, the IRQ pin also remains tri-stated.
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks 18 of 22 The interrupt flag bit (either TDF or KSF) associated with the attempted power-on sequence remains set until cleared by software during a subsequent system power-on. If VCC is applied within the timeout period, the system power-on sequence continues, as shown in Intervals 2 to 5 in the timing diagram. During Interval 2, PWR remains active, and IRQ is driven to its active-low level, indicating that either TDF or KSF was set in initia ting the power-on. In the diagram, KS is assumed to be pulled up to the V BAUX supply. Also at this time, the PAB bit is automatically cleared to 0 in response to a successful power-on. The PWR line remains active as long as the PAB remains cleared to 0. At the beginning of Interval 3, the system processor has begun code execution and clears the interrupt condition of TDF and/or KSF by reading the flags register or by writing TDF and KSF to 0. As long as no other interrupt within the DS1501/DS1511 is pending, the IRQ line is taken inactive once these bits are reset, and execution of the application software can proceed. During this time, the wakeup and kickstart functions can be used to generate status and interrupts. TDF is set in response to a day/date, hours, minutes, and sec onds match condition. KSF is set in response to a low-going transition on KS. If the associated interrupt-enable bit is set (TDE and/or KIE), then the IRQ line is driven low in response to enabled event. In addi tion, the other possible interrupt sources within the DS1501/DS1511 can cause IRQ to be driven low. While system power is applied, the on-chip logic always attempts to drive the PWR pin active in response to the enabled kickstart or wakeup condition. This is true even if PWR was previously inactive as the result of power being applied by some means other than wakeup or kickstart. The system can be powered down unde r software control by setting the PAB bit to 1. The PAB bit can only be set to 1 after the TDF and KSF flags have been cleared to 0. Setting PAB to 1 causes the open-drain PWR pin to be placed in a high-impedance state, as shown at the beginning of Interval 4 in the timing diagram. As V CC voltage decays, the IRQ output pin is placed in a high-impedance state when V CC goes below V PF. If the system is to be again powered on in response to a wakeup or kickstart, then both the TDF and KSF flags should be cleared, and TPE and/or KIE should be enabled prior to setting the PAB bit. During Interval 5, the system is fully powered down. Battery backup of the clock calendar and NV RAM is in effect and IRQ is tri-stated, and monitoring of wakeup and kickstart takes place. If PRS = 1, PWR stays active; otherwise, if PRS = 0, PWR is tri-stated. SQUARE-WAVE OUTPUT The square-wave output is enabled and disabled through the E32K bit. If the square wave is enabled ( E32K = 0) and the oscillator is running, then a 32.768kHz square wave is output on the SQW pin. If the battery-backup 32kHz-enable bit (BB32) is enabled, and voltage is applied to V BAUX, then the 32.768kHz square wave is output on the SQW pin in the absence of VCC. BATTERY MONITOR The DS1501/DS1511 constantly monitor the battery voltage of the backu p-battery sources (V BAT and VBAUX). The battery low flags BLF1 and BLF2 are set to 1 if the battery voltages on V BAT and VBAUX are less than V BLF (typical); otherwise, BLF1 and BLF2 are 0. BLF1 monitors VBAT and BLF2 monitors VBAUX. 256 x 8 EXTENDED RAM Two on-chip latch registers control access to the SRAM. One register is used to hold the SRAM address; the other is used to hold read/write data. The SRAM address space is from 00h to FFh. The 8-bit address of the RAM location to be accessed must be loaded into the ext ended RAM address register located at 10h. Data in the addressed location can be read by performing a read operat ion from location 13h, or written to by performing a write operation to location 13h. Data in any addressed location can be read or written repeatedly with changing the address in location 10h. To read or write consecutive extended RAM locations, a burst mode feature can be enabled to increment the extended RAM address. To enable the burst mode feature, set the BME bit to 1. With burst mode enabled, write the extended RAM starting address lo cation to register 10h. Then read or write the extended RAM data from/to register 13h. The extended RAM address locations are automatically incremented on the rising edge of OE, CE, or
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks 19 of 22 WE only when register 13h is being accessed ( Figure 4). The address pointer wraps around after the last address is accessed. ORDERING INFORMATION (continued) PART VOLTAGE (V) TEMP RANGE PIN-PACKAGE TOP MARK* DS1501WN+ 3.3 -40°C to +85°C 28 DIP (0.600) DS1501WN DS1501WZ+ 3.3 0°C to +70°C 28 SO (0.300) DS1501ZS DS1501WZN+ 3.3 -40°C to +85°C 28 SO (0.300) DS1501WZN DS1501WZN+T&R 3.3 -40°C to +85°C 28 SO (0.300)/Tape & Reel DS1501WZN DS1501WZ+T&R 3.3 0°C to +70°C 28 SO (0.300)/Tape & Reel DS1501WZ DS1501Y+ 5.0 0°C to +70°C 28 DIP (0.600) DS1501Y DS1501YE+ 5.0 0°C to +70°C 28 TSOP DS1501YE DS1501YEN+ 5.0 -40°C to +85°C 28 TSOP DS1501YEN DS1501YEN+T&R 5.0 -40°C to +85°C 28 TSOP/Tape & Reel DS1501YEN DS1501YE+T&R 5.0 0°C to +70°C 28 TSOP/Tape & Reel DS1501YE DS1501YN+ 5.0 -40°C to +85°C 28 DIP (0.600) DS1501YN DS1501YZ+ 5.0 0°C to +70°C 28 SO (0.300) DS1501YZ DS1501YZN+ 5.0 -40°C to +85°C 28 SO (0.300) DS1501YZN DS1501YZN+T&R 5.0 -40°C to +85°C 28 SO (0.300)/Tape & Reel DS1501YZN DS1501YZ+T&R 5.0 0°C to +70°C 28 SO (0.300)/Tape & Reel DS1501YZ DS1511W+ 3.3 0°C to +70°C 28 EDIP (0.720) DS1511W DS1511Y+ 5.0 0°C to +70°C 28 EDIP (0.720) DS1511Y +Denotes a lead(Pb)-free/RoHS-compliant package. * A “+” anywhere on the top mark denotes a lead(Pb)-free package. An N or IND denotes an industrial temperature device.
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks 20 of 22 PIN CONFIGURATIONS EDIP N.C. N.C. DQ0 DQ1 DQ2 GND PWR RST IRQ SQW N.C. DQ7 DQ6 DQ5 DQ4 DQ3 CE OE KS WE VBAUX N.C. CCV Maxim DS1511 28 1 OE SQW KS VBAUX VBAT WE VCC IRQ RST PWR GND DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND DQ7 CE TSOP Maxim DS1501 TOP VIEW Maxim DS1501 SQW GND DQ7 DQ6 DQ5 DQ4 DQ3 WE KS OE CE V CC V BAUX V BAT DQ0 DQ1 DQ2 GND PWR RST IRQ DIP, SO
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks 21 of 22 TYPICAL OPERATING CIRCUITS DS1501 CPU VCC VCC VCC IRQ RST GND X2 X1 VCC RPU CRYSTAL SQW VBAT DQ0–DQ7 RST WE OE VBAUX KS PWR CE A0–A4 IRQ GND DS1511 CPU VCC VCC VCC IRQ RST GND VCC RPU SQW DQ0–DQ7 RST WE OE VBAUX KS PWR CE A0–A4 IRQ GND
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE DOCUMENT NUMBER 28-pin DIP (600 mils) 21-0044 28-pin SO (300 mils) 21-0042 28-pin TSOP (8mm x 13.4mm) 21-0273 28-pin EDIP (720 mils) 21-0241
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks 22 of 22 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products is a registered trademark of Maxim Integrated Products.
REVISION HISTORY
Removed the leaded parts from the Ordering Information table. 1, 19 Updated the Features section. 1 Removed the redundant operating temperature range line from the Absolute Maximum Ratings section. 2 Moved the UL information link into the VBAT and VBAUX pin descriptions in the Pin Description table. 9 080508 Added an overview to the Detailed Description section. 11 Replaced 330-mil SO package ordering and top mark information with 300-mil SO package information in the Ordering Information table. 1, 19 010909 Updated the Package Information table. 21