DS1500 MAXIM | Alldatasheet
Document overview
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Technical content
1 of 19 REV: 111705 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS1500 is a full-function, year 2000-compliant real-time clock/calendar (RTC) with an alarm, watchdog timer, power-on reset, battery monitors, 256 bytes of on-board nonvolatile (NV) SRAM, NV control for backing up an external SRAM, and a 32.768kHz output. User access to all registers within the DS1500 is accomplished with a byte-wide interface, as shown in Figure 7. The RTC registers contain century, year, m onth, date, day, hours, minutes, and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for day of month and leap year are made automatically.
APPLICATIONS
Pin Configuration and Typical Operating Circuit appear at end of data sheet.
FEATURES
BCD-Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap-Year Compensation Valid Up to the Year 2100 Programmable Watchdog Timer and RTC Alarm Century Register; Y2K-Compliant RTC Automatic Battery Backup and Write Protection to External SRAM +5V Operation Precision Power-On Reset Power-Control Circuitry Supports System Power-On from Date/Day/Time Alarm or Key Closure 256 Bytes User NV RAM Auxiliary Battery Input Accuracy Better than ±1 Minute/Month at +25°C Day-of-Week/Date Alarm Register Battery Voltage-Level Indicator Flags Industrial Temperature Range: -40°C to +85°C
ORDERING INFORMATION
PART TEMP RANGE VOLTAGE (V) PIN-PACKAGE TOP MARK* DS1500WE 0°C to +70°C 3.3 32 TSOP DS1500W DS1500WE+ 0°C to +70°C 3.3 32 TSOP DS1500W DS1500WEN -40°C to +85° C 3.3 32 TSOP DS1500WN DS1500WEN+ -40°C to +85° C 3.3 32 TSOP DS1500WN DS1500YE 0°C to +70°C 5.0 32 TSOP DS1500Y DS1500YE+ 0°C to +70°C 5.0 32 TSOP DS1500Y DS1500YEN -40°C to +85° C 5.0 32 TSOP DS1500YN DS1500YEN+ -40°C to +85° C 5.0 32 TSOP DS1500YN DS1500YN -40°C to +85°C 5.0 32 TSOP DS1500Y + Denotes a lead-free/RoHS-compliant device. * A “+” anywhere on the top mark indicates a lead-free/RoHS-compliant device. An “N” indicates an industrial temperature range device. DS1500 Y2K Watchdog RTC with Nonvolatile Control www.maxim-ic.com
DS1500 Y2KC Watchdog RTC with Nonvolatile Control 2 of 19 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may c ause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Y 2.2 VCC +
0.3 Logic 1 Voltage All Inputs (Note 2) VIH
W 2.0 VCC + 0.3 V Pullup Voltage, IRQ, PWR, and RST Outputs VPU (Note 2) 5.5 V Y -0.3 +0.8 Logic 0 Voltage All Inputs (Note 2) VIL W -0.3 +0.6 V Battery Voltage (Note 2) VBAT 2.5 3.0 3.7 V DC ELECTRICAL CHARACTERISTICS (VCCMIN < VCCI < VCCMAX, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Y 15 Active Supply Current (Note 3) I CC W 10 mA Y 5 TTL Standby Current (CS = VIH) I CC1 W 4 mA Y 5 CMOS Standby Current (CS ≥ VCCI - 0.2V) ICC2 W 4 mA Input Leakage Current (Any Input) I IL -1 +1 µA Output Leakage Current (Any Output) I OL -1 +1 µA Output Logic 1 Voltage (IOUT = -1.0mA) V OH (Note 2) 2.4 V VOL1 (Note 2) 0.4 V Output Logic 0 Voltage (IOUT = 2.1mA, DQ0–7, CEO IOUT = 5.0mA, IRQ, IOUT = 7.0mA PWR, and RST) VOL2 (Notes 2, 4) 0.4 V Y 2.0 Battery Low, Flag Trip Point (Note 2) V BLF W 1.9 V Y Output Voltage (ICCO1 = 85mA ) (Note 5) V CCO1 W VCCI - 0.3 V Y 4.20 4.50 Power-Fail Voltage (Note 2) V PF W 2.75 2.97 V Battery Switchover Voltage V SO (Notes 2, 6) VBAT, VBAUX, or VPF V Output Voltage (ICCO2 = 50µA) V CCO2 (Note 7) VBAT - 0.3 V Battery Leakage Current I LKG 10 100 nA
DS1500 Y2KC Watchdog RTC with Nonvolatile Control 3 of 19 DC ELECTRICAL CHARACTERISTICS (VCC = 0V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Battery Current, BB32 = 0, EOSC = 0 IBAT1 (Notes 8, 9) 0.27 1.0 µA Battery Current, BB32 = 0, EOSC = 1 IBAT2 (Notes 8, 9) 0.01 0.1 µA VBAUX Current BB32 = 1, SQW Open I BAUX (Notes 8, 9) 2 µA CRYSTAL SPECIFICATIONS* PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Nominal Frequency f O 32.768 kHz Series Resistance ESR 45 kΩ Load Capacitance C L 6 pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. AC OPERATING CHARACTERISTICS (VCCI = 5.0V ±10%, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Read Cycle Time t RC 70 ns Address Access Time t AA 70 ns CS to DQ Low-Z tCSL (Note 10) 5 ns CS Access Time tCSA 70 ns CS Data Off Time tCSZ (Note 10) 25 ns OE to DQ Low-Z (0°C to +85°C) tOEL (Note 10) 5 ns OE to DQ Low-Z (-40°C to 0°C) tOEL (Note 10) 2 ns OE Access Time tOEA 35 ns OE Data Off Time tOEZ (Note 10) 25 ns Output Hold from Address t OH 5 ns Write Cycle Time t WC 70 ns Address Setup Time t AS 0 ns WE Pulse Width tWEW 50 ns CS Pulse Width tCSW 55 ns Data Setup Time t DS 30 ns Data Hold Time t DH 5 ns Address Hold Time t AH 0 ns WE Data Off Time tWEZ (Note 10) 25 ns Write Recovery Time t WR 15 ns CEI to CEO Propagation Delay tCEPD 10 ns Pulse Width, OE, WE, or CS High PWHIGH 20 ns Pulse Width, OE, WE, or CS Low PWLOW 70 ns
Figure 1. Read Cycle Timing
Figure 4. Burst Mode Timing Waveform
Figure 5. 5V Power-Up/Down Waveform Timing device is in battery-backup mode.
Note: Time intervals shown above are referenced in Wakeup/Kickstart. Figure 6. Wakeup/Kickstart Timing Diagram Note 1: Limits at -40°C are not production tested and are guaranteed by design. Note 2: Voltage referenced to ground. Note 4: The IRQ, PWR, and RST outputs are open drain. Note 5: Value for voltage and currents is from the VCCI input pin to the VCCO pin. Note 7: Value for voltage and currents is from the VBAT or VBAUX input pin to the VCCO pin. Note 8: IBAT1 and IBAT2 are specified with VCCO floating and do not include any RAM current. Note 9: VBAT or VBAUX current. Using a 32,768Hz crystal connected to X1 and X2. Note 10: These parameters are sampled with a 5pF load and are not 100% tested. Note 11: Typical values are at +25°C, nominal (active) supply, unless otherwise noted. Note 12: If the oscillator is not enabled, the startup time of the oscillator after VCCI is applied is added to the wakeup/kickstart timeout.
DS1500 Y2KC Watchdog RTC with Nonvolatile Control 9 of 19 PIN DESCRIPTION PIN NAME FUNCTION
1 SQW
Square-Wave Output. When enabled, the SQW pin outputs a 32.768kHz square wave. If the square wave (E32K) and battery-backup 32kHz (BB32) bits are enabled, power is provided by VBAUX when VCC is absent. 2 KS Kickstart Input. This pin is used to wake up a system from an external event, such as a key closure. The KS pin is normally connected using a pullup resistor to VBAUX. If the KS function is not used, connect to ground.
3 V BAT
Battery input for any standard 3V lithium cell or other energy source. Battery voltage must be held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse charging current when used with a lithium battery. If not used, connect to ground.*
4 V BAUX
Auxiliary battery input for any standard 3V lithium cell or other energy source. Battery voltage must be held between 2.5V and 3.7V for proper operation. Provides backup power to the device, and provides power for auxiliary functions. UL recognized to ensure against reverse charging current when used with a lithium battery. If not used, connect to ground.* 5 CEO Chip-Enable Output. Buffered chip-enable output signal for external SRAM switches high when VCCI falls below the power-fail point VPF. 6 CEI Chip-Enable Input. Input for chip-enable signal for external SRAM. 7 WE Write-Enable Input. Active-low input that enables DQ0–DQ7 for data input to the device.
8 V CC1
DC power is applied to the device on these pins. VCC is the positive terminal. When power is applied within the normal limits, the device is fully accessible and data can be written and read. When VCC drops below the normal limits, reads and writes are inhibited. As VCC drops below the battery voltage, the RAM and timekeeping circuits are switched over to the battery. 9 V CC0 Buffered VCC output to external SRAM. Switches to either VBAT or VBAUX when in data retention mode. 10 N.C. No Connect 11 PWR Power-On Output (Open Drain). This output, if used, is normally connected to power-supply control circuitry. This pin requires a pullup resistor connected to a positive supply to operate correctly. 12, 13 X1, X2 Connections for a standard 32.768kHz quartz crystal. For greatest accuracy, the DS1500 must be used with a crystal that has a specified load capacitance of either 6pF or 12.5pF. The crystal select (CS) bit in control register B is used to select operation with a 6pF or 12.5pF crystal. The crystal is attached directly to the X1 and X2 pins. There is no need for external capacitors or resistors. An external 32.768kHz oscillator can also drive the DS1500. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. See Figure 8.
14 RST
Reset Output (Open Drain). This output, if used, is normally connected to a microprocessor-reset input. This pin requires a pullup resistor connected to a positive supply to operate correctly. When RST is active, the device is not accessible. 15 IRQ Interrupt Output (Open Drain). This output, if used, is normally connected to a microprocessor interrupt input. This pin requires a pullup resistor connected to a positive supply to operate correctly. 16–20 A4–A0 Address Inputs. Selects one of 17 register locations. 21–23, 25–29 DQ0–DQ7 Data I/O pins for 8-bit parallel data transfer. 24, 31 GND DC power is applied to the device on these pins. VCC is the positive terminal. When power is applied within the normal limits, the device is fully accessible and data can be written and read. When VCC drops below the normal limits, reads and writes are inhibited. As VCC drops below the battery voltage, the RAM and timekeeping circuits are switched over to the battery. 30 CS Chip-Select Input. Active-low input to enable the device. 32 OE Output-Enable Input. Active-low input that enables DQ0–DQ7 for data output from the device *See “Conditions of Acceptability” at www.maxim-ic.com/TechSupport/QA/ntrl.htm.
occurs regardless of external register settings to guarantee that accurate RTC information is always maintained. operation caused by low VCCI levels. An external SRAM can be made nonvolatile by using the V CCO and CEO pins. returns and stabilizes; the RST output is used for this function. only components required to maintain time-of-day and memory status in the absence of power.. Table 1. RTC Operating Modes goes indeterminate until the next address access (Table 1). defined by the address inputs. A low transition on WE then disables the outputs tWEZ after WE goes active (Table 1).
DS1500 Y2KC Watchdog RTC with Nonvolatile Control 12 of 19 DATA RETENTION MODE The DS1500 is fully accessible and data can be written and read only when V CCI is greater than V PF. However, when VCCI falls below the power-fail point V PF (point at which write protection oc curs) the internal clock registers and SRAM are blocked from any access. While in the dat a retention mode, all inputs are don’t cares and outputs go to a high-Z state, with the exception of VCCO, CEO, and with the possible exception of KS, PWR, SQW, and RST. CEO is forced high. If VPF is less than VBAT and VBAUX, the device power is switched from VCCI to the greater of VBAT and V BAUX when V CCI drops below V PF. If V PF is greater than V BAT and V BAUX, the device power and V CCO are switched from V CCI to the larger of V BAT and V BAUX when V CCI drops below the larger of V BAT and V BAUX. RTC operation and SRAM data are maintained from the battery until V CC is returned to nominal levels (Table 1). If the square-wave and battery-backup 32kHz functions are enabled, V BAUX always provides power for the square-wave output, when the device is in battery-backup mode. All c ontrol, data, and address signals must be no more than 0.3V above VCCI. AUXILIARY BATTERY The VBAUX input is provided to supply power from an auxilia ry battery for the DS1500 kickstart and square-wave output features in the absence of V CCI. This power source must be available to use these auxiliary features when no VCCI is applied to the device. This auxiliary battery can be used as the primary back up power source for maintaining the clock/calendar and external SRAM. This occurs if the VBAT pin is at a lower voltage than VBAUX. If the DS1500 is to be backed-up using a single battery with the aux iliary features enabled, then V BAUX should be used and connected to V BAT. If V BAUX is not to be used, it should be grounded. POWER-ON RESET A temperature-compensated comparator circuit monitors the level of V CCI. When V CCI falls to the power-fail trip point, the RST signal (open drain) is pulled low. When VCCI returns to nominal levels, the RST signal continues to be pulled low for a period of t REC. The power-on reset function is independent of the RTC oscillator and therefore operational whether or not the oscillator is enabled. TIME AND DATE OPERATION The time and date information is obtained by reading t he appropriate register bytes. Table 2 shows the RTC registers. The time and date are set or initialized by writing the appropriate register bytes. The contents of the time and date registers are in the binary-coded decimal (BCD ) format. Hours are in 24-hour mode. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. READING THE CLOCK When reading the clock and calendar data, it is possible to access the registers while an update (once per second) occurs. There are three ways to avoid using invalid time and date data. The first method uses the transfer enable (TE) bit in the c ontrol B register. Transfers are halted when a 0 is written to the TE bit. Setting TE to 0 halts updates to the user-acc essible registers, while allowing the internal registers to advance. After the registers are read, the TE bit should be wr itten to 1. TE must be kept at 1 for at least 366µs to ensure a user register update. The time and date registers can be read and stored in te mporary variables. The time and date registers are then read again, and compared to the first values. If the values do not match, the time and date registers should be read a third time and compared to the previous values. This should be done until two consecutive reads of the time and date registers match. The TE bit should always be enabled when using this method for reading the time and date,. The third method of reading the time and date uses the al arm function. The alarm can be configured to activate once per second, and the time-of-day alarm-interrupt enable bit (TIE) is enabled. The TE bit should always be enabled. When the IRQ pin goes active, the time and date information does not change until the next update.
It is recommended to halt updates to the external set of double buffered RTC registers when writing to the clock. registers and allows normal operation to resume. an external oscillator the X2 pin must be left open. Accuracy of DS1510 is better than ±1min/month at +25°C. Table 2. Register Map These bits are set upon power-up: EOSC = 0, E32K = 0, TIE = 0, KIE = 0, WDE = 0, and WDS = 0. power application; the DS1500 should be properly configured/defined during initial configuration. AM4 must be set as described below for the IRQ or PWR outputs to be activated for a matched alarm condition.
enables the alarm flag to activate the PWR pin. The alarm functions on VCC, VBAT, and VBAUX. Table 3. Alarm Mask Bits The controls and status information for the DS1500 features are maintained in the following register bits. rises above the power-fail voltage. default to the once-per-second mode to notify the user of an incorrect alarm setting. written to a 1, the alarm is the result of a match with the day of the week.
DS1500 Y2K Watchdog RTC with Nonvolatile Control 15 of 19 Control A Register (0Eh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BLF1 BLF2 PRS PAB TDF KSF WDF IRQF BLF1, Valid RAM and Time Bit 1 (0Eh Bit 7); BLF2, Valid RAM and Time Bit 2 (0Eh Bit 6) These status bits give the condition of any batteries attached to the V BAT or V BAUX pins. The DS1500 constantly monitors the battery voltage of the backup-battery sources (VBAT and VBAUX). The BLF1 and BLF2 bits are set to 1 if the battery voltage on V BAT and V BAUX is less than V BLF, otherwise BLF1 and BLF2 bits are 0. BLF1 reflects the condition of VBAT with BLF2 reflecting VBAUX. If either bit is read as 1, the voltage on the respective pin is inadequate to maintain the RAM memory or clock functions. These bits are read only. PRS, Reset Select Bit (0Eh Bit 5) When set to 0, the PWR pin is set high-Z when the DS1500 goes into power-fail. When set to 1, the PWR pin remains active upon entering power-fail. PAB, Power Active-Bar Control Bit (0Eh Bit 4) When this bit is 0, the PWR pin is in the active-low state. When this bit is 1, the PWR pin is in the high-impedance state. The user can write this bit to 1 or 0. If either TD F AND TPE = 1 or KSF = 1, the PAB bit is cleared to 0. This bit can be read or written. TDF, Time-of-Day/Date Alarm Flag (0Eh Bit 3) A 1 in the TDF bit indicates that the current time has matched the alarm time. If the TIE bit is also 1, the IRQ pin goes low and a 1 appears in the IRQF bit. This bit is cleared by reading the register or writing it to 0. KSF, Kickstart Flag (0Eh Bit 2) This bit is set to 1 when a kickstart condition occurs or when the user writes it to 1. If the KIE bit is also 1, the IRQ pin goes low and a 1 appears in the IRQF bit. This bit is cleared by reading the register or writing it to 0. WDF, Watchdog Flag (0Eh Bit 1) If the processor does not access the DS1500 with a write within the period specified in addresses 0CH and 0DH, the WDF bit is set to 1. WDF is cleared by writing it to 0. IRQF, Interrupt Request Flag (0Eh Bit 0) The interrupt request flag (IRQF) bit is set to 1 when one or more of the following are true: TDF = TIE = 1 KSF = KIE = 1 WDF = WDE = 1 i.e., IRQF = (TDF x TIE) + (KSF x KIE) + (WDF x WDE) Any time the IRQF bit is 1, the IRQ pin is driven low. Clearing IRQ and Flags The time-of-day/date alarm flag (TDF), watchdog flag (WDF), kickstart flag (KSF) and interrupt request flag (IRQF) are cleared by reading the flag register (0EH). The address must be stable for a minimum of 15ns while CS and OE are active. After the address stable requirement has been met, either a change in address, a rising edge of OE, or a rising edge of CS causes the flags to be cleared. The IRQ pin goes inactive after the IRQF flag is cleared. TDF and WDF can also be cleared by writing to 0.
DS1500 Y2K Watchdog RTC with Nonvolatile Control 16 of 19 Control B Register (0Fh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TE CS BME TPE TIE KIE WDE WDS TE, Transfer Enable Bit (0Fh Bit 7) When the TE bit is 1, the update transfer functions norm ally by advancing the count s once per second. When the TE bit is written to 0, any update transfer is inhibi ted and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be exec uted in a similar manner. TE is a read/write bit that is not modified by internal functions of the DS1500. CS, Crystal Select Bit (0Fh Bit 6) When CS is set to 0, the oscillator is configured for operation with a cr ystal that has a 6pF specified load capacitance. When CS = 1, the oscillator is configured for a 12.5pF crystal. CS is disabled in the DS1510 module and should be set to CS = 0. BME, Burst-Mode Enable Bit (0Fh Bit 5) The burst-mode enable bit allows the extended user RAM address registers to automatically increment for consecutive reads and writes. When BME is set to 1, the automatic incrementing is enabled; when BME is set to 0, the automatic incrementing is disabled. TPE, Time-of-Day/Date Alarm Power-Enable Bit (0Fh Bit 4) The wakeup feature is controlled through the TPE bit. W hen the TDF flag bit is set to 1, if TPE is 1, the PWR pin is driven active. Therefore, setting TPE to 1 enables the wa keup feature. Writing a 0 to TPE disables the wakeup feature. TIE, Time-of-Day/Date Alarm Interrupt-Enable Bit (0Fh Bit 3) The TIE bit allows the TDF flag to assert an interrupt. When the TDF flag bit is set to 1, if TIE is 1, the IRQF flag bit is set to 1. Writing a 0 to the TIE bit prevents the TDF flag from setting the IRQF flag. KIE, Kickstart Enable-Interrupt Bit (0Fh Bit 2) When V CCI voltage is absent and KIE is set to 1, the PWR pin is driven active low when a kickstart condition occurs (KS pulsed low), causing the KSF bit to be set to 1. When VCCI is then applied, the IRQ pin is also driven low. If KIE is set to 1 while system power is applied, both IRQ and PWR are driven low in response to KSF being set to 1. When KIE is cleared to a 0, the KSF bit has no effect on the PWR or IRQ pins. WDE, Watchdog Enable Bit (0Fh Bit 1) When WDE is set to 1, the watchdog function is enabled, and either the IRQ or RST pin is pulled active based on the state of the WDS and WDF bits. This bit is automatica lly cleared to logic 0 to by the internal power-on reset when power is applied and V CC rises above the power-fail voltage. WDS, Watchdog Steering Bit (0Fh Bit 0) If WDS is 0 when the watchdog flag bit WDF is set to 1, the IRQ pin is pulled low. If WDS is 1 when WDF is set to 1, the watchdog outputs a negative pulse on the RST output. The WDE bit resets to 0 immediately after RST goes active. This bit is automatically cleared to logic 0 to by the internal power-on reset when power is applied and V CC rises above the power-fail voltage. CLOCK OSCILLATOR CONTROL The clock oscillator can be st opped at any time. To increase the shelf life of a backup lithium-battery source, the oscillator can be turned off to minimize current drain from the battery. The EOSC bit is used to control the state of the oscillator, and must be set to 0 for the oscillator to function. USING THE WATCHDOG TIMER The watchdog timer can be used to restart an out-of-cont rol processor. The watchdog timer is user programmable in 10ms intervals ranging from 0.01 seconds to 99.99 se conds. The user programs t he watchdog timer by writing the timeout value into the two BCD watchdog registers (address 0Ch and 0Dh). The watchdog reloads and restarts whenever the watchdog times out. If either watchdog regi ster is nonzero, a timeout sets the WDF bit to 1,
DS1500 Y2K Watchdog RTC with Nonvolatile Control 17 of 19 regardless of the state of the watchdog enable (WDE) bit, to serve as an indication to the processor that a watchdog timeout has occurred. The watchdog timer operates in two modes, repetitive and single-shot. If WDE is 1 and the watchdog steering bit (WDS) is 0, the watchdog is in repetitive mode. When the watchdog times out, both WDF and IRQF are set. IRQ goes active and IRQF goes to 1. The watchdog timer is reloaded when the processor performs a write of t he watchdog registers and the timeout pe riod restarts. Reading the control A register clears the IRQ flag. If WDE and WDS are 1, the watchdog is in si ngle-shot mode. When the watchdog times out, RST goes active for a period of t REC. When RST goes inactive, WDE resets to 0. Writing a value of 00h to both watchdog registers disables the watchdog timer. The watchdog function is automatically disabled up on power-up by the power-on reset setting WDE = 0 and WDS = 0. The watchdog registers are not initialized at power-up and should be initialized by the user. Note: The TE bit must be used to disable transfers when writing to the watchdog registers. The following summarizes the configurations in which the watchdog can be used: WDE = 0 and WDS = 0: WDF is set. WDE = 0 and WDS = 1: WDF is set. WDE = 1 and WDS = 0: WDF and IRQF are set, and the IRQ pin is pulled low. WDE = 1 and WDS = 1: WDF is set, the RST pin pulses low, and WDE resets to 0. WAKEUP/KICKSTART The DS1500 incorporates a wakeup feature, which powers on at a predetermined date by activating the PWR output pin. In addition, the kickstart feature allows the system to be powered up in response to a low-going transition on the KS pin, without operating voltage applied to the VCCI pin. As a result, system power can be applied upon such events as key closure, or a modem-ring-detects signal. To use either the wakeup or the kickstart features, the DS1500 must have an auxiliary battery connected to the VBAUX pin, and the oscillator must be running. The wakeup feature is controlled through the time-of- day/date power-enable bit (TPE). Setting TPE to 1 enables the wakeup feature. Transfers (TE) must be enabled for a wake up event to occur. Writing TPE to 0 disables the wakeup feature. Similarly, the kickstart feature is controlled through the kickstart interrupt-enable bit (KIE). If the wakeup feature is enabled, whil e the system is powered down (no V CCI voltage), the clock/calendar monitors the current day or date for a match condition with day/date alarm register (0Bh). With the day/date alarm register, the hours, minutes, and seconds alarm bytes in the cloc k/calendar register map (02h, 01h, and 00h) are also monitored. As a result, a wakeup occurs at the day or date and time specified by the day/date, hours, minutes, and seconds alarm register values. This additional alarm occurs regardless of the programming of the TIE bit. When the match condition occurs, the PWR pin is automatically driven low. This output can turn on the main system power supply, which provides V CCI voltage to the DS1500 as well as the other major components in the system. Also, at this time, the time-of-day/date alarm flag is set, indicating that a wakeup condition has occurred. If VBAUX is present, while VCC is low, the KS input pin is monitored for a low-going transition of minimum pulse width tKSPW. When such a transition is detected, the PWR line is pulled low, as it is for a wakeup condition. Also at this time, KSF is set, indicating that a kickstart condition has occurred. The KS input pin is always enabled and must not be allowed to float. The timing associated with these functions is divided into five intervals, labeled 1 to 5 on the diagram. The occurrence of either a kickstart or wakeup condition causes the PWR pin to be driven low, as described above. During Interval 1, if the supply voltage on the V CCI pin rises above the greater of V BAT or V PF before the power-on timeout period (tPOTO) expires, then PWR remains at the active-low level. If V CCI does not rise above the greater of VBAT or VPF in this time, then the PWR output pin is turned off and returns to its high-impedance level. In this event, the IRQ pin also remains tri-stated. The interrupt flag bit (e ither TDF or KSF) associated with the attempted power- on sequence remains set until cleared by software during a subsequent system power-on.
DS1500 Y2K Watchdog RTC with Nonvolatile Control 18 of 19 If VCCI is applied within the timeout period, then the system power-on sequence continues, as shown in Intervals 2 to 5 in the timing diagram. During Interval 2, PWR remains active, and IRQ is driven to its active-low level, indicating that either TDF or KSF was set in initiating the power-on. In the diagram, KS is assumed to be pulled up to the VBAUX supply. Also at this time, the PAB bit is automatical ly cleared to 0 in response to a successful power- on. The PWR line remains active as long as the PAB remains cleared to 0. At the beginning of Interval 3, the system processor has begun code execution and clears the interrupt condition of TDF and/or KSF by writing 0s to both of these control bi ts. As long as no other interrupt within the DS1500 is pending, the IRQ line is taken inactive once these bits are rese t, and execution of the application software can proceed. During this time, the wakeup and kickstart functions can be used to generate status and interrupts. TDF is set in response to a day/date, hours, minutes, and seconds ma tch condition. KSF is set in response to a low-going transition on KS. If the associated interrupt-enable bi t is set (TDE and/or KIE), then the IRQ line is driven low in response to enabled event. In addition, the other possible interrupt sources within the DS1500 can cause IRQ to be driven low. While system power is applied, the on-chip logic always attempts to drive the PWR pin active in response to the enabled kickstart or wa keup condition. This is true even if PWR was previously inactive as the result of power being applied by some means other than wakeup or kickstart. The system can be powered down unde r software control by setting the PAB bit to 1. This causes the open-drain PWR pin to be placed in a high-impedance state, as shown at the beginning of Interval 4 in the timing diagram. As VCCI voltage decays, the IRQ output pin is placed in a high-impedance state when V CCI goes below V PF. If the system is to be again powered on in response to a wakeup or kickstart, then both the TDF and KSF flags should be cleared, and TPE and/or KIE should be enabled prior to setting the PAB bit. During Interval 5, the system is fully powered down. Battery backup of the clock calendar and NV RAM is in effect and IRQ is tri-stated, and monitoring of wakeup and kickstart takes place. If PRS = 1, PWR stays active; otherwise, if PRS = 0, PWR is tri-stated. SQUARE-WAVE OUTPUT The square-wave output is enabled and disabled through the E32K bit. If the square wave is enabled ( E32K = 0) and the oscillator is running, then a 32.768kHz square wave is output on the SQW pin. If the battery-backup 32kHz-enable bit (BB32) is enabled, and voltage is applied to V BAUX, then the 32.768kHz square wave is output on the SQW pin in the absence of VCCI. BATTERY MONITOR The DS1500 constantly monitors the battery voltage of the backup-battery sources (V BAT and VBAUX). The battery low flags BLF1 and BLF2 are set to 1 if the battery voltages on V BAT and V BAUX are less than 2.5V (typical); otherwise, BLF1 and BLF2 are 0. BLF1 monitors VBAT and BLF2 monitors VBAUX. 256 x 8 EXTENDED RAM The DS1500 provides 256 x 8 of on-chip SRAM, which is c ontrolled as nonvolatile storage sustained from a lithium battery. On power-up, the RAM is taken out of write-protect status by an internal signal. Two on-chip latch registers control access to the SRAM. O ne register is used to hold the SRAM address; the other is used to hold read/write data. The SRAM address space is from 00h to FFh. The 8-bit address of the RAM location to be accessed must be loaded into the ext ended RAM address register located at 10h. Data in the addressed location can be read by performing a read operat ion from location 13h, or written to by performing a write operation to location 13h. Data in any addressed lo cation can be read or written repeatedly with changing the address in location 10h. To read or write consecutive extended RAM locations, a burst mode feature can be enabled to increment the extended RAM address. To enable the burst mode feature, set the BME bit to 1. With burst mode enabled, write the extended RAM starting address lo cation to register 10h. Then read or write the extended RAM data from/to register 13h. The extended RAM address locations ar e automatically incremented on the rising edge of OE, CS, WE only when register 13h is being accessed (Figure 4). The address pointer wraps around after the last address is accessed.
DS1500 Y2K Watchdog RTC with Nonvolatile Control 19 of 19 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products • Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. PIN CONFIGURATION TYPICAL OPERATING CIRCUIT
PACKAGE INFORMATION
(For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) Dallas Semiconductor DS1500 CPU VCC VCCI IRQ RST GND X2X1 RPU CRYSTAL SQW VBAT DQ0–DQ7 RST VBAUX KS PWR CE A0–A4 IRQ GND SRAM WE OE CEI CEO CE VCCO VCC VCC VCC TOP VIEW Dallas Semiconductor DS1500 TSOP (8mm x 20mm)