DS1481 MAXIM | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 10
Technical content
FEATURES
Provides a synchronous interface to Dallas Semiconductor 1-Wire devices Compatible with low power parallel ports (can be used with microcontrollers) Can be cascaded with other DS1481s Allows print spooler and other processes to run during 1-Wire I/O Provides high speed communication with overdrive capable devices Space saving 14-pin (150 mil), SO package Recommended for short 1-Wire networks less than 3 inches. Longer 1-Wire lengths can be achieved with the DS2480B. PIN CONFIGURATION PIN DESCRIPTION VCC - Supply ENI - Enable In D/CLK - Data/Clock RES - Reset O1/BSY1 - Output 1/Busy 1 O2/BSY2 - Output 2/Busy 2 GND - Ground I1 - Input 1 I2 - Input 2 I/O - 1-Wire ENO - Enable Out NC - No connection
DESCRIPTION
The DS1481 is a dedicated 1-Wire ® timing generator. The device is normally used in conjunction with a parallel port controller to provide the necessary interface to the host processor. Busy signals allow the host processor to perform other tasks while 1-Wire “time-slots” are completed. The DS1481 also saves the state of D/CLK and RES, allowing print spoolers to operate without affecting 1-Wire communication. DS1481 based devices can be cascaded. The first de vice’s O1/BSY1 and O2/BSY2 connect to the PC printer port’s BUSY and SELECT OUT signals (pins 11 and 13 respectively). The next DS1481 connects its O1/BSY1 and O2/BSY2 to the first device’s I1 and I2 respectively. ENO of the first device connects to ENI of the second devi ce. More DS1481s can be stacked in a sim ilar manner. The last device’s I1 and I2 connect to BUSY and SELECT of the attached printer. DS1481 1-Wire Bus Master with Overdrive www.maxim-ic.com Vcc 1 14 I/O ENI 2 13 ENO O1/BSY1 3 12 I1 O2/BSY2 4 11 I2 D/CLK 5 10 NC RES 6 9 NC NC 7 8 GND 14-PIN SO (150 MIL) 1-Wire is a registered trademark of Dallas Semiconductor. Not Recommended for New Design
The DS1481’s 3V operation insures comp atibility with most low power parallel ports (i.e., portable computers). DEVICE OPERATION 1-Wire communication is executed in “time slots”. The DS1481 generate s either a read/w rite bit “time slot” or a reset on the I/O pin. The operation performed is determined by the states of the D/CLK and RES pins as follows: TIME SLOT D/CLK RES Toggle Speed logic low l ogic low (see Figure 7) Read 0, Read 1, Write 1 logic high logic high (see Figure 4) Write 0 logic low logic high (see Figure 5) 1-Wire Reset logic high logic low (see Figure 6) After D/CLK and RES have been set, the time slot begins when ENI is driven to its active state. A falling edge on ENI causes the DS1481 to save the state of D/CLK and RES. If the time slot is a 1-Wire reset the DS1481 will issue a busy signal by driving O1/BSY1 low and O2/BSY2 high. After 2 μs O2/BSY2 is driven low. Both outputs will rema in low until the communication on the I/O line is finished. A busy signal for a bit time slot differs from the reset bus y signal only in that both O1/BSY1 and O2/BSY2 are driven low immediately. While the busy signal is asserted, the host processor is free to perform other tasks (including running the print spooler). When the time slot is complete, the DS1481 restores both O1/B SY1 and O2/BSY2 to the states of I1 and I2 (see Figure 1). When the host detects that one or both of the busy signals has returned high, it must query the result of the time slot. This is accomplished by driving D/CLK lo w. If the result of the time slot was low (Read 0, Write 0 or presence detect) the DS1481 drives both O1/BSY1 and O2/BSY2 low (t his state is held until ENI returns high). Otherwise it propagates the states of I1 and I2. After the host reads the result of the time slot it must drive ENI to its inactive st ate (high). The DS1481 will then set O1/BSY1 and O2/BSY2 to the states of I1 and 1-WIRE TIMING GENERATION For all time slots, the DS1481 samples the I/O pin at t SO (see Figure 4). The DS1481 waits a minimun of 60μs from the start of the time slot and de-asserts O1/BSY1 and O2/BSY2. When a reset is requested, the DS1481 dr ives the I/O pin low for at least 480 μs and then releases it. During a normal reset the I/O pin immediately begins to return high. If a 1-Wire device is present on the I/O line it pulls I/O low after time T (15 μs ≤ T ≤ 60μs) from the previous rising edge. The 1-Wire device(s) holds the I/O line low for 4T and then releases it, allowing the I/O line to return high. This is the presence detect pul se. The I/O line must remain high (in its idle state) for at least 3T before the 1-Wire device(s) is ready for further commun ication. To ensure this idle high time is satisfied, the DS1481 does not releas e O1/BSY1 and O2/BSY2 for at least 960μs (measured from the 1st falling edge on the I/O pin). Not Recommended for New Design
If after 480μs of low time the I/O line did not return high, either the I/O line has been shorted to ground or there is at least one 1-Wire devi ce connected to the I/O line which is issuing an alar m interrupt (see Figure 6). In this case the DS1481 waits for I/O to return high for an additional 3840 μs (64 * 60). If time expires the I/O line is assumed to be shorted and the DS1481 releases O1/BSY1 and O2/BSY2. If the I/O line returns high, the DS1481 continues to monitor the presen ce detect portion of th e reset (as described above) as for the non-interrupt case. No te that the 3T idle high time is still required after the presence detect ends. OVERDRIVE The DS1481 also supports overdrive communication w ith overdrive capable 1-Wire devices. When the DS1481 powers up it is in normal m ode (i.e., OD = 0, Figure 1). To t oggle to overdrive mode the host sets D/CLK and RES low and drives ENI low. The DS1481 toggles the OD bit to a logic high and returns the states of I1 and I2 on O1/BSY1 and O2/BSY2. Ov erdrive mode is cleared in the same way. When overdrive is turned off (OD = 0). O1/BSY1 and O2/BSY2 are driven low to report the state of the OD bit. When OD = 1, communication with the 1-Wire device is exactly as de scribed in the operation section above. The actual 1-Wire timing for both modes of operation is described in Figures 4, 5, and 6. Note that when toggling the OD bit there is no change on the I/O line. PRINTER COEXISTENCE In order to coexist with parallel port pr inters, the DS1481 utilizes two i nput pins (I1 an d I2) and two output pins (O1/BSY1 and O2/BSY2). When ENI is low these pins are used for transmitting data received on the I/O pin or for issuing an unmistakable busy signal. When ENI is inactive (high) O1/BSY1 and O2/BSY2 propagate the states of I1 and I2. If a printer is attached to a DS1481, I1 is connected to the printers BUSY signal (low only if printer is on line and busy), and I2 is connected to SELECT OUT (driven low if printer is off line), see Figure 2. If the attached printer is “pow ered up” and on line, the DS1481 us es SELECT OUT fo r communication regardless of the state of the printer’s BUSY signal. If the printer is off line its BUSY signal is inactive (high) and this line is used by the DS1481 for host communication. If the attached printer is powered off, both S ELECT OUT and BUSY will be low. This prevents meaningful communication with the DS1481 because it is unable to de -assert its busy signal (O1/BSY1 and O2/BSY2 low) or return a high sample of the I/O pin. To solve this problem, the DS1481 uses the busy signal issued during a reset to detect the presence of another DS1481 based device attached be hind it on the parallel por t. If this busy signal is not detected by the DS1481, it assumes that it is the last DS1481 based device on the port. If the DS1481 determines that it is the last de vice on the port it ignores the st ates of its I1 and I2 pins while ENI is low. It also leaves the ENO pin high to prevent sending line feed signals to the printer. This gives the last device the ability to control O1/BSY1 and O2/BSY2 without affecting stackability. Not Recommended for New Design
the end of the four overdrive toggles to enter transparent mode. to take the DS1481 out of transparent mode and perform 1-Wire I/O operations. Figure 1. DS1481 FUNCTIONAL BLOCK DIAGRAM
VCC DC supply voltage. ENI I Chip enable, driven low to begin 1-Wire I/O. O1/BSY1 O Driven low during time slot (to indicate a DS1481 busy condition). Set to state of I1 after time slot has finished. O1/BSY1 will go low after D/CLK goes low if sample of I/O communication was low. Returns to state of I1 when ENI goes back high (see Figure 1). O2/BSY2 O Driven low during time slot (to indicate a DS1481 busy condition). Set to state of I2 after time slot has finished. O2/BSY2 will go low after D/CLK goes low if sample of I/O communication was low. Returns to state of I2 when ENI goes back high (see Figure 1). D/CLK I Data/Clock pin. Used to specify type of time slot before communication begins. After the time slot has been completed this pin is driven low in order to solicit the result of the time slot. RES I Set low (before ENI is driven low) to specify that a reset pulse should be generated on the I/O pin. GND System ground. I1 I Can be connected to the O1/BSY1 of another DS1481. May also be connected to parallel port printer’s BUSY signal. Internally pulled high via a weak resistor. I2 I Can be connected to the O2/BSY2 of another DS1481. Can also be connected to a parallel port printer SELECT OUT signal. Internally pulled high via a weak resistor. ENO O Set to ENI if not the last part on port. Open-drain output with weak internal pullup resistor. I/O I/O 1-Wire I/O line. Bidirect ional line with open-drain output. Not Recommended for New Design
ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -1.0V to +7.0V Operating Temperature Range 0 °C to +70°C Storage Temperature Range -55 °C to +125°C Soldering Temperature See IPC/JEDEC JSTD-020A * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0ºC to 40ºC) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Logic 1 V IH 2.4 V CC + 0.3 V 1 Logic 0 V IL -0.3 +0.8 V 1 Supply V CC 2.7 5.0 5.5 V 1 DC ELECTRICAL CHARACTERISTICS (0ºC to 40ºC; 2.7 ≤ VCC ≤ 5.5) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage I IL -1 +1 μA 5 Output Leakage I LO -1 +1 μA VOL @ ISINK = -2mA 0.4 V I1 Pullup Resistance Z I1 50 kΩ I2 Pullup Resistance Z I2 50 kΩ ENI Pullup Resistance Z ENI 50 kΩ ENO Pullup Resistance Z ENO 50 kΩ D/CLK Pullup Resistance Z DC 50 kΩ RES Pullup Resistance Z R 50 kΩ Active Current I CC 500 μA 2 Available I/O Current I I/O 40 mA 6 Not Recommended for New Design
AC ELECTRICAL CHARACTERISTICS: HOST INTERFACE PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Sample Time (For Bit Time Slot, OD = 0) (For Bit Time Slot, OD = 1) t SIO
8 OD = 0
2 OD = 1
μs Recovery Time t REC 1 μs Data to Enable Hold t DE 40 μs Reset to Enable Hold t RE 40 μs Clock Low Time t CL 200 ns Clock Low to O1, O2 Valid t COV 200 ns BSY1, BSY2 Low Time (For Bit Time Slot, OD = 0) (OD = 1) t BLB 60 μs 3 BSY1, BSY2 Low Time (For Reset Time Slot, OD = 0) (OD = 1) t BLR 960 μs 4 NOTES: 1. All voltages are referenced to ground. 2. Measured with outputs open and I1, I2 high. 3. Minimum time required for 1-wire bit time slot. 4. Minimum time required for 1-wire reset time slot. 5. Only pins without pullups. 6. Overdrive mode only. Not Recommended for New Design