DS1308 MAXIM | Alldatasheet
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Features
S Low Timekeeping Current of 250nA (typ) S Compatible with Crystal ESR Up to 100k ω S RTC Counts Seconds, Minutes, Hours, Date, Month, Day of the Week, and Year with Leap-Year Compensation Up to 2400 S 56-Byte, Battery-Backed, General-Purpose RAM with Unlimited Writes S I2C Serial Interface S External Clock Source for Synchronization Clock Reference (e.g., 32kHz, 50Hz/60Hz Powerline, GPS 1PPS) S Programmable Square-Wave Output Signal S Automatic Power-Fail Detect and Switch Circuitry S -40NC to +85NC Operating Temperature Range S Underwriters Laboratories (UL) Recognized Typical Operating Circuit 19-6353; Rev 0; 5/12 Ordering Information appears at end of data sheet. For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/DS1308.related DS1308 SCL SDA SQW/CLKIN VBAT GND VCC VCC RPURPURPU CPU VCC For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Maxim Integrated Products 2 DS1308 Low-Current I2C RTC with 56-Byte NV RAM (All voltages relative to ground.) ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40NC to +85NC, unless otherwise noted.) (Note 2) DC ELECTRICAL CHARACTERISTICS (VCC = VCCMIN to VCCMAX, VBAT = VBATMIN to VBATMAX, TA = -40NC to +85NC, unless otherwise noted.) (Note 2) FSOP Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four- layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. PACKAGE THERMAL CHARACTERISTICS (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Voltage Range VCC DS1308-18 1.71 1.8 5.5 VDS1308-3 2.7 3.0 5.5 DS1308-33 3.0 3.3 5.5 Battery Voltage VBAT 1.3 5.5 V Logic 1 Input VIH 0.7 x VCC VCC + 0.3 V Logic 0 Input VIL -0.3 0.3 x VCC V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power-Supply Active Current (Note 3) ICCA -3 or -33: fSCL = 400kHz 325 FA Power-Supply Standby Current (Note 4) ICCS -33: VCC = 3.63V 125 FA VCC = VCCMAX 200 Battery Leakage Current IBATLKG VCC R VPF -100 25 +100 nA Input Leakage (SCL) II VIN = 0V to VCC -0.1 +0.1 FA I/O Leakage (SDA, SQW/CLKIN) IIO I2C bus inactive, ECLK = 1 -0.1 +0.1 FA Output Logic 0 (SDA, SQW/ CLKIN), VOL = 0.4V IOL VCC R VCCMIN 3.0 mA VBAT R 1.3V R VCC + 0.2V 250 FA Power-Fail Trip Point VPF -33 2.70 2.82 3.00 V Switchover Voltage VSW VBAT > VPF VPF V VBAT < VPF VBAT > VCC
Maxim Integrated Products 3 DS1308 Low-Current I2C RTC with 56-Byte NV RAM DC ELECTRICAL CHARACTERISTICS (VCC = 0V, VBAT = VBATMIN to VBATMAX, TA = -40NC to +85NC, unless otherwise noted.) (Note 2) AC ELECTRICAL CHARACTERISTICS (VCC = VCCMIN to VCCMAX, TA = -40NC to +85NC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Battery Current, SQW Off (Note 5) IBAT1 VBAT = 3V 250 nA VBAT = VBATMAX 600 Battery Current, SQW On (Note 6) IBAT2 VBAT = 3V 550 nA VBAT = VBATMAX 1100 Data-Retention Current (Note 7) IBATDAT VBAT = 3V 25 100 nA PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency fSCL (Note 8) 0.03 400 kHz Bus Free Time Between a STOP and START Condition tBUF 1.3 Fs Hold Time (Repeated) START Condition tHD:STA (Note 9) 0.6 Fs Low Period of SCL Clock tLOW 1.3 Fs High Period of SCL Clock tHIGH 0.6 Fs Data Hold Time tHD:DAT (Notes 10, 11) 0 0.9 Fs Data Setup Time tSU:DAT (Note 12) 100 ns Setup Time for a Repeated START Condition tSU:STA 0.6 Fs Rise Time of Both SDA and SCL Signals tR (Note 13) 20 + 0.1CB 300 ns Fall Time of Both SDA and SCL Signals tF (Note 13) 20 + 0.1CB 300 ns Setup Time for STOP Condition tSU:STO 0.6 Fs Capacitive Load for each Bus Line CB (Note 13) 400 pF SCL Spike Suppression tSP 60 ns Oscillator Stop Flag (OSF) Delay tOSF (Note 14) 100 ms Timeout Interval tTIMEOUT (Note 15) 25 35 ms
Maxim Integrated Products 4 DS1308 Low-Current I2C RTC with 56-Byte NV RAM POWER-UP/DOWN CHARACTERISTICS (TA = -40NC to +85NC, unless otherwise noted.) (Notes 2, 16) CAPACITANCE (TA = +25NC, unless otherwise noted.) (Note 16) Warning: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data. Note 2: Limits are 100% production tested at T A = +25NC and TA = +85NC. Limits over the operating temperature range and relevant supply voltage are guaranteed by design and characterization. Typical values are not guaranteed. Note 3: SCL clocking at max frequency. VSCL = 0V to VCC. Note 4: Specified with I2C bus inactive. Timekeeping and square-wave functions operational. Note 5: CH = ECLK = SQWE = 0. Note 6: CH = ECLK = 0, SQWE = RS1 = RS0 = 1, I OUT = 0mA. Note 7: CH = 1. ECLK = SQWE = 0. Note 8: The minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if SCL is held low for tTIMEOUT. Note 9: After this period, the first clock pulse is generated. Note 10: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the V IHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 11: The maximum tHD:DAT has only to be met if the device does not stretch the low period (t LOW) of the SCL signal. Note 12: A fast-mode device can be used in a standard-mode system, but the requirement t SU:DAT R to 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t RMAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 13: CB is the total capacitance of one bus line, including all connected devices, in pF. Note 14: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 2.4V P VCC P VCCMAX. Note 15: The DS1308 can detect any single SCL clock held low longer than t TIMEOUTMIN. The device’s I2C interface is in reset state and can receive a new START condition when SCL is held low for at least t TIMEOUTMAX. Once the part detects this condition the SDA output is released. The oscillator must be running for this function to work. Note 16: Guaranteed by design and not 100% production tested. PARAMETER SYMBOL MIN TYP MAX UNITS Recovery at Power-Up tREC 1 2 ms VCC Slew Rate (VPF to 0V) tVCCF 1/50 V/Fs VCC Slew Rate (0V to VPF) tVCCR 1/1 V/Fs PARAMETER SYMBOL MIN TYP MAX UNITS Input Capacitance CI 10 pF I/O Capacitance CO 10 pF
Maxim Integrated Products 6 DS1308 Low-Current I2C RTC with 56-Byte NV RAM Typical Operating Characteristics (VCC = +3.3V, TA = +25NC, unless otherwise specified.) POWER-SUPPLY CURRENT vs. SCL FREQUENCY DS1308 toc05 SCL FREQUENCY (kHz) POWER-SUPPLY CURRENT (µA) 300200100 100 150 200 0 400 TA = +25°C, IOUT = 0mA 5.0V 3.0V SQW/CLKIN OUTPUT-VOLTAGE LOW vs. OUTPUT CURRENT DS1308 toc04 OUTPUT CURRENT (mA) OUTPUT VOLTAGE (V) 321 0.1 0.2 0.3 0.4 TA = +25°C, OUT = ECLK = SQWE = 0 VCC = 3.0V VCC = 5.0V VCC = 1.3V BATTERY CURRENT (SQW ON) vs. BATTERY VOLTAGE DS1308 toc03 BATTERY VOLTAGE (V) BATTERY CURRENT (nA) 4.53.52.5 300 400 500 600 700 800 200 1.5 5.5 RS1 = RS0 = SQWE = 1, IOUT = 0mA +85°C +25°C -40°C BATTERY CURRENT (SQW OFF) vs. BATTERY VOLTAGE DS1308 toc02 BATTERY VOLTAGE (V) BATTERY CURRENT (nA) 4.53.52.5 150 200 250 300 350 400 100 1.5 5.5 SQWE = 0, IOUT = 0mA +85°C +25°C -40°C SUPPLY CURRENT vs. SUPPLY VOLTAGE DS1308 toc01 SUPPLY VOLTAGE (V) SUPPLY CURRENT (µA) 5.04.53.5 4.0 100 110 130 120 140 150 3.0 5.5 SQWE = 1, IOUT = 0mA +85°C +25°C -40°C
Maxim Integrated Products 7 DS1308 Low-Current I2C RTC with 56-Byte NV RAM Pin Configuration Pin Description PIN NAME FUNCTION 1 X1 32.768kHz Crystal Connections. The internal oscillator circuitry is designed for use with a crystal having a specified load capacitance (CL) of 6pF. Note: For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Maxim Real-Time Clocks (RTCs) .2 X2
3 VBAT
Battery Supply Input for Lithium Cell or Other Energy Source. Battery voltage must be held between the minimum and maximum limits for proper operation. Diodes placed in series between the backup source and the VBAT pin can prevent proper operation. If a backup supply is not required, V BAT must be grounded. UL recognized to ensure against reverse charging when used with a lithium cell.
4 GND Ground
5 SDA Serial Data Input/Output for the I2C serial interface. It is an open-drain output and requires an external pullup resistor. The pullup voltage can be up to 5.5V, regardless of the voltage on V CC. 6 SCL Serial Clock Input for the I2C serial interface. Used to synchronize data movement on the serial interface. The pullup voltage can be up to 5.5V, regardless of the voltage on V CC.
7 SQW/CLKIN
Square-Wave Output/Clock Input. This I/O pin is used to output one of four square-wave frequencies (1Hz, 4kHz, 8kHz, 32kHz) or accept an external clock input to drive the RTC counter. In the output mode (ECLK = 0), it is open drain and requires an external pullup resistor. The square-wave operates on VCC, or on VBAT with BBCLK = 1. The pullup voltage can be up to 5.5V, regardless of the voltage on VCC. If not used, this pin may be left unconnected. 8 VCC Primary Power Supply. Decouple the power supply with a 0.1 FF capacitor to ground. µSOP
27 SQW/CLKINX2
18 VCCX1
Maxim Integrated Products 8 DS1308 Low-Current I2C RTC with 56-Byte NV RAM Functional Diagram Detailed Description The DS1308 serial RTC is a low-power, full BCD clock/ calendar plus 56 bytes of NV SRAM. Address and data are transferred serially through an I 2C interface. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. The DS1308 has a built-in power-sense circuit that detects power failures and automatically switches to the VBAT supply. Operation The DS1308 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code, followed by data. Subsequent registers can be accessed sequen - tially until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VBAT is greater than VBAT, the device power is switched from VCC to VBAT when VCC drops below VPF. If V BAT is less than V PF, the device power is switched from V CC to V BAT when V CC drops below V BAT. The oscillator and timekeeping functions are maintained from the VBAT source until V CC returns above V PF, read and write access is allowed after t REC. The Functional Diagram shows the main elements of the DS1308. An enable bit in the seconds register (CH) controls the oscillator. Oscillator startup times are highly dependent upon crystal characteristics, PCB leakage, and layout. High ESR and excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with the recommended characteristics and proper layout usually starts within 1 second. On the first application of power to the device, the time and date registers are reset to 01/01/00 01 00:00:00 (DD/ MM/YY DOW HH:MM:SS), and CH bit in the seconds register is set to 0. DS1308N N /4 /32 EXTSYNC CONTROL LOGIC OSC-1Hz POWER CONTROL RAM CLOCK AND CALENDAR REGISTERS /2 128Hz OSC-1Hz SQW/CLKIN SCL SDA 4.096kHz 8.192kHz 32.768kHz MUX/ BUFFER DIVIDER EXT-1Hz SERIAL BUS INTERFACE AND ADDRESS REGISTER VCC VBAT
during storage and shipping. the crystal oscillator is enabled. the capacitive load for which the crystal was trimmed. Clocks (RTCs) for detailed information. Table 1. Power Control Table 2. Crystal Specifications Clocks (RTCs) for additional specifications. Figure 3. Typical PCB Layout for Crystal SIGNAL LINE AND THE PACKAGE.
time and date is transferred to a second set of registers. a multibyte data transfer, while the clock continues to run. of an update of the main registers during a read. set or initialized by writing the appropriate register bytes. BCD format. Bit 7 of Register 0 is the clock halt (CH) bit. entries result in undefined operation. provided the oscillator is already running. The DS1308 runs in either 12-hour or 24-hour mode. Table 3. RTC and RAM Address Map Note: Bits listed as “0” always read as a 0.
10 Hour Hour Hours
The control register controls the operation of the SQW/CLKIN pin and provides oscillator status. and VCC>VPF. If SQWE = 0, the logic level on the SQW/CLKIN pin is 1 if OUT = 1; it is 0 if OUT = 0. See Table 4. SQW/CLKIN pin is an output, with the square-wave frequency defined by the states of RS1 and RS0. to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a STOP condition. The first time power is applied. The voltage present on VCC and VBAT are insufficient to support oscillation. The CH bit is set to 1, disabling the oscillator. External influences on the crystal (i.e., noise, leakage, etc.). VCC or VBAT applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits. CLKIN frequency is invalid inhibits subsequent detections of the input frequency deviation. ered by VBAT. When set to logic 0, this bit disables the SQW/CLKIN I/O while the part is powered by V BAT. wave has been enabled (SQWE = 1). Table 4 lists the square-wave frequencies that can be selected with the RS bits. Table 4. SQW/CLKIN Pin Functions
communication until the next START condition is sent. the byte of data, and generate a STOP condition. edgment during all byte write operations. bytes, and generates a STOP condition. Figure 7. I2C Transactions
Maxim Integrated Products 15 DS1308 Low-Current I2C RTC with 56-Byte NV RAM impractical, the following method should be used to perform reads from a specified memory location. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the mas - ter generates a START condition, writes the slave address byte (R/ W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/ W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. See Figure 7 for a read example using the repeated START condition to specify the starting memory location. Reading Multiple Bytes From a Slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte it must NACK to indicate the end of the transfer and then it generates a STOP condition. Bus Timeout To avoid an unintended I 2C interface timeout, SCL should not be held low longer than t TIMEOUTMIN. The I2C interface is in the reset state and can receive a new START condition when SCL is held low for at least tTIMEOUTMAX . When the part detects this condition, SDA is released and allowed to float. For the timeout function to work, the oscillator must be enabled and running. Applications Information Power-Supply Decoupling To achieve the best results when using the DS1308, decouple the V CC power supply with a 0.01 FF and/or 0.1FF capacitor. Use a high-quality, ceramic, surface- mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high- frequency response for decoupling applications. Using Open-Drain Outputs The SQW/CLKIN output is open drain and therefore requires an external pullup resistor to realize a logic-high output level. SDA and SCL Pullup Resistors SDA is an open-drain output and requires an external pullup resistor to realize a logic-high output level. Because the DS1308 does not use clock cycle stretch - ing, a master using either an open-drain output with a pullup resistor or CMOS output driver (push-pull) could be used for SCL. Battery Charge Protection The DS1308 contains Maxim’s redundant battery-charge protection circuit to prevent any charging of an external battery. Handling, PCB Layout, and Assembly Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. The lead(Pb)-free/RoHS package can be soldered using a reflow profile that complies with JEDEC J-STD-020. Moisture-sensitive packages are shipped from the fac - tory dry-packed. Handling instructions listed on the pack- age label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device (MSD) classifications. Chip Information PROCESS: CMOS SUBSTRATE CONNECTED TO GROUND
Ordering Information
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. +Denotes a lead(Pb)-free/RoHS-compliant package. *Future product—contact factory for availability. PART TEMP RANGE PIN-PACKAGE DS1308U-18+* -40NC to +85NC 8 FSOP DS1308U-3+* -40NC to +85NC 8 FSOP DS1308U-33+ -40NC to +85NC 8 FSOP PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 µSOP U8+1 21-0036 90-0092
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated, Inc., 160 Rio Robles Drive, San Jose, CA 95134 408-601-1000 16 © 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. DS1308 Low-Current I2C RTC with 56-Byte NV RAM
Revision History
0 5/12 Initial release —