DS1307_06 MAXIM | Alldatasheet
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Technical content
1 of 15 REV: 121906 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS1307 serial real-time clock (RTC) is a low-power, full binary-coded decimal (BCD) clock/calendar plus 56 bytes of NV SRAM. Address and data are tran sferred serially through an I 2C, bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24- hour or 12-hour format with AM/PM indicator. The DS1307 has a built-in power-sense circuit that detects power failures and automatically switches to the backup supply. Timekeeping operation continues while th e part operates from the backup supply.
FEATURES
Real-Time Clock (RTC) Counts Seconds, Minutes, Hours, Date of the Month, Month, Day of the week, and Year with Leap-Year Compensation Valid Up to 2100 56-Byte, Battery-Backed, Nonvolatile (NV) RAM for Data Storage I 2C Serial Interface Programmable Square-Wave Output Signal Automatic Power-Fail Detect and Switch Circuitry Consumes Less than 500nA in Battery- Backup Mode with Oscillator Running Optional Industrial Temperature Range: -40°C to +85°C Available in 8-Pin Plastic DIP or SO Underwriters Laboratory (UL) Recognized Typical Operating Circuit and Pin Configurations appear at end of data sheet.
ORDERING INFORMATION
(V) PIN-PACKAGE TOP MARK* DS1307 0°C to +70°C 5.0 8 PDIP (300 mils) DS1307 DS1307+ 0°C to +70°C 5.0 8 PDIP (300 mils) DS1307 DS1307N -40°C to +85°C 5.0 8 PDIP (300 mils) DS1307N DS1307N+ -40°C to +85°C 5.0 8 PDIP (300 mils) DS1307N DS1307Z 0°C to +70°C 5.0 8 SO (150 mils) DS1307 DS1307Z+ 0°C to +70°C 5.0 8 SO (150 mils) DS1307 DS1307ZN -40°C to +85°C 5.0 8 SO (150 mils) DS1307N DS1307ZN+ -40°C to +85°C 5.0 8 SO (150 mils) DS1307N DS1307Z/T&R 0°C to +70°C 5.0 8 SO (150 mils) Tape and Reel DS1307 DS1307Z+T&R 0°C to +70°C 5.0 8 SO (150 mils) Tape and Reel DS1307 DS1307ZN/T&R -40°C to +85°C 5.0 8 SO (150 mils) Tape and Reel DS1307N DS1307ZN+T&R -40°C to +85°C 5.0 8 SO (150 mils) Tape and Reel DS1307N + Denotes a lead-free/RoHS-compliant device. * A “+” anywhere on the top mark indicates a lead-free device. DS1307 64 x 8, Serial, I2C Real-Time Clock
DS1307 64 x 8, Serial, I2C Real-Time Clock 2 of 15 ABSOLUTE MAXIMUM RATINGS Operating Temperature Range (Noncondensing) Soldering Temperature (surface mount)…..…………………………See JPC/JEDEC Standard J-STD-020 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C, TA = -40°C to +85°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC 4.5 5.0 5.5 V Logic 1 Input V IH 2.2 V CC + 0.3 V Logic 0 Input V IL -0.3 +0.8 V VBAT Battery Voltage V BAT 2.0 3 3.5 V DC ELECTRICAL CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = 0°C to +70°C, TA = -40°C to +85°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage (SCL) I LI -1 1 µA I/O Leakage (SDA, SQW/OUT) I LO -1 1 µA Logic 0 Output (IOL = 5mA) V OL 0.4 V Active Supply Current (fSCL = 100kHz) ICCA 1.5 mA Standby Current I CCS (Note 3) 200 µA VBAT Leakage Current I BATLKG 5 50 nA Power-Fail Voltage (VBAT = 3.0V) V PF 1.216 x VBAT 1.25 x VBAT 1.284 x VBAT V DC ELECTRICAL CHARACTERISTICS (VCC = 0V, VBAT = 3.0V; TA = 0°C to +70°C, TA = -40°C to +85°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VBAT Current (OSC ON); SQW/OUT OFF IBAT1 300 500 nA VBAT Current (OSC ON); SQW/OUT ON (32kHz) IBAT2 480 800 nA VBAT Data-Retention Current (Oscillator Off) IBATDR 10 100 nA WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
DS1307 64 x 8, Serial, I2C Real-Time Clock 3 of 15 AC ELECTRICAL CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = 0°C to +70°C, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency f SCL 0 100 kHz Bus Free Time Between a STOP and START Condition tBUF 4.7 µs Hold Time (Repeated) START Condition tHD:STA (Note 4) 4.0 µs LOW Period of SCL Clock t LOW 4.7 µs HIGH Period of SCL Clock t HIGH 4.0 µs Setup Time for a Repeated START Condition tSU:STA 4.7 µs Data Hold Time t HD:DAT 0 µs Data Setup Time t SU:DAT (Notes 5, 6) 250 ns Rise Time of Both SDA and SCL Signals tR 1000 ns Fall Time of Both SDA and SCL Signals tF 300 ns Setup Time for STOP Condition t SU:STO 4.7 µs CAPACITANCE (TA = +25°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Pin Capacitance (SDA, SCL) C I/O 10 pF Capacitance Load for Each Bus Line CB (Note 7) 400 pF Note 1: All voltages are referenced to ground. Note 2: Limits at -40°C are guaranteed by design and are not production tested. Note 3: ICCS specified with VCC = 5.0V and SDA, SCL = 5.0V. Note 4: After this period, the first clock pulse is generated. Note 5: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 6: The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 7: CB—total capacitance of one bus line in pF.
Figure 1. Block Diagram
DS1307 64 x 8, Serial, I2C Real-Time Clock 5 of 15 TYPICAL OPERATING CHARACTERISTICS (VCC = 5.0V, TA = +25°C, unless otherwise noted.) ICCS vs. VCC 100 110 120 CC (V) SUPPLY CURRENT (uA) VBAT=3.0V IBAT vs. Temperature 175.0 225.0 275.0 325.0 - 4 0 - 2 0 0 2 04 06 08 0 TEMPERATURE (°C) SUPPLY CURRENT (nA) VCC=0V, VBAT=3.0 SQW=32kHz SQW off IBAT vs. VBAT 100 150 200 250 300 350 400 2.0 2.5 3.0 3.5 V BACKUP (V) SUPPLY CURRENT (nA) SQW=32kHz SQW off VCC = 0V SQW/OUT vs. Supply Voltage 32768 32768.1 32768.2 32768.3 32768.4 32768.5 32768.6 32768.7 32768.8 32768.9 32769 FREQUENCY (Hz)
DS1307 64 x 8, Serial, I2C Real-Time Clock 6 of 15 PIN DESCRIPTION PIN NAME FUNCTION 1 X1 2 X2 Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF. X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, X2, is floated if an external oscillator is connected to X1. Note: For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.
3 V BAT
Backup Supply Input for Any Standard 3V Lithium Cell or Other Energy Source. Battery voltage must be held between the minimum and maximum limits for proper operation. Diodes in series between the battery and the VBAT pin may prevent proper operation. If a backup supply is not required, VBAT must be grounded. The nominal power-fail trip point (VPF) voltage at which access to the RTC and user RAM is denied is set by the internal circuitry as 1.25 x VBAT nominal. A lithium battery with 48mAhr or greater will back up the DS1307 for more than 10 years in the absence of power at +25°C. UL recognized to ensure against reverse charging current when used with a lithium battery. Go to: www.maxim-ic.com/qa/info/ul/.
4 GND Ground
5 SDA Serial Data Input/Output. SDA is the data input/output for the I2C serial interface. The SDA pin is open drain and requires an external pullup resistor. 6 SCL Serial Clock Input. SCL is the clock input for the I2C interface and is used to synchronize data movement on the serial interface.
7 SWQ/OUT
Square Wave/Output Driver. When enabled, the SQWE bit set to 1, the SQW/OUT pin outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz, 32kHz). The SQW/OUT pin is open drain and requires an external pullup resistor. SQW/OUT operates with either VCC or VBAT applied.
8 V CC
Primary Power Supply. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the device and VCC is below VTP, read and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. DETAILED DESCRIPTION The DS1307 is a low-power clock/calendar with 56 bytes of battery-backed SRAM. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted fo r months with fewer than 31 days, including corrections for leap year. The DS1307 operates as a slave device on the I 2C bus. Access is obtained by implementing a START condition and providing a device identif ication code followed by a register address. Subsequent registers can be accessed sequentially until a ST OP condition is executed. When V CC falls below 1.25 x V BAT, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous da ta from being written to the device from an out-of- tolerance system. When V CC falls below V BAT, the device switches into a low-current battery-backup mode. Upon power-up, the device switches from battery to V CC when VCC is greater than VBAT +0.2V and recognizes inputs when V CC is greater than 1.25 x V BAT. The block diagram in Fi gure 1 shows the main elements of the serial RTC.
the RTC registers. The time and calendar are set or initialized by writing the a ppropriate register bytes. oscillator is disabled. When cleared to 0, the oscillator is enabled. enable the oscillator (CH bit = 0) during initial configuration. 23 hours). The hours value must be re-entered whenever the 12/24-hour mode bit is changed. to avoid rollover issues, the remaining time and date registers must be written within one second. Table 2. Timekeeper Registers
24 PM/
DS1307 64 x 8, Serial, I2C Real-Time Clock 9 of 15 CONTROL REGISTER The DS1307 control register is used to control the operation of the SQW/OUT pin. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OUT 0 0 SQWE 0 0 RS1 RS0 Bit 7: Output Control (OUT). This bit controls the output level of the SQW/OUT pin when the square- wave output is disabled. If SQWE = 0, the logic level on the SQW/OUT pi n is 1 if OUT = 1 and is 0 if OUT = 0. Bit 4: Square-Wave Enable (SQWE). This bit, when set to logic 1, enables the oscillator output. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits. With the square- wave output set to 1Hz, the clock registers update on the falling edge of the square wave. Bits 1, 0: Rate Select (RS1, RS0). These bits control the frequency of the square-wave output when the square-wave output has been enabled. The following tabl e lists the square-wave frequencies that can be selected with the RS bits. RS1 RS0 SQW/OUT OUTPUT SQWE OUT 0 0 1Hz 1 X 0 1 4.096kHz 1 X 1 0 8.192kHz 1 X 1 1 32.768kHz 1 X X X 0 0 0 X X 1 0 1
DS1307 64 x 8, Serial, I2C Real-Time Clock 10 of 15 I2C DATA BUS The DS1307 supports the I 2C protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1307 operates as a slave on the I2C bus. Figures 3, 4, and 5 detail how data is transferred on the I 2C bus. Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenev er the clock line is HIGH. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line re presents valid data when, af ter a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START c ondition and terminated with a STOP condition. The number of data bytes transfe rred between START and STOP conditions is not limited, and is determined by the master device. The informati on is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the I 2C bus specifications a standard mode (100kHz clock rate) and a fast mode (400kHz clock rate) are de fined. The DS1307 operates in the standard mode (100kHz) only. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must ge nerate an extra clock pulse which is associated with this acknowledge bit. A device that acknowledges must pull down the SD A line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte th at has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
Figure 3. Data Transfer on I2C Serial Bus
- Data transfer from a master tran smitter to a slave receiver. The first byte transmitted by the
bit after each received byte. Data is transferred with the most significant bit (MSB) first.
- Data transfer from a slave tr ansmitter to a master receiver. The first byte (the slave address) is
other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. transferred with the most significant bit (MSB) first.
Figure 6. Data Read (Write Pointer, Then Read)—Slave Receive and Transmit
5 SDA
DS1307 64 x 8, Serial, I2C Real-Time Clock 14 of 15
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
DS1307 64 x 8, Serial, I2C Real-Time Clock 15 of 15 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)