DS1305E/T&R

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Technical content

• Completely Manages All Timekeeping Functions o Real-Time Clock (RTC) Counts Seconds, Minutes, Hours, Date of the Month, Month, Day of the Week, and Year with Leap-Year Compensation Valid Up to 2100 o 96-Byte, Battery-Backed NV RAM for Data Storage o Two Time-Of-Day Alarms, Programmable on Combination of Seconds, Minutes, Hours, and Day of the Week
• Standard Serial Port Interfaces with Most Microcontrollers o Supports SPI (Serial Peripheral Interface) Modes 1 and 3 or Standard 3-Wire Interface o Burst Mode for Reading/Writing Successive Addresses in Clock/RAM
• Multiple Power Supply Pins Ease Adding Battery For Backup o Dual-Power Supply Pins for Primary and Backup Power Supplies o Optional Trickle Charge Output to Backup Supply o 2.0V to 5.5V Operation
• 20-Pin TSSOP Minimizes Required Space
• Optional Industrial Temperature Range: -40°C to +85°C Supports Operation in a Wide Range of Applications
• Underwriters Laboratory (UL®) Recognized PIN CONFIGURATIONS TYPICAL OPERATING CIRCUIT UL is a registered trademark of Underwriters Laboratories Inc. VCC2 1 16 VCC1 VBAT 2 15 PF X1 3 14 VCCIF X2 4 13 SDO N.C. 5 12 SDI INT0 6 11 SCLK INT1 7 10 CE GND 8 9 SERMODE DIP (300 mils) DS1305 VCC2 1 20 VCC1 VBAT 2 19 N.C. X1 3 18 PF N.C. 4 17 VCCIF X2 5 16 SD0 N.C. 6 15 SDI INT0 7 14 SCLK N.C. 8 13 N.C. INT1 9 12 CE GND 10 11 SERMODE DS1305 TSSOP (4.4mm) TOP VIEW 19-5055; Rev 4/15 DS1305 Serial Alarm Real-Time Clock 1 of 22

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE TOP MARK* DS1305 0°C to +70°C 16 DIP (300 mils) DS1305 DS1305N -40°C to +85°C 16 DIP (300 mils) DS1305N DS1305E 0°C to +70°C 20 TSSOP (173 mils) DS1305 DS1305E+ 0°C to +70°C 20 TSSOP (173 mils) DS1305 DS1305E/T&R 0°C to +70°C 20 TSSOP (173 mils) DS1305 DS1305E+T&R 0°C to +70°C 20 TSSOP (173 mils) DS1305 DS1305EN -40°C to +85°C 20 TSSOP (173 mils) DS1305 DS1305EN+ -40°C to +85°C 20 TSSOP (173 mils) DS1305N DS1305EN/T&R -40°C to +85°C 20 TSSOP (173 mils) DS1305 DS1305EN+T&R -40°C to +85°C 20 TSSOP (173 mils) DS1305 +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *An “N” on the top mark denotes an industrial device.

DESCRIPTION

The DS1305 serial alarm real -time clock provides a full binary coded decimal (BCD) clock calendar that is accessed by a simple serial interface. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24- hour or 12 -hour format with AM/PM indicator. In addition, 96 bytes of NV RAM are provided for data storage. The DS1305 will maintain the time and date, provided the oscillator is enabled, as long as at least one supply is at a valid level. An interface logic power-supply input pin (VCCIF) allows the DS1305 to drive SDO and PF pins to a level that is compatible with the interface logic. This allows an easy interface to 3V logic in mixed supply systems. The DS1305 offers dual-power supplies as well as a battery input pin. The dual power supplies support a programmable trickle charge circuit that allows a rechargeable energy source (such as a super cap or rechargeable battery) to be used for a backup supply. The V BAT pin allows the device to be backed up by a non-rechargeable battery. The DS1305 is fully operational from 2.0V to 5.5V. Two programmable time -of-day alarms are provided by the DS1305. Each alarm can generate an interrupt on a programmable combination of seconds, minutes, hours, and day. “Don’t care” states can be inserted into one or more fields if it is desired for them to be ignored for the alarm condition. The time-of- day alarms can be programmed to assert two different interrupt outputs or to assert one common interrupt output. Both interrupt outputs operate when the device is powered by V CC1, VCC2, or VBAT. The DS1305 supports a direct interface to SPI serial data ports or standard 3- wire interface. A straightforward address and data format is implemented in which data transfers can occur 1 byte at a time or in multiple-byte-burst mode. 2 of 22

PIN NAME FUNCTION DIP TSSOP 1 1 VCC2 Backup Power Supply. This is the secondary power supply pin. In systems using the trickle charger, the rechargeable energy source is connected to this pin. 2 2 VBAT Battery Input for Standard +3V Lithium Cell or Other Energy Source. If not used, VBAT must be connect to ground. Diodes must not be placed in series between VBAT and the battery, or improper operation will result. UL recognized to ensure against reverse charging current when used in conjunction with a lithium battery. See “Conditions of Acceptability” at www.maxim-ic.com/TechSupport/QA/ntrl.htm. 3 3 X1 Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator is designed for operation with a crystal having a specified load capacitance of 6pF. For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. The DS1305 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. 4 5 X2 5 4, 6, 8, 13, 19 N.C. No Connection 6 7 INT0 Active-Low Interrupt 0 Output. The INT0 pin is an active-low output of the DS1305 that can be used as an interrupt input to a processor. The INT0 pin can be programmed to be asserted by only Alarm 0 or can be programmed to be asserted by either Alarm 0 or Alarm 1. The INT0 pin remains low as long as the status bit causing the interrupt is present and the corresponding interrupt enable bit is set. The INT0 pin operates when the DS1305 is powered by VCC1, VCC2, or VBAT. The INT0 pin is an open-drain output and requires an external pullup resistor. 7 9 INT1 Active-Low Interrupt 1 Output. The INT1 pin is an active-low output of the DS1305 that can be used as an interrupt input to a processor. The INT1 pin can be programmed to be asserted by Alarm 1 only. The INT1 pin remains low as long as the status bit causing the interrupt is present and the corresponding interrupt enable bit is set. The INT1 pin operates when the DS1305 is powered by V CC1, VCC2, or VBAT. The INT1 pin is an open-drain output and requires an external pullup resistor. Both INT0 and INT1 are open-drain outputs. The two interrupts and the internal clock continue to run regardless of the level of VCC (as long as a power source is present). 8 10 GND Ground 9 11 SERMODE Serial Interface Mode. The SERMODE pin offers the flexibility to choose between two serial interface modes. When connected to GND, standard 3-wire communication is selected. When connected to VCC, SPI communication is selected. 10 12 CE Chip Enable. The chip-enable signal must be asserted high during a read or a write for both 3-wire and SPI communication. This pin has an internal 55kΩ pulldown resistor (typical). 11 14 SCLK Serial Clock Input. SCLK is used to synchronize data movement on the serial interface for either the SPI or 3-wire interface. 3 of 22

the output buffers of the SDO and PF pins. 16 20 VCC1 Primary Power Supply. DC power is provided to the device on this pin. paragraphs describe the function of each pin. Figure 1. BLOCK DIAGRAM

Note 58, “Crystal Considerations with Dallas Real-Time Clocks” for detailed information. Table 1. Crystal Specifications Applications Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. of how they are written. Also note that registers 12h to 1Fh (read) and registers 92h to 9Fh are reserved. on). Illogical time and date entries result in undefined operation. one second after writing the seconds register ensures consistent data. Terminating a write before the last bit is sent aborts the write for that byte.

mode, the user copy is static while the internal registers continue to increment. Figure 2. RTC REGISTERS AND ADDRESS MAP

10 Hour Hours

10 Hour Hour Alarm 01–12 + P/A A

Note: Range for alarm registers does not include mask’m’ bits.

alarm registers is set to a logic 1, alarm occurs every second. the corresponding alarm interrupt enable bit is enabled, an interrupt output is activated. Table 2. TIME-OF-DAY ALARM MASK BITS that control the RTC, interrupts, and trickle charger. be cleared before attempting to write to the device. function when INTCN is set to a logic 0. not initiate the INT0 signal.

(IRQF1) bit in the status register to assert INT1 (when INTCN = 1) or to assert INT0 (when INTCN = 0). When the AIE1 bit is set to logic 0, the IRQF1 bit does not initiate an interrupt signal. cleared when the address pointer goes to any of the Alarm 0 registers during a read or write. cleared when the address pointer goes to any of the Alarm 1 registers during a read or write. Figure 3. PROGRAMMABLE TRICKLE CHARGER

Table 3. TRICKLE CHARGER RESISTOR AND DIODE SELECT accessible when VCC1 is greater than VBAT + 0.2V. VCC2, VCC2 powers the DS1305. The DS1305 does not write-protect itself in this configuration. CC1 and VBAT pins are grounded and the battery is connected to the VCC2 pin. Only these three configurations are allowed. Unused supply pins must be grounded.

Figure 4. POWER-SUPPLY CONFIGURATIONS NOTE: DEVICE DOES NOT PROVIDE AUTOMATIC WRITE PROTECTION. NOTE: DEVICE IS WRITE-PROTECTED IF VCC < VCCTP.

determined by the SERMODE pin. When this pin is connected to V CC, SPI communication is selected. When this pin is connected to ground, standard 3-wire communication is selected. microcontroller being the master. movement between the master (microcontroller) and the slave (DS1305) devices. bit transferred. Address and data bits are transferred in groups of eight, MSB first. Figure 5. SERIAL CLOCK AS A FUNCTION OF MICROCONTROLLER CLOCK NOTE 1: CPHA BIT POLARITY (IF APPLICABLE) MAY NEED TO BE SET ACCORDINGLY. NOTE 2: CPOL IS A BIT THAT IS SET IN THE MICROCONTROLLER’S CONTROL REGISTER. NOTE 3: SDO REMAINS AT HIGH-Z UNTIL 8 BITS OF DATA ARE READY TO BE SHIFTED OUT DURING A READ.

Figure 8. SPI MULTIPLE-BYTE BURST TRANSFER around after reaching 7Fh (FFh for writes).

where each byte is shifted in MSB first. rising edge of SCLK and output on the falling edge of SCLK. Figure 9. 3-WIRE SINGLE-BYTE TRANSFER NOTE: IN BURST MODE, CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST. *I/O IS SDI AND SDO TIED TOGETHER.

This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated i n the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability. OPERATING RANGE RANGE TEMP RANGE VCC (V) Commercial 0°C to +70°C 2.0 to 5.5 VCC1 or VCC2 Industrial -40°C to +85°C 2.0 to 5.5 VCC1 or VCC2 RECOMMENDED DC OPERATING CONDITIONS (Over the operating range, unless otherwise specified.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage VCC1, VCC2 VCC1, VCC2 2.0 5.5 V 7 Logic 1 Input VIH 2.0 VCC + 0.3 V Logic 0 Input VIL VCC = 2.0V -0.3 +0.3 V VCC = 5V +0.8 VBAT Battery Voltage VBAT 2.0 5.5 V VCCIF Supply Voltage VCCIF 2.0 5.5 V 11 15 of 22

DC ELECTRICAL CHARACTERISTICS (Over the operating range, unless otherwise specified.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage ILI -100 +500 µA Output Leakage ILO -1 1 µA Logic 0 Output Logic 1 Output VCC1 Active Supply Current ICC1A VCC1 = 2.0V 0.425 mA 2, 8 VCC1 = 5V 1.28 VCC1 Timekeeping Current (Osc on) ICC1T VCC1 = 2.0V 25.3 μA 1, 8, 12 VCC1 = 5V 81 VCC1 Standby Current (Osc off) ICC1S VCC1 = 2.0V 25 μA 6, 8, 12 VCC1 = 5V 80 VCC2 Active Supply Current ICC2A VCC2 = 2.0V 0.4 mA 2, 9 VCC2 = 5V 1.2 VCC2 Timekeeping Current (Osc on) ICC2T VCC2 = 2.0V 0.3 µA 1, 9, 12 VCC2 = 5V 1 VCC2 Standby Current (Osc off) ICC2S VCC2 = 2.0V 200 nA 6, 9, 12 VCC2 = 5V 200 Battery Timekeeping Current IBAT VBAT = 3V 400 nA 10, 12 Battery Standby Current IBATS VBAT = 3V 200 nA 10, 12 VCC Trip Point VCCTP VBAT - 50 VBAT + 200 mV Trickle Charge Resistors R1 2 kΩ R2 4 R3 8 Trickle Charge Diode Voltage Drop VTD 0.7 V CAPACITANCE (TA = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance CI 10 pF Output Capacitance CO 15 pF 16 of 22

3-WIRE AC ELECTRICAL CHARACTERISTICS (Over the operating range, unless otherwise specified.) (Figure 10 and Figure 11) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Data to CLK Setup tDC VCC = 2.0V 200 ns 3,4 VCC = 5V 50 CLK to Data Hold tCDH VCC = 2.0V 280 ns 3,4 VCC = 5V 70 CLK to Data Delay tCDD VCC = 2.0V 800 ns 3,4,5 VCC = 5V 200 CLK Low Time tCL VCC = 2.0V 1000 ns 4 VCC = 5V 250 CLK High Time tCH VCC = 2.0V 1000 ns 4 VCC = 5V 250 CLK Frequency tCLK VCC = 2.0V 0.6 MHz 4 VCC = 5V DC 2.0 CLK Rise and Fall tR, tF VCC = 2.0V 2000 ns VCC = 5V 500 CE to CLK Setup tCC VCC = 2.0V 4 μs 4 VCC = 5V 1 CLK to CE Hold tCCH VCC = 2.0V 240 ns 4 VCC = 5V 60 CE Inactive Time tCWH VCC = 2.0V 4 μs 4 VCC = 5V 1 CE to Output High-Z tCDZ VCC = 2.0V 280 ns 3,4 VCC = 5V 70 SCLK to Output High-Z tCCZ VCC = 2.0V 280 ns 3,4 VCC = 5V 70 17 of 22

SPI AC ELECTRICAL CHARACTERISTICS (Over the operating range, unless otherwise specified.) (Figure 12 and Figure 13) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Data to CLK Setup tDC VCC = 2.0V 200 ns 5,6 VCC = 5V 50 CLK to Data Hold tCDH VCC = 2.0V 280 ns 5,6 VCC = 5V 70 CLK to Data Delay tCDD VCC = 2.0V 800 ns 5,6,7 VCC = 5V 200 CLK Low Time tCL VCC = 2.0V 1000 ns 6 VCC = 5V 250 CLK High Time tCH VCC = 2.0V 1000 ns 6 VCC = 5V 250 CLK Frequency tCLK VCC = 2.0V 0.6 MHz 6 VCC = 5V DC 2.0 CLK Rise and Fall tR, tF VCC = 2.0V 2000 ns VCC = 5V 500 CE to CLK Setup tCC VCC = 2.0V 4 μs 6 VCC = 5V 1 CLK to CE Hold tCCH VCC = 2.0V 240 ns 6 VCC = 5V 60 CE Inactive Time tCWH VCC = 2.0V 4 μs 6 VCC = 5V 1 CE to Output High-Z tCDZ VCC = 2.0V 280 ns 5,6 VCC = 5V 70 19 of 22

NOTES: 1) ICC1T and ICC2T are specified with CE set to a logic 0 and EOSC bit = 0 (oscillator enabled). 2) ICC1A and I CC2A are specified with CE = V CC, SCLK=2MHz a t V CC = 5V; SCLK = 500kHz at VCC = 2.0V, VIL = 0V, VIH = VCC, and EOSC bit = 0 (oscillator enabled). 3) Measured at VIH = 2.0V or VIL = 0.8V and 10ms maximum rise and fall time. 4) Measured with 50pF load. 5) Measured at VOH = 2.4V or VOL = 0.4V. 6) ICC1S and I CC2S are specified with CE set to a logic 0. The EOSC bit must be set to logic 1 (oscillator disabled). 7) VCC = VCC1, when VCC1 > VCC2 + 0.2V (typical); VCC = VCC2, when VCC2 > VCC1. 8) VCC2 = 0V. 9) VCC1 = 0V. 10) VCC1 < VBAT. 11) VCCIF must be less than or equal to the largest of VCC1, VCC2, and VBAT. 12) Using a crystal on X1 and X2, rated for 6pF load. 21 of 22

REVISION HISTORY

Added Table 1. Crystal Specifications to the Clock Accuracy section. 5 Added “SERMODE = VCC” to Figures 6, 7, 12, and 13. 12, 20 Added “SERMODE = GND” to Figures 9, 10, and 11. 14, 18 Removed the “Crystal Capacitance” parameter from the Capacitance table. 16 4/15 Revised Benefits and Features section 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 1 60 Rio Robles , S an Jose , CA 9 5134 408 -601- 10 00 © 2015 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. 22 of 22