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Technical content
FEATURES
10 years minimum data retention in the absence of external power Data is automatically protected during power loss Directly replaces 2k x 8 volatile static RAM or EEPROM Unlimited write cycles Low-power CMOS JEDEC standard 24-pin DIP package Read and write access times of 100 ns Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time Full ±10% V CC operating range (DS1220AD) Optional ±5% VCC operating range (DS1220AB) Optional industrial temperature range of -40°C to +85°C, designated IND PIN ASSIGNMENT 24-Pin ENCAPSULATED PACKAGE 720-mil EXTENDED PIN DESCRIPTION A0-A10 - Address Inputs DQ0-DQ7 - Data In/Data Out CE - Chip Enable WE - Write Enable OE - Output Enable VCC - Power (+5V) GND - Ground
DESCRIPTION
The DS1220AB and DS1220AD 16k Nonvolatile SRAMs are 16,384-bit, fully static, nonvolatile SRAMs organized as 2048 words by 8 bits. Each NV SRAM has a self -contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and wr ite protection is unconditionally enabled to prevent data corruption. The NV SRAMs can be used in place of existing 2k x 8 SRAMs directly conforming to the popular bytewide 24- pin DIP standard. The devices also match the pinout of the 2716 EPROM and the 2816 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. DS1220AB/AD 16k Nonvolatile SRAM 19-5580; Rev 10/10 www.maxim-ic.com VCC WE 12 13 DQ0 DQ1 GND DQ2 OE A10 CE DQ7 DQ6 DQ5 DQ3 DQ4
The DS1220AB and DS1220AD execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 11 address inputs (A0- A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within t ACC (Access Time) after the last address input signal is stable, providing that the CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later -occurring signal and the limiting parameter is either tCO for CE or tOE for OE rather than address access. WRITE MODE The DS1220AB and DS1220AD execute a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The latter occu rring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles t o avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1220AB provides full functional capability for V CC greater than 4.75 volts and write protects by 4.5V. The DS1220AD provides full functional capability for VCC greater than 4.5 volts and write protects by 4.25V. Data is maintained in the absence of V CC without any additional support circuitry. The nonvolatile static RAMs constantly monitor V CC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As V CC falls below approxima tely 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power -up, when V CC rises above approximately 3.0 volts, the power switching circuit connects external V CC to RAM and disconnects the lithium energy s ource. Normal RAM operation can resume after V CC exceeds 4.75 volts for the DS1220AB and 4.5 volts for the DS1220AD. FRESHNESS SEAL Each DS1220 device is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full ener gy capacity. When V CC is first applied at a level of greater than V TP, the lithium energy source is enabled for battery backup operation.
Voltage on Any Pin Relative to Ground -0.3V to +6.0V Operating Temperature Range Commercial: 0°C to +70°C Industrial: -40°C to +85°C Storage Temperature -40°C to +85°C Lead Temperature (soldering, 10s) +260°C Note: EDIP is wave or hand soldered only. This is a stress rating only and functional operatio n of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliabil ity. RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES DS1220AB Power Supply Voltage VCC 4.75 5.0 5.25 V DS1220AD Power Supply Voltage VCC 4.50 5.0 5.50 V Logic 1 VIH 2.2 VCC V Logic 0 VIL 0.0 +0.8 V DC ELECTRICAL CHARACTERISTICS (TA: See Note 10) (VCC = 5V ± 5% for DS1220AB) (VCC = 5V ± 10% for DS1220AD) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current IIL -1.0 +1.0 µA I/O Leakage Current CE ≥ VIH ≤ VCC IIO -1.0 +1.0 µA Output Current @ 2.4V IOH -1.0 mA Output Current @ 0.4V IOL 2.0 mA Standby Current CE = 2.2V ICCS1 5.0 10.0 mA Standby Current CE = VCC-0.5V ICCS2 3.0 5.0 mA Operating Current (Commercial) ICC01 75 mA Operating Current (Industrial) ICCO1 85 mA Write Protection Voltage (DS1220AB) VTP 4.5 4.62 4.75 V Write Protection Voltage (DS1220AD) VTP 4.25 4.37 4.5 V CAPACITANCE (TA = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance CIN 5 10 pF Input/Output Capacitance CI/O 5 12 pF
AC ELECTRICAL CHARACTERISTICS (TA: See Note 10) (VCC = 5.0V ± 5% for DS1220AB) (VCC = 5.0V ± 10% for DS1220AD) PARAMETER SYMBOL DS1220AB-100 DS1220AD-100 UNITS NOTES MIN MAX Read Cycle Time tRC 100 ns Access Time tACC 100 ns OE to Output Valid tOE 50 ns CE to Output Valid tCO 100 ns OE or CE to Output Active tCOE 5 ns 5 Output High Z from Deselection tOD 35 ns 5 Output Hold from Address Change tOH 5 ns Write Cycle Time tWC 100 ns Write Pulse Width tWP 75 ns 3 Address Setup Time tAW 0 ns Write Recovery Time tWR1 tWR2 10 ns ns Output High from WE tODW 35 ns 5 Output Active from WE tOEW 5 ns 4 Data Setup Time tDS 40 ns 4 Data Hold Time tDH1 tDH2 10 ns ns
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12 WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
POWER-DOWN/POWER-UP CONDITION SEE NOTE 11 POWER-DOWN/POWER-UP TIMING (TA: See Note 10) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES VCC Fail Detect to CE and WE Inactive tPD 1.5 µs 11 VCC slew from VTP to 0V tF 300 µs VCC slew from 0V to VTP tR 300 µs VCC Valid to CE and WE Inactive tPU 2 ms VCC Valid to End of Write Protection tREC 125 ms (TA = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Data Retention Time tDR 10 years 9 WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when dev ice is in the battery backup mode. NOTES: 1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 3. tWP is specified as th e logical AND of CE and WE . tWP is measured from the latter of CE or CE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a high-impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-impedance state during this period.
- If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 9. Each DS1220AB and each DS1220AD has a built -in switch that disconnects the lithium source until VCC is first applied by the user. The expected t DR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. This parameter is guaranteed by design and is not 100% tested. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0°C to 70°C. For indust rial products (IND), this range is - 40°C to +85°C. 11. In a power down condition the voltage on any pin may not exceed the voltage on VCC. 12. tWR1 , tDH1 are measured from WE going high. 13. tWR2 , tDH2 are measured from CE going high. 14. DS1220 modules are recognized by Underwriters Laboratories (UL) under file E99151. DC TEST CONDITIONS Outputs Open Cycle = 200ns for Operating Current All Voltages Are Referenced to Ground AC TEST CONDITIONS Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0 - 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
DS1220AB-100+ 0°C to +70°C 5V ± 5% 24 720 EDIP DS1220AB-100IND+ -40°C to +85°C 5V ± 5% 24 720 EDIP DS1220AD-100+ 0°C to +70°C 5V ± 10% 24 720 EDIP DS1220AD-100IND+ -40°C to +85°C 5V ± 10% 24 720 EDIP +Denotes a lead(Pb)-free/RoHS-compliant package.
PACKAGE INFORMATION
For the latest package outline information and land patterns , go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
24 EDIP MDT24+1 21-0245
REVISION HISTORY
121907 Added package information table; removed the DIP module package
drawing and dimension table 9 Updated the storage and soldering temperature information in the Absolute Maximum Ratings section, removed the unused AC timing specs in the AC Electrical Characteristics table, updated the Ordering Information table, updated the Package Information table 1, 3, 4, 7