DS1217

ADS1217 BURR-BROWN | Alldatasheet

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Technical content

8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER

FEATURES

G 24 BITS NO MISSING CODES G INL: 0.0012% of FSR (max) G FULL-SCALE INPUT: ±2VREF G PGA FROM 1 TO 128 G 22 BITS EFFECTIVE RESOLUTION (PGA = 1), 19 BITS (PGA = 128) G SINGLE CYCLE SETTLING MODE G PROGRAMMABLE DATA OUTPUT RATES UP TO 1kHz G ON-CHIP 1.25V/2.5V REFERENCE G ON-CHIP CALIBRATION G SPI COMPATIBLE G POWER SUPPLY: 2.7V to 5.25V G < 1mW POWER CONSUMPTION, V DD = 3V

DESCRIPTION

The ADS1217 is a precision, wide dynamic range, delta- sigma, Analog-to-Digital (A/D) converter with 24-bit resolu- tion operating from 2.7V to 5.25V supplies. The delta-sigma, A/D converter provides up to 24 bits of no missing code performance and effective resolution of 22 bits. The eight input channels are multiplexed. Internal buffering can be selected to provide a very high input impedance for direct connection to transducers or low-level voltage signals. Burnout current sources are provided that allow for the detection of an open or shorted sensor. An 8-bit Digital-to- Analog Converter (DAC) provides an offset correction with a range of 50% of the FSR (Full-Scale Range). The PGA (Programmable Gain Amplifier) provides selectable gains of 1 to 128 with an effective resolution of 19 bits at a gain of 128. The A/D conversion is accomplished with a 2nd-order, delta-sigma modulator and programmable sinc filter. The reference input is differential and can be used for ratiometric measurements. The onboard current DACs operate indepen- dently with the maximum current set by an external resistor. The serial interface is SPI compatible. Eight bits of digital I/O are also provided that can be used for input or output. The ADS1217 is designed for high-resolution measurement appli- cations in smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation.

APPLICATIONS

G INDUSTRIAL PROCESS CONTROL G LIQUID/GAS CHROMATOGRAPHY G BLOOD ANALYSIS G SMART TRANSMITTERS G PORTABLE INSTRUMENTATION G WEIGH SCALES G PRESSURE TRANSDUCERS BUF PGA+ Voltage Reference Clock Generator Registers Serial Interface 2nd-Order Modulator RAM Digital I/O Interface AGND AV DD R DAC VREFOUT VRCAP VREF+ VREF– XIN XOUT D7BUFEN ... D0DGNDDV DD D IN SCLK POL D OUT CS DRDY PDWN DYSNC RESET MUX AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM IDAC1 ControllerProgram- mable Digital Filter 8-Bit IDAC IDAC2 8-Bit IDAC Offset DAC ADS1217 SBAS260B – MAY 2002 – REVISED OCTOBER 2004 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002-2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.

SBAS260Bwww.ti.com ELECTRICAL CHARACTERISTICS: AV DD = 5V All specifications at –40°C to +85°C, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 150kΩ , fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. A DD + 0.3V NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS (1) ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY ADS1217 TQFP-48 PFB –40 °C to +85°C ADS1217 ADS1217IPFBT Tape and Reel, 250 " """ " ADS1217IPFBR Tape and Reel, 2000 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. PACKAGE/ORDERING INFORMATION (1) ADS1217 PARAMETER CONDITIONS MIN TYP MAX UNITS ANALOG INPUT (AIN0 – AIN7, AINCOM ) Full-Scale Input Voltage (A IN+) – (AIN–) ±2VREF /PGA V Analog Input Voltage Buffer OFF AGND – 0.1 AV DD + 0.1 V Buffer ON AGND + 0.05 AV DD – 1.5 V Differential Input Impedance Buffer OFF 10/PGA M Ω Input Current Buffer ON 0.5 nA Bandwidth Fast Settling Filter –3dB 0.469f DATA Hz Sinc2 Filter –3dB 0.318f DATA Hz Sinc3 Filter –3dB 0.262f DATA Hz Programmable Gain Amplifier User Selectable Gain Ranges 1 128 Burnout Current Sources 2 µA OFFSET DAC Offset DAC Range ±V REF /(PGA) V Offset DAC Monotonicity 8 Bits Offset DAC Gain Error ±1% Offset DAC Gain Error Drift 1 ppm/ °C SYSTEM PERFORMANCE Resolution 24 Bits No Missing Codes Sinc

3 Filter 24 Bits

Integral Nonlinearity End Point Fit, Differential Input, 0.0003 0.0012 % of FSR (1) Buffer Off Offset Error Before Calibration 7.5 ppm of FSR Offset Drift 0.02 ppm of FSR/ °C Gain Error Before Calibration 0.005 % Gain Error Drift 0.5 ppm/ °C Common-Mode Rejection at DC 100 dB f CM = 60Hz, fDATA = 10Hz 130 dB fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB Normal-Mode Rejection f SIG = 50Hz, fDATA = 50Hz 100 dB fSIG = 60Hz, fDATA = 60Hz 100 dB Output Noise See Typical Characteristics Power-Supply Rejection at DC, dB = –20log( ∆VOUT /∆VDD )(2) 80 95 dB NOTES: (1) FSR is Full-Scale Range. (2) ∆VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.

www.ti.com ELECTRICAL CHARACTERISTICS: AV DD = 5V (Cont.) All specifications at –40°C to +85°C, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 150kΩ , fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. ADS1217 PARAMETER CONDITIONS MIN TYP MAX UNITS VOLTAGE REFERENCE INPUT Reference Input (VREF )V REF ≡ (VREF+ ) – (VREF– ) 0.1 2.5 2.6 V Negative Reference Input (VREF– ) AGND – 0.1 (V REF+ ) – 0.1 V Positive Reference Input (VREF+ )( V REF– ) + 0.1 AV DD + 0.1 V Common-Mode Rejection at DC 120 dB Common-Mode Rejection f VREFCM = 60Hz, fDATA = 60Hz 120 dB Bias Current(3) VREF = 2.5V, PGA = 1 1.3 µA ON-CHIP VOLTAGE REFERENCE Output Voltage REF HI = 1 2.4 2.5 2.6 V REF HI = 0 1.25 V Short-Circuit Current Source 8m A Short-Circuit Current Sink 50 µA Drift 15 ppm/ °C Noise V RCAP = 0.1µF, BW = 0.1Hz to 100Hz 10 µVrms Output Impedance Sourcing 100 µA3 Ω Startup Time 5m s IDAC Full-Scale Output Current R DAC = 150kΩ , Range = 1 0.5 mA R DAC = 150kΩ , Range = 2 1 mA R DAC = 150kΩ , Range = 3 2 mA R DAC = 15kΩ , Range = 3 20 mA Current Setting Resistance (RDAC )1 0 k Ω Monotonicity R DAC = 150kΩ 8 Bits Compliance Voltage 0A V DD – 1 V Output Impedance See Typical Characteristics PSRR V OUT = AVDD /2, Code > 16 400 ppm/V Gain Error Individual IDAC 5 % Gain Error Drift Individual IDAC 75 ppm/ °C Gain Error Mismatch Between IDACs, Same Range and Code 0.25 % Gain Error Mismatch Drift Between IDACs, Same Range and Code 15 ppm/ °C POWER-SUPPLY REQUIREMENTS Power-Supply Voltage AV DD 4.75 5.25 V Analog Current (IADC + IVREF + IIDAC) PDWN = 0, or SLEEP 1 nA A/D Converter Current (IADC ) PGA = 1, Buffer OFF 175 275 µA PGA = 128, Buffer OFF 500 750 µA PGA = 1, Buffer ON 250 350 µA PGA = 128, Buffer ON 900 1375 µA VREF Current (IVREF ) 250 375 µA IIDAC Current (IIDAC ) Excludes Load Current 480 675 µA Digital Current Normal Mode, DV DD = 5V 180 275 µA SLEEP Mode, DV DD = 5V 150 µA Read Data Continuous Mode, DVDD = 5V 230 µA PDWN = 0 1 nA Power Dissipation PGA = 1, Buffer OFF, REFEN = 0, 1.8 2.8 mW IDACs OFF, DVDD = 5V NOTES: (1) FSR is Full-Scale Range. (2) ∆VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.

SBAS260Bwww.ti.com ELECTRICAL CHARACTERISTICS: AV DD = 3V All specifications at –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75kΩ , fDATA = 10Hz, and VREF = +1.25V, unless otherwise specified. ADS1217 PARAMETER CONDITIONS MIN TYP MAX UNITS ANALOG INPUT (AIN0 – AIN7, AINCOM ) Full-Scale Input Voltage (AIN+) – (AIN–) ±2VREF /PGA V Analog Input Range Buffer OFF AGND – 0.1 AV DD + 0.1 V Buffer ON AGND + 0.05 AV DD – 1.5 V Input Impedance Buffer OFF 10/ PGA M Ω Input Current Buffer ON 0.5 nA Bandwidth Fast Settling Filter –3dB 0.469f DATA Hz Sinc2 Filter –3dB 0.318f DATA Hz Sinc3 Filter –3dB 0.262f DATA Hz Programmable Gain Amplifier User Selectable Gain Ranges 1 128 Burnout Current Sources 2 µA OFFSET DAC Offset DAC Range ±V REF /(PGA) V Offset DAC Monotonicity 8 Bits Offset DAC Gain Error ±1% Offset DAC Gain Error Drift 2 ppm/ °C SYSTEM PERFORMANCE Resolution 24 Bits No Missing Codes Sinc Integral Nonlinearity End Point Fit, Differential Input, 0.0003 0.0012 % of FSR (1) Buffer Off, T = 25°C Offset Error Before Calibration 15 ppm of FSR Offset Drift 0.04 ppm of FSR/ °C Gain Error Before Calibration 0.010 % Gain Error Drift 1.0 ppm/ °C Common-Mode Rejection at DC 100 dB f CM = 60Hz, fDATA = 10Hz 130 dB fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB Normal-Mode Rejection f SIG = 50Hz, fDATA = 50Hz 100 dB fSIG = 60Hz, fDATA = 60Hz 100 dB Output Noise See Typical Characteristics Power-Supply Rejection at DC, dB = –20 log( ∆VOUT /∆VDD )(2) 75 90 dB VOLTAGE REFERENCE INPUT Reference Input (VREF )V REF ≡ (VREF+ ) – (VREF– ) 0.1 1.25 1.3 V Negative Reference Input (VREF– ) AGND – 0.1 (V REF+ ) – 0.1 V Positive Reference Input (VREF+ )( V REF– ) + 0.1 AV DD + 0.1 V Common-Mode Rejection at DC 120 dB Common-Mode Rejection f VREFCM = 60Hz, fDATA = 60Hz 120 dB Bias Current(3) VREF = 1.25V 0.65 µA ON-CHIP VOLTAGE REFERENCE Output Voltage REF HI = 0 1.2 1.25 1.3 V Short-Circuit Current Source 3m A Short-Circuit Current Sink 50 µA Drift 15 ppm/ °C Noise V RCAP = 0.1µF, BW = 0.1Hz to 100Hz 10 µVrms Output Impedance Sourcing 100 µA3 Ω Startup Time 5m s IDAC Full-Scale Output Current R DAC = 75kΩ , Range = 1 0.5 mA R DAC = 75kΩ , Range = 2 1 mA R DAC = 75kΩ , Range = 3 2 mA R DAC = 15kΩ , Range = 3 20 mA Current Setting Resistance (RDAC )1 0 k Ω Monotonicity R DAC = 75kΩ 8 Bits Compliance Voltage 0A V DD – 1 V Output Impedance See Typical Characteristics PSRR V OUT = AVDD /2, Code > 16 600 ppm/V Gain Error Individual IDAC 5 % Gain Error Drift Individual IDAC 75 ppm/ °C Gain Error Mismatch Between IDACs, Same Range and Code 0.25 % Gain Error Mismatch Drift Between IDACs, Same Range and Code 15 ppm/ °C NOTES: (1) FSR is Full-Scale Range. (2) ∆VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.

www.ti.com POWER-SUPPLY REQUIREMENTS Power-Supply Voltage AV DD 2.7 3.3 V Analog Current (IADC + IVREF + IIDAC ) PDWN = 0, or SLEEP 1 nA A/D Converter Current (IADC ) PGA = 1, Buffer OFF 160 250 µA PGA = 128, Buffer OFF 450 700 µA PGA = 1, Buffer ON 230 325 µA PGA = 128, Buffer ON 850 1325 µA VREF Current (IVREF ) 250 375 µA IIDAC Current (IIDAC ) Excludes Load Current 480 675 µA Digital Current Normal Mode, DV DD = 3V 90 200 µA SLEEP Mode, DV DD = 3V 75 µA Read Data Continuous Mode, DVDD = 3V 113 µA PDWN = 0 1 nA Power Dissipation PGA = 1, Buffer OFF, REFEN = 0, 0.8 1.4 mW IDACs OFF, DVDD = 3V NOTES: (1) FSR is Full-Scale Range. (2) ∆VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency. ADS1217 PARAMETER CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS: AV DD = 3V (Cont.) All specifications at –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75kΩ , fDATA = 10Hz, and VREF = +1.25V, unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNITS INPUT/OUTPUT Logic Level VIH 0.8 × DVDD DV DD V VIL(1) DGND 0.2 × DVDD V VOH IOH = 1mA DV DD – 0.4 V VOL IOL = 1mA DGND DGND + 0.4 V Input Leakage: IIN 0 < VI < DVDD –10 10 µA CLOCK RATES Master Clock Rate: fOSC 1 8 MHz Master Clock Period: tOSC 1/fOSC 125 1000 ns NOTE: (1) Maximum VIL for XIN is DGND + 0.05V. ELECTRICAL CHARACTERISTICS: Digital All specifications at –40°C to +85°C, and DVDD = +2.7V to 5.25V.

SBAS260Bwww.ti.com PIN CONFIGURATION PIN NUMBER NAME DESCRIPTION 1A V DD Analog Power Supply

2 AGND Analog Ground

10 A IN7 Analog Input 7

11 A INCOM Analog Input Common

12 AGND Analog Ground

14 V RCAP VREFOUT Bypass Capacitor

15 IDAC1 Current DAC1 Output

16 IDAC2 Current DAC2 Output

23 BUFEN Buffer Enable Input

24 RESET Active LOW, resets the entire chip. PIN DESCRIPTIONS PIN NUMBER NAME DESCRIPTION RESET BUFEN DGND DGND DGND DGND DGND R DAC IDAC2 IDAC1 V RCAP AV DD D OUT D IN SCLK CS DRDY DV DD DGND DSYNC POL PDWN X OUT XIN AV DD AGND AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM AGND AGND V REFOUT VREF+ VREF – 36 35 34 33 32 31 30 29 28 27 26 123456789 1 0 1 1 ADS1217 Top View TQFP

25 X IN Clock Input

26 X OUT Clock Output, used with crystal or resonator. 27 PDWN Active LOW. Power Down. The power-down function shuts down the analog and digital circuits.

28 POL Serial Clock Polarity Input

29 DSYNC Active LOW, Synchronization Control Input

30 DGND Digital Ground

32 DRDY Active LOW, Data Ready Output

33 CS Active LOW, Chip Select Input

34 SCLK Serial Clock, Schmitt Trigger

IN Serial Data Input, Schmitt Trigger

36 D OUT Serial Data Output

37-44 D0-D7 Digital I/O 0-7

45 AGND Analog Ground

46 V REFOUT Voltage Reference Output

47 V REF+ Positive Differential Reference Input

48 V REF – Negative Differential Reference Input

www.ti.com SPEC DESCRIPTION MIN MAX UNITS t1 SCLK Period 4t OSC Periods

3 DRDY Periods

t2 SCLK Pulse Width, HIGH and LOW 200 ns t3 CS LOW to First SCLK Edge; Setup Time(1) 0n s t4 D IN Valid to SCLK Edge; Setup Time 50 ns t5 Valid DIN to SCLK Edge; Hold Time 50 ns t6 Delay Between Last SCLK Edge for DIN and First SCLK Edge for DOUT : RDATA, RDATAC, RREG, WREG, RRAM, WRAM 50 t OSC Periods CSREG, CSRAMX, CSRAM 200 t OSC Periods CSARAM, CSARAMX 1100 t OSC Periods t7(2) SCLK Edge to Valid New DOUT 50 ns t8(2) SCLK Edge to DOUT , Hold Time 0 ns t9 Last SCLK Edge to DOUT Tri-State 6 10 t OSC Periods NOTE: D OUT goes tri-state immediately when CS goes HIGH. t10 CS LOW Time After Final SCLK Edge 0 ns t11 Final SCLK Edge of One Op Code Until First Edge SCLK of Next Command: RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, t OSC Periods CSRAM, CSARAM, CSREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC 4 t OSC Periods CREG, CRAM 220 t OSC Periods CREGA 1600 t OSC Periods SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 7 DRDY Periods SELFCAL 14 DRDY Periods RESET (Input pin, command, or SCLK pattern) 16 t OSC Periods t12 300 500 t OSC Periods t13 5t OSC Periods t14 550 750 t OSC Periods t15 1050 1250 t OSC Periods t16 Pulse Width 4t OSC Periods t17 Data Not Valid 4 t OSC Periods NOTES: (1) CS may be tied LOW. (2) Load = 20pF. TIMING DIAGRAMS TIMING CHARACTERISTICS MSB (Command or Command and Data) LSB t1t3 CS SCLK (POL = 0) D IN D OUT NOTE: (1) Bit Order = 0. SCLK Reset Waveform MSB (1) LSB (1) t10t2 t2 t11 SCLK (POL = 1) t12 t14 t15 t13 t13 SCLK t17 DRDY t16 RESET, DSYNC, PDWN ADS1217 Resets On Falling Edge

SBAS260Bwww.ti.com TYPICAL CHARACTERISTICS AV DD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ , fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8PGA1 PGA2 PGA16 PGA32 PGA64 PGA128 Decimation Ratio = fMOD fDATA Sinc3 Filter, VREF = 1.25V, BUFFER OFF EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8 PGA1 PGA2 PGA32 PGA128PGA16 PGA64 Decimation Ratio = fMOD fDATA Sinc2 Filter FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) 1500 Decimation Ratio = fMOD fDATA Fast Settling Filter EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO Decimation Ratio = f MOD fDATA 0 500 1000 1500 2000 PGA4 ENOB (rms) PGA2 PGA16 PGA1 PGA8 PGA32 PGA64 PGA128 Sinc3 Filter, BUFFER OFF EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8 PGA1 PGA2 PGA16 PGA32 PGA64 PGA128 Decimation Ratio = fMOD fDATA Sinc3 Filter, BUFFER ON EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO Decimation Ratio 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8 PGA1 PGA2 PGA16 PGA32 PGA64 PGA128 Sinc3 Filter, VREF = 1.25V, BUFFER ON

www.ti.com TYPICAL CHARACTERISTICS (Cont.) AV DD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ , fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. 0.7 0.6 0.5 0.4 0.3 0.2 0.1 NOISE vs INPUT SIGNAL V IN (V) Noise (rms, ppm of FS) 130 120 110 100 COMMON-MODE REJECTION RATIO vs FREQUENCY Frequency of CM Signal (Hz) 1 10 100 1k 10k 100k CMRR (dB) 120 110 100 POWER-SUPPLY REJECTION RATIO vs FREQUENCY Frequency of Power Supply (Hz) 11 0 1 k 100 10k 100k PSRR (dB) 1.00010 1.00006 1.00002 0.99998 0.99994 0.99990 0.99986 GAIN vs TEMPERATURE Temperature (°C) –50 –30 10 –10 30 50 70 90 Gain (Normalized) 140 120 100 –20 –40 OFFSET vs TEMPERATURE Offset (ppm of FS) Temperature (°C) –50 0 50 100 PGA128 PGA16 PGA64 PGA1 INTEGRAL NONLINEARITY vs INPUT SIGNAL V IN (V) INL (ppm of FS) +25°C –40°C +85°C

SBAS260Bwww.ti.com TYPICAL CHARACTERISTICS (Cont.) AV DD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ , fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. 2.55 2.50 2.45 V REFOUT vs LOAD CURRENT VREFOUT Current Load (mA) VREFOUT (V) 200 170 140 110 –10 –40 –70 –100 OFFSET DAC: OFFSET vs TEMPERATURE Offset (ppm of FSR) Temperature (°C) –50 –30 10 –10 30 50 70 90 270 240 210 180 150 CURRENT vs TEMPERATURE Current (µA) IANALOG IDIGITAL Temperature (°C) –60 –30 0 30 60 90 120 400 350 300 250 200 150 100 DIGITAL CURRENT V DD (V) Current (µA) Normal 4.91MHz SLEEP 4.91MHz SLEEP 2.45MHz Normal 2.45MHz 5000 4000 3000 2000 1000 HISTOGRAM OF OUTPUT DATA ppm of FS –2.0 Number of Occurrences 900 800 700 600 500 400 300 200 100 A/D CURRENT vs PGA PGA Setting 18 24 3 2 16 128 64 IADC (µA) AV DD = 5V, Buffer = ON AV DD = 3V, Buffer = ON Buffer = OFF Buffer = OFF

www.ti.com TYPICAL CHARACTERISTICS (Cont.) AV DD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ , fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. 1.00020 1.00016 1.00012 1.00008 1.00004 1.00000 0.99996 0.99992 0.99988 0.99984 0.99980 0.99976 OFFSET DAC: GAIN vs TEMPERATURE Normalized Gain Temperature (°C) –50 –30 10 –10 30 50 70 90 1.0000 1.000 0.999 0.999 0.998 IDAC IOUT vs VOUT VDD – VOUT (V) 012 345 IOUT (Normalized) +85°C –40°C +25°C 1.010 1.005 1.000 0.995 0.990 0.985 IDAC NORMALIZED I OUT vs TEMPERATURE IOUT (Normalized) Temperature (°C) –50 –30 10 –10 30 50 70 90 3000 2000 1000 –1000 –2000 –3000 –4000 –5000 –6000 IDAC MATCHING vs TEMPERATURE IDAC Match (ppm) Temperature (°C) –50 –30 10 –10 30 50 70 90 0.5 0.4 0.3 0.2 0.1 –0.1 –0.2 –0.3 –0.4 –0.5 IDAC DIFFERENTIAL NONLINEARITY (Range = 1, R DAC = 150kΩ , VREF = 2.5V) IDAC Code 0 255 32 64 96 128 160 192 224 DNL (LSB) 0.5 0.4 0.3 0.2 0.1 –0.1 –0.2 –0.3 –0.4 –0.5 IDAC INTEGRAL NONLINEARITY (Range = 1, R DAC = 150kΩ , VREF = 2.5V) IDAC Code 0 255 32 64 96 128 160 192 224 INL (LSB)

sink current to detect open or short circuits on the pins. positive input channel sources approximately 2µA of current. the selected input differential pair. (SBAA090) for more information. ODAC does not reduce the performance of the A/D converter. the SPEED bit in the setup register. FIGURE 1. Input Multiplexer Configuration. An on-chip diode provides temperature sensing capability. 1s, the diode is connected to the input of the A/D converter. connected to ground to complete the circuit. ADS1218 (SBAA073) for more information.

default power-up condition for the digital I/O pins are as inputs. ground, this prevents excess power dissipation. operates in slave only mode. transaction. CS can be tied low. attempted while the register is being updated. FIGURE 4. Filter Frequency Responses.

(for POL = 0). Afterwards, the reset releases automatically. proper operation, the power supply should ramp monotonically. through dedicated instructions. device is referred to as a Register Bank, as shown in Figure 5. that is, the RAM can be used as general-purpose RAM.

128 Bytes

storage of settings for each input. around to bank 0 and Offset 00H . address for that bank of memory. FIGURE 5. Memory Organization.

SBAS260Bwww.ti.com DETAILED REGISTER DEFINITIONS SETUP (Address 00H ) Setup Register Reset Value = iii01110 bit 7-5 Factory Programmed Bits bit 4 SPEED: Modulator Clock Speed 0 : fMOD = fOSC /128 (default) 1 : fMOD = fOSC /256 bit 3 REF EN: Internal Voltage Reference Enable 0 = Internal Voltage Reference Disabled 1 = Internal Voltage Reference Enabled (default) bit 2 REF HI: Internal Reference Voltage Select 0 = Internal Reference Voltage = 1.25V 1 = Internal Reference Voltage = 2.5V (default) bit 1 BUF EN: Buffer Enable 0 = Buffer Disabled 1 = Buffer Enabled (default) bit 0 BIT ORDER: Set Order Bits are Transmitted 0 = Most Significant Bit Transmitted First (default) 1 = Least Significant Bit Transmitted First Data is always shifted into the part most significant bit first. Data is always shifted out of the part most significant byte first. This configuration bit only con- trols the bit order within the byte of data that is shifted out. ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00H SETUP ID ID ID SPEED REF EN REF HI BUF EN BIT ORDER 01H MUX PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0 02H ACR BOCS IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0 PGA2 PGA1 PGA0 03H IDAC1 IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0 04H IDAC2 IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC2_3 IDAC2_2 IDAC2_1 IDAC2_0 05H ODAC SIGN OSET_6 OSET_5 OSET_4 OSET_3 OSET_2 OSET_1 OSET_0 06H DIO DIO_7 DIO_6 DIO_5 DIO_4 DIO_3 DIO_2 DIO_1 DIO_0 07H DIR DIR_7 DIR_6 DIR_5 DIR_4 DIR_3 DIR_2 DIR_1 DIR_0 08H DEC0 DEC07 DEC06 DEC05 DEC04 DEC03 DEC02 DEC01 DEC00 09H M/DEC1 DRDY U/B SMODE1 SMODE0 Reserved DEC10 DEC09 DEC08 0A H OCR0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00 0B H OCR1 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08 0C H OCR2 OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16 0D H FSR0 FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00 0EH FSR1 FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08 0FH FSR2 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16 TABLE II. Registers. REGISTER MAP bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ID ID ID SPEED REF EN REF HI BUF EN BIT ORDER bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0 MUX (Address 01H ) Multiplexer Control Register Reset Value = 01H bit 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel Select 0000 = AIN0 (default) 0001 = AIN1 0010 = AIN2 0011 = AIN3 0100 = AIN4 0101 = AIN5 0110 = AIN6 0111 = AIN7 1xxx = AINCOM (except when all bits are 1s) 1111 = Temperature Sensor Diode bit 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel Select 0000 = AIN0 0001 = AIN1 (default) 0010 = AIN2 0011 = AIN3 0100 = AIN4 0101 = AIN5 0110 = AIN6 0111 = AIN7 1xxx = AINCOM (except when all bits are 1s) 1111 = Temperature Sensor Diode

www.ti.com ACR (Address 02H ) Analog Control Register Reset Value = 00H bit 7 BOCS: Burnout Current Source 0 = Disabled (default) 1 = Enabled IDAC Current = V R DAC CodeREF DAC RANGE 8 2 1 ( )( )− bit 6-5 IDAC2R1: IDAC2R0: Full-Scale Range Select for IDAC2 00 = Off (default) 01 = Range 1 10 = Range 2 11 = Range 3 bit 4-3 IDAC1R1: IDAC1R0: Full-Scale Range Select for IDAC1 00 = Off (default) 01 = Range 1 10 = Range 2 11 = Range 3 bit 2-0 PGA2: PGA1: PGA0: Programmable Gain Amplifier Gain Selection 000 = 1 (default) 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 128 IDAC1 (Address 03 H ) Current DAC 1 Reset Value = 00H The DAC code bits set the output of DAC1 from 0 to full- scale. The value of the full-scale current is set by this Byte, V REF , RDAC , and the DAC1 range bits in the ACR register. IDAC2 (Address 04H ) Current DAC 2 Reset Value = 00H The DAC code bits set the output of DAC2 from 0 to full- scale. The value of the full-scale current is set by this Byte, V REF , RDAC , and the DAC2 range bits in the ACR register. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BOCS IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0 PGA2 PGA1 PGA0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0 ODAC (Address 05H ) Offset DAC Setting Reset Value = 00H bit 7 Offset Sign 0 = Positive 1 = Negative bit 6-0 Offset = V PGA CodeREF •    127 NOTE: The offset must be used after calibration or the calibration will notify the effects. DIO (Address 06H ) Digital I/O Reset Value = 00H A value written to this register will appear on the digital I/O pins if the pin is configured as an output in the DIR register. Reading this register will return the value of the digital I/O pins. DIR (Address 07 H ) Direction control for digital I/O Reset Value = FFH Each bit controls whether the Digital I/O pin is an output (= 0) or input (= 1). The default power-up state is as inputs. DEC0 (Address 08 H ) Decimation Register (Least Significant 8 bits) Reset Value = 80H The decimation value is defined with 11 bits for a range of 20 to 2047. This register is the least significant 8 bits. The 3 most significant bits are contained in the M/DEC1 register. The default data rate is 10Hz with a 2.4576MHz crystal. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DEC07 DEC06 DEC05 DEC04 DEC03 DEC02 DEC01 DEC00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0

SBAS260Bwww.ti.com M/DEC1 (Address 09H ) Mode and Decimation Register Reset Value = 07H bit 7 DRDY: Data Ready (Read Only) This bit duplicates the state of the DRDY pin. bit 6 U/B: Data Format 0 = Bipolar (default) 1 = Unipolar bit 5-4 SMODE1: SMODE0: Settling Mode 00 = Auto (default) 01 = Fast Settling filter 10 = Sinc 2 filter 11 = Sinc3 filter bit 2-0 DEC10: DEC09: DEC08: Most Significant Bits of the Decimation Value OCR0 (Address 0AH ) Offset Calibration Coefficient (Least Significant Byte) Reset Value = 00 H OCR1 (Address 0BH ) Offset Calibration Coefficient (Middle Byte) Reset Value = 00 H U/B ANALOG INPUT DIGITAL OUTPUT +FS 0x7FFFFF

0 Zero 0x000000

–FS 0x800000 +FS 0xFFFFFF

1 Zero 0x000000

–FS 0x000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR15 FSR14 FSR13 FSR12 FSR011 FSR10 FSR09 FSR08 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR23 FSR22 FSR21 FSR20 FSR019 FSR18 FSR17 FSR16 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DRDY U/B SMODE1 SMODE0 Reserved DEC10 DEC09 DEC08 OCR2 (Address 0CH ) Offset Calibration Coefficient (Most Significant Byte) Reset Value = 00 H FSR0 (Address 0DH ) Full-Scale Register (Least Significant Byte) Reset Value = 24 H FSR1 (Address 0EH ) Full-Scale Register (Middle Byte) Reset Value = 90 H FSR2 (Address 0FH ) Full-Scale Register (Most Significant Byte) Reset Value = 67 H

www.ti.com RDATA Read Data Description: Read a single 24-bit ADC conversion result. On completion of read back, DRDY goes HIGH. Operands: None Bytes: 1 Encoding: 0000 0001 Data Transfer Sequence: COMMANDS DESCRIPTION COMMAND BYTE 2ND COMMAND BYTE RDATA Read Data 0000 0001 (01 H ) — RDATAC Read Data Continuously 0000 0011 (03 H ) — STOPC Stop Read Data Continuously 0000 1111 (0F H ) — RREG Read from REG Bank rrrr 0001 rrrr( 1 xH ) xxxx_nnnn (# of reg-1) RRAM Read from RAM Bank aaa 0010 0aaa (2xH ) xnnn_nnnn (# of bytes-1) CREG Copy REGs to RAM Bank aaa 0100 0aaa (4xH ) — CREGA Copy REGS to all RAM Banks 0100 1000 (48 H ) — WREG Write to REG rrrr 0101 rrrr( 5 xH ) xxxx_nnnn (# of reg-1) WRAM Write to RAM Bank aaa 0110 0aaa (6xH ) xnnn_nnnn (# of bytes-1) CRAM Copy RAM Bank aaa to REG 1100 0aaa (Cx H ) — CSRAMX Calc RAM Bank aaa Checksum 1101 0aaa (Dx H ) — CSARAMX Calc all RAM Bank Checksum 1101 1000 (D8 H ) — CSREG Calc REG Checksum 1101 1111 (DF H ) — CSRAM Calc RAM Bank aaa Checksum 1110 0aaa (Ex H ) — CSARAM Calc all RAM Banks Checksum 1110 1000 (E8 H ) — SELFCAL Self Cal Offset and Gain 1111 0000 (F0 H ) — SELFOCAL Self Cal Offset 1111 0001 (F1 H ) — SELFGCAL Self Cal Gain 1111 0010 (F2 H ) — SYSOCAL Sys Cal Offset 1111 0011 (F3 H ) — SYSGCAL Sys Cal Gain 1111 0100 (F4 H ) — WAKEUP Wake Up From Sleep Mode 1111 1011 (FB H ) — DSYNC Sync DRDY 1111 1100 (FC H ) — SLEEP Put in Sleep Mode 1111 1101 (FD H ) — RESET Reset to Power-Up Values 1111 1110 (FE H ) — NOTE: (1) The data received by the A/D converter is always MSB First, the data out format is set by the BIT ORDER bit in ACR reg. TABLE III. Command Summary. RDATAC Read Data Continuous Description: Read Data Continuous mode enables the con- tinuous output of new data on each DRDY . This command eliminates the need to send the Read Data Command on each DRDY . This mode may be terminated by either the STOP Read Continuous command or the RESET command. Operands: None Bytes: 1 Encoding: 0000 0011 Data Transfer Sequence: Command terminated when uuuu uuuu equals STOPC or RESET. NOTE: (1) For wait time, refer to timing specification. D IN

• • • 0000 0011 • • •(1) uuuu uuuu uuuu uuuu uuuu uuuu D OUT D IN uuuu uuuu uuuu uuuu D OUT MSB Mid-Byte uuuu uuuu LSB DRDY
• • •
• • • MSB Mid-Byte LSB COMMAND DEFINITIONS The commands listed below control the operation of the ADS1217. Some of the commands are stand-alone com- mands (e.g., RESET) while others require additional bytes (e.g., WREG requires command, count, and the data bytes). Commands that output data require a minimum of four f OSC cycles before the data is ready (e.g., RDATA). Operands: n = count (0 to 127) r = register (0 to 15) x = don’t care a = RAM bank address (0 to 7) D IN 0000 0001 • • •(1) xxxx xxxx xxxx xxxx xxxx xxxx D OUT MSB Mid-Byte LSB DRDY

SBAS260Bwww.ti.com STOPC Stop Continuous Description: Ends the continuous data output mode. Operands: None Bytes: 1 Encoding: 0000 1111 Data Transfer Sequence: RREG Read from Registers Description: Output the data from up to 16 registers starting with the register address specified as part of the instruction. The number of registers read will be one plus the second byte. If the count exceeds the remaining registers, the addresses will wrap back to the beginning. Operands: r, n Bytes: 2 Encoding: 0001 rrrr xxxx nnnn Data Transfer Sequence: Read Two Registers Starting from Register 01 H (MUX) RRAM Read from RAM Description: Up to 128 bytes can be read from RAM starting at the bank specified in the op code. All reads start at the address for the beginning of the RAM bank. The number of bytes to read will be one plus the value of the second byte. Operands: a, n Bytes: 2 Encoding: 0010 0aaa xnnn nnnn Data Transfer Sequence: Read Two RAM Locations Starting from 20 H CREG Copy Registers to RAM Bank Description: Copy the 16 control registers to the RAM bank specified in the op code. Refer to timing specifications for command execution time. Operands: a Bytes: 1 Encoding: 0100 0aaa Data Transfer Sequence: Copy Register Values to RAM Bank 3 CREGA Copy Registers to All RAM Banks Description: Duplicate the 16 control registers to all the RAM banks. Refer to timing specifications for command execution time. Operands: None Bytes: 1 Encoding: 0100 1000 Data Transfer Sequence: WREG Write to Register Description: Write to the registers starting with the register specified as part of the instruction. The number of registers that will be written is one plus the value of the second byte. Operands: r, n Bytes: 2 Encoding: 0101 rrrr xxxx nnnn Data Transfer Sequence: Write Two Registers Starting from 06 H (DIO) D IN 0000 1111 NOTE: (1) For wait time, refer to timing specification. D IN 0001 0001 0000 0001 xxxx xxxx xxxx xxxx D OUT MUX ACR

• • •(1) D IN 0010 0010 x000 0001 xxxx xxxx xxxx xxxx D OUT RAM Data 20H RAM Data 21H
• • •(1) D IN 0100 0011 D IN 0100 1000 0101 0110 xxxx 0001 Data for DIO Data for DIRD IN

www.ti.com WRAM Write to RAM Description: Write up to 128 RAM locations starting at the beginning of the RAM bank specified as part of the instruction. The number of bytes written is RAM is one plus the value of the second byte. Operands: a, n Bytes: 2 Encoding: 0110 0aaa xnnn nnnn Data Transfer Sequence: Write to Two RAM Locations starting from 10 H CRAM Copy RAM Bank to Registers Description: Copy the selected RAM Bank to the Configura- tion Registers. This will overwrite all of the registers with the data from the RAM bank. Operands: a Bytes: 1 Encoding: 1100 0aaa Data Transfer Sequence: Copy RAM Bank 0 to the Registers CSRAMX Calculate RAM Bank Checksum Description: Calculate the checksum of the selected RAM Bank. The checksum is calculated as a sum of all the bytes with the carry ignored. The ID, DRDY , and DIO bits are masked so they are not included in the checksum. Operands: a Bytes: 1 Encoding: 1101 0aaa Data Transfer Sequence: Calculate Checksum for RAM Bank 3 Calculate the Checksum CSARAMX for all RAM Banks Description: Calculate the checksum of all RAM Banks. The checksum is calculated as a sum of all the bytes with the carry ignored. The ID, DRDY , and DIO bits are masked so they are not included in the checksum. Operands: None Bytes: 1 Encoding: 1101 1000 Data Transfer Sequence: CSRAM Calculate RAM Bank Checksum Description: Calculate the checksum of the selected RAM Bank. The checksum is calculated as a sum of all the bytes with the carry ignored. All bits are included in the checksum calculation, there is no masking of bits. Operands: a Bytes: 1 Encoding: 1110 0aaa Data Transfer Sequence: Calculate Checksum for RAM Bank 2 Calculate the Checksum CSREG of Registers Description: Calculate the checksum of all the registers. The checksum is calculated as a sum of all the bytes with the carry ignored. The ID, DRDY and DIO bits are masked so they are not included in the checksum. Operands: None Bytes: 1 Encoding: 1101 1111 Data Transfer Sequence: 0110 0001 x000 0001 Data for 10H Data for 11H D IN D IN 1100 0000 D IN 1101 0011 • • •(1) xxxx xxxx D OUT Checksum D IN 1101 1000 • • •(1) xxxx xxxx D OUT Checksum D IN 1101 1111 • • •(1) xxxx xxxx D OUT Checksum D IN 1110 0010 • • •(1) xxxx xxxx D OUT Checksum NOTE: (1) For wait time, refer to timing specification.

SBAS260Bwww.ti.com SELFCAL Offset and Gain Self Calibration Description: Starts the process of self calibration. The Offset Control Register (OCR) and the Full-Scale Register (FSR) are updated with new values after this operation. Operands: None Bytes: 1 Encoding: 1111 0000 Data Transfer Sequence: SELFOCAL Offset Self Calibration Description: Starts the process of self-calibration for offset. The Offset Control Register (OCR) is updated after this opera- tion. Operands: None Bytes: 1 Encoding: 1111 0001 Data Transfer Sequence: SELFGCAL Gain Self Calibration Description: Starts the process of self-calibration for gain. The Full-Scale Register (FSR) is updated with new values after this operation. Operands: None Bytes: 1 Encoding: 1111 0010 Data Transfer Sequence: SYSOCAL System Offset Calibration Description: Starts the system offset calibration process. For a system offset calibration the input should be set to 0V differential, and the ADS1217 computes the OCR register value that will compensate for offset errors. The Offset Control Register (OCR) is updated after this operation. Operands: None Bytes: 1 Encoding: 1111 0011 Data Transfer Sequence: SYSGCAL System Gain Calibration Description: Starts the system gain calibration process. For a system gain calibration, the differential input should be set to the reference voltage and the ADS1217 computes the FSR register value that will compensate for gain errors. The FSR is updated after this operation. Operands: None Bytes: 1 Encoding: 1111 0100 Data Transfer Sequence: Calculate Checksum CSARAM for all RAM Banks Description: Calculate the checksum of all RAM Banks. The checksum is calculated as a sum of all the bytes with the carry ignored. All bits are included in the checksum calculation, there is no masking of bits. Operands: None Bytes: 1 Encoding: 1110 1000 Data Transfer Sequence: D IN 1110 1000 • • •(1) xxxx xxxx D OUT Checksum D IN 1111 0000 D IN 1111 0001 D IN 1111 0010 D IN 1111 0011 D IN 1111 0100 NOTE: (1) For wait time, refer to timing specification.

www.ti.com LSB MSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 x rdata x rdatac x x x x x x x x x x x stopc 0001 rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg 0 1 23 45 6 78 9AB C DE F 0010 rram rram rram rram rram rram rram rram x x x x x x x x 0 1 23 45 6 7 0011 x x x x x x x x x x x x x x x x 0100 creg creg creg creg creg creg creg creg crega x x x x x x x 0 1 23 45 6 7 0101 wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg 0 1 23 45 6 78 9AB C DE F 0110 wram wram wram wram wram wram wram wram x x x x x x x x 0 1 23 45 6 7 0111 x x x x x x x x x x x x x x x x 1000 x x x x x x x x x x x x x x x x 1001 x x x x x x x x x x x x x x x x 1010 x x x x x x x x x x x x x x x x 1011 x x x x x x x x x x x x x x x x 1100 cram 0 cram 1 cram 2 cram 3 cram 4 cram 5 cram 6 cram 7 x x x x x x x x 1101 csramx csramx csramx csramx csramx csramx csramx csramx csa x x x x x x 0 1 2 3 4 5 6 7 ramx csreg 1110 cs cs cs cs cs cs cs cs csa x x x x x x x ram 0 ram 1 ram2 ram 3 ram 4 ram 5 ram 6 ram 7 ram 1111 self self self sys sys x x x x x x wakeup dsync sleep reset x cal ocal gcal ocal gcal x = Reserved TABLE IV. Command Map. SLEEP Sleep Mode Description: Puts the ADS1217 into a low power sleep mode. SCLK must be inactive while in sleep mode. To exit this mode, issue the WAKEUP command. Operands: None Bytes: 1 Encoding: 1111 1101 Data Transfer Sequence: WAKEUP Wakeup From Sleep Mode Description: Use this command to wake up from sleep mode. Operands: None Bytes: 1 Encoding: 1111 1011 Data Transfer Sequence: DSYNC Sync DRDY Description: Synchronizes the ADS1217 to the serial clock edge. Operands: None Bytes: 1 Encoding: 1111 1100 Data Transfer Sequence: D IN 1111 1100 D IN 1111 1101 D IN 1111 1011 RESET Reset to Power-Up Values Description: Restore the registers to their power-up values. This command will also stop the Read Continuous mode. It does not affect the contents of RAM. Operands: None Bytes: 1 Encoding: 1111 1110 Data Transfer Sequence: D IN 1111 1110

SBAS260Bwww.ti.com Filter Selection— the ADS1217 uses a (sinx /x) filter or sinc filter. There are three different sinc filters that can be se- lected. A fast settling filter will settle in one tDATA cycle. The sinc2 filter will settle in two cycles and have lower noise. The sinc3 will achieve lowest noise and higher number of effective bits, but requires three cycles to settle. The ADS1217 will operate with any one of these filters, or it can operate in an auto mode, where it will first select the fast settling filter after a new channel is selected and will then switch to sinc 2 for one reading, followed by sinc3 from then on. fDATA — the frequency of the digital output data produced by the ADS1217, fDATA is also referred to as the Data Rate. f f Decimation Ratio f mfactor Decimation RatioDATA MOD OSC=   = • fMOD — the frequency or speed at which the modulator of the ADS1217 is running. This depends on the SPEED bit as shown below: DEFINITION OF TERMS Analog Input Voltage— the voltage at any one analog input relative to AGND. Analog Input Differential Voltage— given by the following equation: (AIN+) – (AIN–). Thus, a positive digital output is produced whenever the analog input differential voltage is positive, while a negative digital output is produced whenever the differential is negative. For example, when the converter is configured with a 2.5V reference and placed in a gain setting of 1, the positive full-scale output is produced when the analog input differen- tial is 2 • 2.5V. The negative full-scale output is produced when the differential is 2 • (–2.5V). In each case, the actual input voltages must remain within the AGND to AV DD range. Conversion Cycle— the term conversion cycle usually refers to a discrete A/D conversion operation, such as that per- formed by a successive approximation converter. As used here, a conversion cycle refers to the t DATA time period. However, each digital output is actually based on the modu- lator results from several t DATA time periods. FILTER SETTING MODULATOR RESULTS Fast Settling 1 t DATA Time Period Sinc2 2 tDATA Time Period Sinc3 3 tDATA Time Period BITS rms BIPOLAR Vrms UNIPOLAR Vrms 24 596nV 298nV 22 2.38 µV1 . 1 9 µV 20 9.54 µV4 . 7 7 µV 18 38.1 µV 19.1 µV 16 153 µV 76.4 µV 14 610 µV 305 µV 12 2.44mV 1.22mV Data Rate— the rate at which conversions are completed. See definition for fDATA . Decimation Ratio— defines the ratio between the output of the modulator and the output Data Rate. Valid values for the Decimation Ratio are from 20 to 2047. Larger Decimation Ratios will have lower noise. Effective Resolution— the effective resolution of the ADS1217 in a particular configuration can be expressed in two different units: bits rms (referenced to output) and Vrms (referenced to input). Computed directly from the converter’s output data, each is a statistical calculation. The conversion from one to the other is shown below. Effective number of bits (ENOB) or effective resolution is commonly used to define the usable resolution of the A/D converter. It is calculated from empirical data taken directly from the device. It is typically determined by applying a fixed known signal source to the analog input and comput- ing the standard deviation of the data sample set. The rms noise defines the ± σ interval about the sample mean. The data from the A/D converter is output as codes, which then can be easily converted to other units, such as ppm or volts. The equations and table below show the relationship between bits or codes, ppm, and volts. ENOB ppm= – log( ) 60 2 SPEED BIT f MOD 0f OSC /128 1f OSC /256 fOSC — the frequency of the crystal input signal at the XIN input of the ADS1217. fSAMP — the frequency, or switching speed, of the input sam- pling capacitor. The value is given by one of the following equations: PGA SETTING SAMPLING FREQUENCY 1, 2, 4, 8 64, 128 f f mfactorSAMP OSC= f f mfactorSAMP OSC= 2 f f mfactorSAMP OSC= 8 f f mfactorSAMP OSC= 16 f f mfactorSAMP OSC= 16 60 2 V PGA REF ENOB     . • 60 2 V PGA REF ENOB     . •

www.ti.com PGA REF 5V SUPPLY ANALOG INPUT (1) GENERAL EQUATIONS DIFFERENTIAL PGA OFFSET FULL-SCALE DIFFERENTIAL PGA SHIFT GAIN SETTING FULL-SCALE RANGE INPUT VOLTAGES (2) RANGE RANGE INPUT VOLTAGES (2) RANGE 1 10V ±5V ±2.5 25 V ±2.5V ±1.25V 42 . 5 V ±1.25V ±0.625V 8 1.25V ±0.625V ±312.5mV 16 0.625V ±312.5mV ±156.25mV 32 312.5mV ±156.25mV ±78.125mV 64 156.25mV ±78.125mV ±39.0625mV 128 78.125mV ±39.0625mV ±19.531mV NOTES: (1) With a 2.5V reference. (2) The ADS1217 allows common-mode voltage as long as the absolute input voltage on AIN+ or AIN– does not go below AGND or above AV DD . TABLE V. Full-Scale Range versus PGA Setting. Full-Scale Range (FSR)— as with most A/D converters, the full-scale range of the ADS1217 is defined as the “input”, which produces the positive full-scale digital output minus the “input”, which produces the negative full-scale digital output. The full-scale range changes with gain setting, see Table V. For example, when the converter is configured with a 2.5V reference and is placed in a gain setting of 2, the full-scale range is: 2 • [1.25V (positive full-scale) minus –1.25V (nega- tive full-scale)] = 5V. Least Significant Bit (LSB) Weight— this is the theoretical amount of voltage that the differential voltage at the analog input would have to change in order to observe a change in the output data of one least significant bit. It is computed as follows: LSB Weight Full Scale Range N= − where N is the number of bits in the digital output. tDATA — the inverse of fDATA , or the period between each data output. PGA REF ±2V PGA REF

ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY ADS1217IPFBR ACTIVE TQFP PFB 48 2000 ADS1217IPFBT ACTIVE TQFP PFB 48 250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. PACKAGE OPTION ADDENDUM www.ti.com 11-Oct-2004

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176/B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 SQ 7,20 6,80 5,50 TYP SQ8,80 9,20 1,05 0,95 1,20 MAX 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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