DS1201

DS1201 MAXIM | Alldatasheet

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SEMICONDUCTOR Electronic Tag FEATURES PIN ASSIGNMENT © User-insertable, nonvolatile 1024 bits of read/write 22nnn” memory © Low-power CMOS circuitry allows for 10 years of data DALLAS retention Ds1204 ELECTRONIC TAG © Miniature and transportable © Durable and rugged © Impervious to handling SIDE © Four million bits/second data rate / 7) PN4 PINS © Single-byte or multiple-byte data transfer capability ~ Z © No restrictions on the number of write cycles owas © Applications include computer identification, system BOTTOM: PIN VIEW access control, secure personnel areas, calibration, PUTT, automatic system setup, and traveling work record. 4.0 IN See Mech. Drawings ‘Seaton PIN DESCRIPTION Pin 1 Vec +5 Volts Pin2 RST RESET Pin3 DQ Data Input/Output Pin4 CLK Clock PinS GND Ground

DESCRIPTION

The DS1201 Electronic Tag Is a miniature nonvolatile, RESET, and DATAINPUT/OUTPUT. Low pin count and read/write memory system which can randomly access __a guided entry for a mating receptacle overcome me- individual 8-bit strings (bytes) or sequentially access the chanical problems normally encountered when a con- entire 1024-bit contents (burst). Interface costto ami- _ ventional integrated circuit package is inserted by the croprocessor is minimized by on-chip circuitry which end user. permits data transfers with only three signals: CLOCK, 030598 1/7

ELECTRONIC TAG BLOCK DIAGRAM Figure 1 oa 24 air SHIFT REGISTER] 128Xxe cu NV. RAM| conget SWITCH Yoo eno —1 ADDRESS/COMMAND Figure 2 765 43210765 45 2107 65 4 3 274 0 B-URST VV V V R-READ eyes ayTe2 eyTE1 WewRITe OPERATION data for a write. The number of CLOCK pulses equals The block diagram (Figure 1) of the Electronic Tag lus- 24 plus 8 for byte mode or 24 plus 1024 for burst mode. trates the main elements of the device: shift register, control logic, nonvolatile RAM, and power switch. Toini- ‘The tag can be usedas a four-pin or five-pin device, de- tiato a memory cycle RESET is taken high and 24 bits. pendingon the application. For hardwired applications, are loaded into the shift register, providing both address __ active powers supplied by the Vcc pin. Alternatively, for and command information. Each bit is input serially on _user-insertable applications, power can be supplied by the rising edge of the CLOCK input. Seven address bits the RESET pin. specify one of the 128 RAM locations. The remaining command bits specify read/write and byte/burst mode. After the first 24 CLOCKs which load the shift register, additional CLOCKs will output data for a read or input (030596 2/7

ADDRESS/COMMAND source for RESET of 2mA @3.8 volts is required. How- Each memory transfer consists of a three-byte input _ever if the Vcc pinis connected to a 5-volt source within called the address/command. The address/command nominal limits, then the RESET pin is not used as a is shown in Figure 2. As defined, the first byte ofthe ad- source of power and input levels revert to normal Vir, dress/command specifies whether the memory willbe and Vy, inputs with a drive current requirement of written into orread. Ifany one of the bits of the first byte 500A. Finally, the RESET signal provides a method of of the address/command fails to meet the exact pattern.__terminatingeither single byte or multiple byte data trans- of read or write, the cycle is abortedandallfuture inputs __fers. A CLOCK cycle is a sequence of falling edge fol- to the tag are ignored until RESET is brought low and _lowed by arising edge. Fordatainputs, the data must be then high again to begin anew cycle. The 8-bit pattern _valid during the rising edge of the CLOCK cycle. Ad- for read is 01100010. The pattern for write is 10011101 dress/command bits and data bits are input on the rising The second byte of the address/command describes edge of the CLOCK and data bits are output on the fall- address inputs AQ in bit 0 through AGin bit 6. Bit7 ofthe —_ing edge of the CLOCK. All data transfer terminates if second byte of the address/command wordmust be set the RESET input is low and D/Q pin goes to a high im- to logic 0. This bit is reserved for future higher density _pedance state. When data transfer to the tag is termi- versions of the tag. If bit 7 does not equal logic 0, the —_natedusing RESET, the transition of RESET must occur cycle Is aborted and all future inputs to the tag are ig- while the clockis at high level to avoid disturbing the last nored until RESET is brought lowandthen highagainto _bit of data. Data transfer is illustrated in Figure 3. begin a new cycle. The third byte of the address/com- mand is also set aside for future expansion. Bits 0 through 6 must be set to logic 0 or the cycle is aborted DATA INPUT | and all future inputs are ignored until RESET is brought Following the 24 CLOCK cycles that input an address/ low and then high again to begin a new cycle. Bit 7 of Command, a data byte is Input on the rising edge of the byte 3 of the address/command is used along with ad- _-"extelght CLOCK cycles, assuming that the read/write dress bits AO through A6 todefine burst mode. When Ad "Nd write/read bits are properly set (for datainput byte 1, through A6 equals logic 0 and bit 7 of byte 3 of the ad- -BItO= 1; bit 1 = 0; bit2= 1; bit3 = 1; bit4 = 1; bit 5=0; dress command equals logic 1, the tag will enter the it 6 = 0; bit 7 = 1). burst mode after the address/command sequence is complete. DATA OUTPUT Following the 24 CLOCK cycles that input the read BURST MODE mode, a data byte is output on the falling edge of the Burst mode is specified for the Electronic Tag when all NeXt8 CLOCK cycles (for data output byte 1, bitO=0; bit address bits (AO-A6) of theaddress/commandaresetto 1 = 1; bit2=0; bit = 0; bit4 = 0; bit = 1; bit6= 1; logic 0 and bit 7 of byte 3 to logic 1. The burst mode _—Dit 7 = 0). causes 128 consecutive bytes to be read or written. Burst mode terminates when the RESET inputis driven Taq CONNECTIONS low. The tagis designed to be plugged into a standard 5-pin, 0.1-inch center SIP receptacle. A key is provided to pre- RESET AND CLOCK CONTROL vent the tag from being plugged in backwards and to aid All data transfers are initiated by driving the RESET in- __‘" alignment of the receptacle. For portable applica- put high. The RESET input serves three functions. First, _ tions, contact to the tag pins can be determined to en- RESET turns onthecontrollogicwhich allows access to Sure connection integrity before data transfer begins. the shift register for the address/command sequence. CLOCK, RESET, and DATA INPUT/OUTPUT all have Second, the RESET signal provides a power source for _internal 40K ohm pulldown resistors to ground which the cycle to follow. To meet this requirement, a drive aN be sensed by a reading device. 020808 977

‘CLK i A CLOCK RESET o 4 6 7 8 8 a [am] ww] wo Tm] 7 To [oo | on | [oo [ov > BURST MODE TRANSFER ou cock RESET o 1 2 8 8 0 2m 0 4 ove 1028 LF F- LeTeoJot ey To[: [ofa] [oo Lox > NOTES: 1. Data input sampled on rising edge of clock cycle. 2. Data output changes on falling edge of clock. READ/WRITE DATA TRANSFER Figure 4 WRITE DATA TRANSFER tow ESET ‘ec ; 7 ta ~+— cLock Y ip rp / toe ‘en tcpy DATA INPUT! 080896 47

RESET ———/ tee. cLock toc tooo <_ DATAINPUT/ v NOTES: 1. All voltages and resistances are referenced to ground 2. Input levels apply to CLK, D/Q, and RST while Veg Is within nominal limits. When Vog is not connected to the tag, then RST input reverts to Vine 3. Measured at Vij = 2.0 or Vj, = 0.8V and 10 ns maximum rise and fall time. 4. Measured at Voy = 2.4 volts and Voy = 0.4 volts. 5. For CLK, D/Q, RST and Voc at 5 volts. 6. Load capacitance = 50 pF. 7. Applies to RST when Voc < 3.8 volts. 8. Measured with outputs open. 9. Measured at Vij of RST greater than or equal to 3.8V when RST supplies power. 10. Logic 1 maximum is Veg + 0.3V if the Voc pin supplies power and RST +0.3V if the RST pin supplies power. 11. RST logic 1 maximum is Veg + 0.3V if the Vee pin supplies power and 5.5V maximum if RST supplies power. 12. Each DS1201 is marked with a 4-digit date code ABB. AA designates the year of manufacture. BB desig- nates the week of manufacture. The expected tpp is defined as starting at the date of manufacture. 13, Average AC RST current can be determined using the following formula: hota = 2 + lLoap pc +(4 X 10°9)(CL + 140)F HrotaL and ILoap are in mA; CL is in pF; fis in MHz. Applying the above formula, a load capacitance of 50 pF running at a frequency of 4.0 MHz gives an IroraL current of 5 mA. 14. When RST is supplying power tcw} must be increased to 100 ms. 030808 5/7

ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -1.0 to +7.0V Operating Temperature 0°C to 70°C Storage Temperature -40°C to +70°C. * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is notimplied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C) [raraweten ———[srweoc] wn [TW WAX | UNS | NOTES | Ee Ec a Ea DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; Voc = 5V + 10%) [raraweren——[srwpoc] wn [TW [wax | uns | nores | a [RSTintfesstncs | Zaer | [|| Komms | 1 [ocinuresree | zoo | | | «| Kom | 1 [cuxirfessince [Zou [vo [| «| Komme [1 [acvecunet | em fmm [seraycuret | tue | || es | mm | [estou | Pm CAPACITANCE (ta = 25°C) [Paraweten ——‘([Swweo]_wN [P| WAX | UNS | NOTES | [rewcwecince | cw | [oupcapctnes | town || | |e | [

AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; Voc = 5V + 10%) Trarawever —————(seweoc[ wN [TP [wax | UNTS | NOTES [baaiocixtews | ew [ [| | [ae [baaiocixoewy | too [|| 7 | me | 9408 [cuctwtne | ta fe fe ES [cucreeny | tex [oe [| «0 | we [ae a feuctorsrras | ew | | | +f =» | se ecco | LT | Retention Time 950858 777 | [