DS100KR401SQE/NOPB

Texas Instruments

Ultra Low Power, 4 Lane (8-channel, bi-directional) Repeater for Data-rates up to 10.3 Gbps

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 DS100KR401UltraLowPower,4Lane(8-channel,bi-directional)RepeaterforData-rates upto10.3Gbps Check forSamples: DS100KR401 1FEATURES DESCRIPTION The DS100KR401 isan extremelylow power, high 2• Comprehensive Product Family: performancerepeaterdesignedtosupport4 lane(bi-– DS100KR800: 8-channel,Uni-directional directional)10G-KR and otherhigh speed interfaceRepeater serialprotocolsup to 10.3 Gbps. The receiver's – DS100KR401: 4x Lane,Bi-directional continuoustime linearequalizer(CTLE) providesa boostof up to +36 dB at 5 GHz (10.3125Gbps) inRepeater each ofitseightchannelsand iscapableofopening– DS100BR210: 2-channel,Uni-directional an inputeye thatiscompletelycloseddue to interRepeater symbol interference(ISI)induced by interconnect – DS100BR111: 1x Lane,Bi-directional medium such as long backplanesor cables,hence Repeater enablinghostcontrollerstoensurean errorfreeend- to-endlink.The transmitterprovidesa de-emphasis• 4 Lane (8-channel,Bi-directional)Repeaterfor boostof up to -12 dB and outputvoltageamplitude4x 10G-KR and Other SerialStandards up to controlfrom 700 mV to 1300 mV to allowmaximum10.3Gbps flexibilityin the physical placement within the• TransparentManagement of10G-KR (802.3ap) interconnectchannel. LinkTrainingProtocol When operatingin10G-KR mode, the DS100KR401• Low 65 mW/channel (Typ)Power transparentlyallowsthe hostcontrollerand the endConsumption, withOption toPower Down pointto optimizethe fulllinkand negotiatetransmitUnused Channels equalizercoefficientsas defined in the 802.3ap

Advanced SignalConditioningFeatures standard.This seamless management of the link trainingprotocolensures guaranteed system level– Receive Equalizationup to36 dB at5 GHz interoperabilitywithminimum latency.– TransmitDe-emphasis up to-12dB With a low power consumptionof 65 mW/channel– TransmitOutput VoltageControl:700 mV to (typ)and optionto turn-offunused channels,the1300 mV DS100KR401 enables energy efficientsystem
Programmable viaPin Selection,EEPROM or design.A singlesupplyof3.3vor 2.5visrequiredto SMBus Interface power thedevice.
SingleSupply OperationSelectable:2.5Vor The programmable settingscan be appliedvia pin3.3V settings,SMBus (I2C) protocolor an external EEPROM. When operatingin the EEPROM mode,• –40°C to+85°C OperatingTemperature Range the configurationinformationisautomaticallyloaded• 3 kV HBM ESD Rating on power up.Thiseliminatestheneed foran external• Flow-thruPinoutin10mm ×5.5mm 54-pin microprocessororsoftwaredriver. LeadlessWQFN Package Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2012,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

INx_n+ INx_n- EQ OUTBUF SMBus VOD/ DeEMPHASIS CONTROLVDD SMBus DEMA/B EQA/B OUTx_n+ OUTx_n- Equalizer CONTROL DS100KR401

10 Gbps KR

SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. TYPICAL APPLICATION BLOCK DIAGRAM -DETAIL VIEW OF CHANNEL (1of8)

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OUT_B_0+ OUT_B_0- OUT_B_1+ LPBK INPUT_EN ALL_DONE DAP = GND OUT_B_1- OUT_B_2+ OUT_B_2- IN_A_3- IN_A_0+ IN_A_0- VDD IN_A_1+ IN_A_1- EQA0 IN_A_2+ IN_A_2- IN_A_3+ OUT_A_1+ OUT_A_1- EQA1 OUT_A_2+ OUT_A_2- OUT_A_3+ OUT_A_3- VIN VDD_SEL IN_B_3+ IN_B_3- VDD MODE OUT_A_0+ OUT_A_0- IN_B_0+ IN_B_0- IN_B_1+ IN_B_1- IN_B_2- IN_B_2+ VDD DEMA1/SCL50 DEMA0/SDA ENSMB OUT_B_3+ OUT_B_3- SMBUS AND CONTROL DEMB1/AD0 DEMB0/AD1 SD_THA / READ_EN EQB1/AD2 EQB0/AD3 RESET VDD VDD Vreg DS100KR401 www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 PIN DIAGRAM Figure1. DS100KR401 Pin Diagram 54 lead Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS100KR401

SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com PIN DESCRIPTIONS (1) Pin Name Pin Number I/O,Type Pin Description DifferentialHigh Speed I/O's OUT_B_0+, OUT_B_0- 1,2, O Invertingand non-inverting50Ω driverbank B outputswithde-emphasis. , 3,4, CompatiblewithAC coupledCML inputs. OUT_B_1+, OUT_B_1- 5,6, , 7,8 OUT_B_2+, OUT_B_2- OUT_B_3+, OUT_B_3- IN_A_0+,IN_A_0-, 10,11, I Invertingand non-invertingdifferentialinputstobank A equalizer.A gatedon- IN_A_1+,IN_A_1-, 12,13, chip50Ω terminationresistorconnectsINA_n+ toVDD and INA_n-toVDD IN_A_2+,IN_A_2-, 15,16, when enabled. IN_A_3+,IN_A_3- 17,18 IN_B_0+,IN_B_0-, 45,44, I Invertingand non-invertingdifferentialinputstobank B equalizer.A gatedon- IN_B_1+,IN_B_1-, 43,42, chip50Ω terminationresistorconnectsINB_n+ toVDD and INB_n-toVDD IN_B_2+,IN_B_2-, 40,39, when enabled. IN_B_3+,IN_B_3- 38,37 OUT_A_0+, OUT_A_0- 35,34, O Invertingand non-inverting50Ω driverbank A outputswithde-emphasis. , 33,32, CompatiblewithAC coupledCML inputs. OUT_A_1+, OUT_A_1- 31,30, , 29,28 OUT_A_2+, OUT_A_2- OUT_A_3+, OUT_A_3- ControlPins — Shared (LVCMOS) ENSMB 48 I,LVCMOS System Management Bus (SMBus) enablepin Tie1kΩ toVDD = RegisterAccess SMBus Slavemode FLOAT = Read ExternalEEPROM (MasterSMBUS Mode) Tie1kΩ toGND = PinMode ENSMB = 1 (SMBUS MODE) SCL 50 I,LVCMOS, ENSMB MasterorSlavemode O, OPEN SMBUS clockinputpinisenabled. Drain Clockoutputwhen loadingEEPROM configuration(mastermode). SDA 49 I,LVCMOS, ENSMB MasterorSlavemode O, OPEN The SMBus bi-directionalSDA pinisenabled.Data inputoropen drain(pull- Drain down only)output. AD0-AD3 54,53,47,46 I,LVCMOS ENSMB MasterorSlavemode SMBus SlaveAddressInputs.InSMBus mode, thesepinsaretheuserset SMBus slaveaddressinputs. READ_EN 26 I,4-LEVEL, When usingan ExternalEEPROM, a transitionfromhightolowstartsthe LVCMOS loadfromtheexternalEEPROM ENSMB = 0 (PINMODE) EQA0, EQA1, 20,19,46,47 I,4-LEVEL, EQA[1:0]and EQB[1:0]controlthelevelofequalizationon theinputpins.The EQB0, EQB1 LVCMOS pinsareactiveonlywhen ENSMB isdeasserted(low).The 8 channelsare organizedintotwo banks.Bank A iscontrolledwiththeEQA[1:0]pinsand bank B iscontrolledwiththeEQB[1:0]pins.When ENSMB ishightheSMBus registersprovideindependentcontrolofeach channel.The EQB[1:0]pinsare convertedtoSMBUS AD2/ AD3 inputs. See Table2 DEMA0, DEMA1, 49,50,53,54 I,4-LEVEL, DEMA[1:0]and DEMB[1:0]controlthelevelofde-emphasisoftheoutput DEMB0, DEMB1 LVCMOS driverwhen inGen1/2 mode. The pinsareonlyactivewhen ENSMB isde- asserted(low).The 8 channelsareorganizedintotwo banks.Bank A is controlledwiththeDEMA [1:0]pinsand bank B iscontrolledwiththe DEMB[1:0]pins.When ENSMB ishightheSMBus registersprovide independentcontrolofeach channel.The DEMA[1:0]pinsareconvertedto SMBUS SCL/SDA and DEMB[1:0]pinsareconvertedtoAD0, AD1 inputs. See Table3 (1) Notes: LVCMOS inputswithoutthe“Float”conditionsmust be driventoa logicloworhighatalltimesoroperationisnotguaranteed. Inputedge rateforLVCMOS/FLOAT inputsmust be fasterthan50 ns from10–90%. For3.3Vmode operation,VIN pin= 3.3Vand the"VDD "forthe4-levelinputis3.3V. For2.5Vmode operation,VDD pin= 2.5Vand the"VDD "forthe4-levelinputis2.5V.

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 PIN DESCRIPTIONS (1)(continued) Pin Name Pin Number I/O,Type Pin Description MODE 21 I,4-LEVEL, Tie1kΩ toVDD = 10G-KR Mode Operation LVCMOS Tie1kΩ toGND = 10G Mode Operation SD_TH 26 I,4-LEVEL, ControlstheinternalSignalDetectThreshold LVCMOS See Table4 ControlPins — Both Pin and SMBus Modes (LVCMOS) INPUT_EN 22 I,4-LEVEL, Tie1kΩ toVDD = Normal Operation LVCMOS LPBK 23 I,4-LEVEL, Controlstheloopbackfunction LVCMOS Tie1kΩ toGND = INA_n toOUTB_n loopback Float= Normal Operation(loopbackisdisabled) Tie1kΩ toVDD = INB_n toOUTA_n loopback VDD_SEL 25 I,FLOAT Controlstheinternalregulator Float= 2.5Vmode TieGND = 3.3Vmode RESET 52 I,LVCMOS LOW = Deviceisenabled(NormalOperation) HIGH = Low Power Mode Outputs ALL_DONE 27 O, LVCMOS ValidRegisterLoad StatusOutput HIGH = ExternalEEPROM loadfailed LOW = ExternalEEPROM loadpassed Power VIN 24 Power In3.3Vmode, feed3.3VtoVIN In2.5Vmode, leavefloating. VDD 9,14,36,41,51 Power Power supplypinsCML/analog 2.5Vmode, connectto2.5V 3.3Vmode, connect0.1uF cap toeach VDD pin GND DAP Power Ground pad (DAP -dieattachpad). ABSOLUTE MAXIMUM RATINGS (1)(2) SupplyVoltage(VDD = 2.5Vmode) -0.5Vto+2.75V SupplyVoltage(VIN= 3.3Vmode) -0.5Vto+4.0V LVCMOS Input/OutputVoltage -0.5Vto+4.0V CML InputVoltage -0.5Vto(VDD+0.5) CML InputCurrent -30to+30 mA JunctionTemperature 125°C StorageTemperature -40°C to+125°C Lead TemperatureRange Soldering(4sec.) +260°C DerateNJY0054A Package 52.6mW/°C above +25°C ESD Rating HBM, STD -JESD22-A114F 5 kV MM, STD -JESD22-A115-A 150 V CDM, STD -JESD22-C101-D 1000 V ThermalResistance θJC 11.5°C/W θJA,No Airflow,4 layerJEDEC 19.1°C/W Forsolderingspecifications:see productfolderatwww.ti.com,and SNOA549 (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions.Absolute Maximum Numbers arespecifiedfora junctiontemperaturerangeof-40°C to+125°C. Models arevalidatedtoMaximum Operating Voltagesonly. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS100KR401

SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS Min Typ Max Units SupplyVoltage(2.5Vmode) 2.375 2.5 2.625 V SupplyVoltage(3.3Vmode) 3.0 3.3 3.6 V AmbientTemperature -40 25 +85 °C SMBus (SDA, SCL) 3.6 V SupplyNoiseup to50 MHz (1) 100 mVp-p (1) Allowedsupplynoise(mVp-p sinewave) undertypicalconditions. ELECTRICAL CHARACTERISTICS (1) Symbol Parameter Conditions Min Typ (2) Max Units Power PD Power Dissipation VDD = 2.5V supply,EQ Enabled, 500 700 mWVOD = 1.0Vp-p,INPUT_EN = 1,RESET = 0 VIN = 3.3V supply,EQ Enabled, 660 900 mWVOD = 1.0Vp-p,INPUT_EN = 1,RESET = 0 LVCMOS /LVTTL DC Specifications Vih HighLevelInputVoltage 3.3VMode Operation(VIN= 3.3V) 2.0 3.6 V Vil Low LevelInputVoltage 0 0.8 V Voh HighLevelOutputVoltage Ioh = −4mA 2.0 V(ALL_DONE pin) Vol Low LevelOutputVoltage Iol= 4mA 0.4 V(ALL_DONE pin) Iih InputHighCurrent(RESET pin) VIN = 3.6V, -15 +15 uA LVCMOS = 3.6VInputHighCurrentwithinternal +20 +150 uA resistors(4–levelinputpin) Iil InputLow Current(RESET pin) VIN = 3.6V,LVCMOS = 0 V -15 +15 uA InputLow Currentwithinternal -160 -40 uA resistors(4–levelinputpin) CML ReceiverInputs(IN_n+,IN_n-) RL rx-diff RX package pinsplusSi 0.05GHz -7.5GHz -15 dB differentialreturnloss 7.5GHz -15 GHz -5 dB RLrx-cm Common mode RX returnloss 0.05GHz -5 GHz -10 dB Zrx-dc RX DC common mode impedance TestedatVDD = 0 40 50 60 Ω Zrx-diff-dc RX DC differntialmode impedance TestedatVDD = 0 80 100 120 Ω Vrx-diff-dc DifferentialRX peak topeak Testedatpins 0.6 1.2 Vvoltage Vrx-signal-det-SignaldetectassertlevelforactiveSD_TH = F (float),0101 patternat10.3Gbps 180 mVp-p diff-pp datasignal Vrx-idle-det- Signaldetectde-assertlevelfor SD_TH = F (float),0101 patternat10.3Gbps 110 mVp-p diff-pp electricalidle High Speed Outputs Vtx-diff-pp OutputVoltageDifferentialSwing Differentialmeasurement withOut_n+ and OUT_n-, terminatedby 50Ω toGND, 0.8 1.0 1.2 Vp-pAC-Coupled,VID = 1.0Vp-p,DEM0 = 1, DEM1 = 0 Vtx-de-ratio_3.5 TXde-emphasisratio VOD = 1.0Vp-p,DEM0 = 0,DEM1 = R −3.5 dB Vtx-de-ratio_6 TX de-emphasisratio VOD = 1.0Vp-p,DEM0 = R, DEM1= R −6 dB TTX-HF-DJ-DD TX Dj> 1.5MHz 0.15 UI TTX-HF-DJ-DD TX RMS jitter< 1.5MHz 3.0 ps RMS (1) The ElectricalCharacteristicstableslistspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwise modifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand areNOT guaranteed. (2) Typicalvaluesrepresentmost likelyparametricnorms atVDD = 2.5V,TA = 25°C.,and attheRecommended OperationConditionsat thetimeofproductcharacterizationand areNOT guaranteed.

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS (1)(continued) Symbol Parameter Conditions Min Typ (2) Max Units TTX-RISE-FALL Transmitterrise/falltime 20% to80% ofdifferentialoutputvoltage 35 45 ps TRF-MISMATCH Transmitterrise/fallmismatch 20% to80% ofdifferentialoutputvoltage 0.01 0.1 UI RL TX-DIFF Differentialreturnloss 0.05GHz -7.5GHz -15 dB 7.5GHz -15 GHz -5 dB RL TX-CM Common mode returnloss 0.05GHz -5 GHz -10 dB ZTX-DIFF-DC DC differentialTX impedance 100 Ω VTX-CM-AC-PP TX AC common mode voltage VOD = 1.0Vp-p,DEM0 = 1,DEM1 = 0 100 mVpp ITX-SHORT Transmittershortcircuitcurrent Totalcurrentthetransmittercan supplywhen 20 mAlimit shortedtoVDD orGND TPDEQ Differentialpropagationdelay EQ = 00,(3) 200 ps TLSK Lane tolaneskew T = 25C, VDD = 2.5V 25 ps TPPSK Parttopartpropagationdelay T = 25C, VDD = 2.5V 40 psskew Equalization DJE1 Residualdeterministicjitterat 35”4 milFR4, VID = 0.8Vp-p,PRBS15, 0.3 UI10.3Gbps EQ = 1F'h,DEM = 0 dB DJE2 Residualdeterministicjitterat 10 meters30 awg cable,VID = 0.8Vp-p, 0.3 UI10.3Gbps PRBS15, EQ = 2F'h,DEM = 0 dB De-emphasis DJD1 Residualdeterministicjitterat 20”4milsFR4, VID = 0.8Vp-p,PRBS15, 0.1 UI10.3Gbps EQ = 00,VOD = 1.0Vp-p,DEM = −9 dB (3) PropagationDelaymeasurements willchange slightlybased on thelevelofEQ selected.EQ = 00 willresultintheshortestpropagation delays. ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ Max Units SERIAL BUS INTERFACE DC SPECIFICATIONS VIL Data,ClockInputLow Voltage 0.8 V VIH Data,ClockInputHighVoltage 2.1 3.6 V IPULLUP CurrentThroughPull-UpResistor HighPower Specification 4 mAorCurrentSource VDD NominalBus Voltage 2.375 3.6 V ILEAK-Bus InputLeakage Per Bus Segment See (1) -200 +200 µA ILEAK-Pin InputLeakage Per DevicePin -15 µA C I CapacitanceforSDA and SCL See (1)(2) 10 pF R TERM ExternalTerminationResistance PullupVDD = 3.3V,See (1)(2)(3) 2000 Ω pulltoVDD = 2.5V± 5% PullupVDD = 2.5V,See (1)(2)(3) 1000 ΩOR 3.3V± 10% SERIAL BUS INTERFACE TIMING SPECIFICATIONS FSMB Bus OperatingFrequency ENSMB = VDD (SlaveMode) 400 kHz ENSMB = FLOAT (MasterMode) 280 400 520 kHz TBUF Bus FreeTime Between Stopand 1.3 µsStartCondition THD:STA Holdtimeafter(Repeated)Start AtIPULLUP ,Max Condition.Afterthisperiod,the 0.6 µs firstclockisgenerated. TSU:STA Repeated StartConditionSetup 0.6 µsTime (1) Recommended value. (2) Recommended maximum capacitanceloadperbus segment is400pF. (3) Maximum terminationvoltageshouldbe identicaltothedevicesupplyvoltage. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS100KR401

tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA ST SP tSU:STO SCL SDA ST IN 0V tPLHD OUT 0V tPHLD VOD (p-p) = (OUT+) ± (OUT-) (OUT-) (OUT+) 20% 80% 20% 80% tFALLtRISE DS100KR401 SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE (continued) Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ Max Units TSU:STO StopConditionSetupTime 0.6 µs THD:DAT Data HoldTime 0 ns TSU:DAT Data SetupTime 100 ns TLOW ClockLow Period 1.3 µs THIGH ClockHighPeriod See (4) 0.6 50 µs tF Clock/DataFallTime See (4) 300 ns tR Clock/DataRiseTime See (4) 300 ns tPOR Time inwhicha devicemust be See (4)(5) 500 msoperationalafterpower-onreset SMBus common AC specificationsfordetails. (5) Specifiedby Design.Parameternottestedinproduction. TIMING DIAGRAMS Figure2. CML Output and Rise and FALL TransitionTime Figure3. PropagationDelay Timing Diagram Figure4. SMBus Timing Parameters

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 FUNCTIONAL DESCRIPTIONS The DS100KR401 isa lowpower media compensation4 lanerepeateroptimizedfor10G –KR. The DS100KR401 compensates forlossyFR-4 printedcircuitboard backplanesand balancedcables.The DS100KR401 operates in 3 modes: Pin ControlMode (ENSMB = 0),SMBus Slave Mode (ENSMB = 1) and SMBus Master Mode (ENSMB = float)toloadregisterinformationsfromexternalEEPROM; pleaserefertoSMBUS MasterMode for additionalinformation. PinControlMode: When inpinmode (ENSMB = 0),therepeaterisconfigurablewithexternalpins.Equalizationand de-emphasis can be selectedvia pin foreach side independently.When de-emphasisis assertedVOD is automatically adjustedpertheDe-Emphasis tablebelow.The receiverelectricalidledetectthresholdisalsoadjustableviathe SD_TH pin. SMBUS Mode: When inSMBus mode (ENSMB = 1),theVOD (outputamplitude),equalization,de-emphasis,and termination disablefeaturesareallprogrammableon a individuallanebasis,insteadofgroupedby A orB as inthepinmode case.Upon assertionofENSMB theMODE, EQx and DEMx functionsreverttoregistercontrolimmediately.The EQx and DEMx pinsare convertedtoAD0-AD3 SMBus addressinputs.The otherexternalcontrolpinsremain activeunlesstheirrespectiveregistersare writtentoand theappropriateoverridebitisset,inwhich case they areignoreduntilENSMB isdrivenlow (pinmode).On power-upand when ENSMB isdrivenlow allregistersare resettotheirdefaultstate.IfRESET isassertedwhileENSMB ishigh,theregistersretaintheircurrentstate. Equalizationsettingsaccessibleviathe pincontrolswere chosen to meet the needs of most applications.If additionalfinetuningor adjustmentisneeded,additionalequalizationsettingscan be accessed viatheSMBus registers.Each inputhas a totalof256 possibleequalizationsettings.The tablesshow the16 settingwhen the deviceisinpinmode. When usingSMBus mode, the equalization,VOD and de-Emphasis levelsare setby registers. The inputcontrolpinshave been enhanced to have 4 differentlevelsand providea widerrange of control settingswhen ENSMB=0. Table1. 4–LevelControlPin Settings(1) Pin Setting Description VoltageatPin 0 Tie1kΩ toGND 0.03x VDD R Tie20kΩ toGND 1/3x VDD Float Float(leavepinopen) 2/3x VDD 1 Tie1kΩ toVDD 0.98x VDD (1) The above requiredresistorvalueisfora singledevice.When therearemultipledevicesconnectedtothepull-up/pull-downresistor, thevaluemust scalewiththenumber ofdevices.If4 devicesareconnectedtoa singlepull-uporpull-down,the1kΩ resistorvalue shouldbe 250Ω.Forthe20kΩ toGND, thisshouldalsoscaleto5kΩ. 3.3Vor 2.5VSupply Mode Operation The DS100KR401 has an optionalinternalvoltageregulatorto providethe 2.5V supplyto the device.In 3.3V mode, the VIN pin= 3.3V isused to supplypower to the deviceand the VDD pinsshouldbe leftopen. The internalregulatorwillprovidethe2.5V totheVDD pinsofthedeviceand a 0.1µF cap isneeded ateach of5 VDD pinsforpower supplyde-coupling(totalcapacitanceshouldbe ≤0.5µF).The VDD_SEL pinmust be tiedto GND toenabletheinternalregulator.In2.5V mode, theVIN pinshouldbe leftopen and 2.5V supplymust be appliedtotheVDD pins.The VDD_SEL pinmust be leftopen (noconnect)todisabletheinternalregulator. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS100KR401

VDD_SEL VIN VDD VDD VDD VDD VDD 3.3V 0.1 uF 0.1 uF 0.1 uF 0.1 uF 0.1 uF Internal voltage regulator Enable 2.5V VDD_SEL VIN VDD VDD VDD VDD VDD Internal voltage regulator Disable Place 0.1 uF close to VDD Pin Total capacitance should be 7 0.5 uF 1 uF 10 uF 2.5V1 uF 10 uF 0.1 uF 0.1 uF 0.1 uF 0.1 uF 0.1 uF Place capcitors close to VDD Pin open openCapacitors can be either tantalum or an ultra-low ESR seramic. 3.3V mode 2.5V mode Capacitors can be either tantalum or an ultra-low ESR seramic. DS100KR401 SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com Figure5. 3.3Vor 2.5VSupply Connection Diagram Table2.EqualizerSettings EQA1 EQA0 dB at dB at dB atLevel EQ – 8 bits[7:0] Suggested UseEQB1 EQB0 1.0GHz 3.0GHz 5.0GHz 1 0 0 0000 0000 = 0x00 1.7 4.2 5.3 FR4 < 5 inchtrace 2 0 R 0000 0001 = 0x01 2.8 6.6 8.7 FR4 5 inch5–miltrace 3 0 Float 0000 0010 = 0x02 4.1 8.6 10.6 FR4 5 inch4–miltrace 4 0 1 0000 0011 = 0x03 5.1 9.8 11.7 FR4 10 inch5–miltrace 5 R 0 0000 0111 = 0x07 6.2 12.4 15.6 FR4 10 inch4–miltrace 6 R R 0001 0101 = 0x15 5.1 12.0 16.6 FR4 15 inch4–miltrace 7 R Float 0000 1011 = 0x0B 7.7 15.0 18.3 FR4 20 inch4–miltrace 8 R 1 0000 1111 = 0x0F 8.8 16.5 19.7 FR4 25 to30 inch4–miltrace 9 Float 0 0101 0101 = 0x55 6.3 14.8 20.3 FR4 30 inch4–miltrace 10 Float R 0001 1111 = 0x1F 9.9 19.2 23.6 FR4 35 inch4–miltrace 11 Float Float 0010 1111 = 0x2F 11.3 21.7 25.8 10m, 30awg cable 12 Float 1 0011 1111 = 0x3F 12.4 23.2 27.0 10m – 12m cable 13 1 0 1010 1010 = 0xAA 11.9 24.1 29.1 14 1 R 0111 1111 = 0x7F 13.6 26.0 30.7 15 1 Float 1011 1111 = 0xBF 15.1 28.3 32.7 16 1 1 1111 1111 = 0xFF 16.1 29.7 33.8

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 Table3. De-emphasis and Output VoltageSettings DEMA1 DEMA0 InnerAmplitudeLevel VOD Vp-p DEM dB Suggested UseDEMB1 DEMB0 Vp-p 1 0 0 0.8 0 0.8 FR4 <5 inch4–miltrace 2 0 R 0.9 0 0.9 FR4 <5 inch4–miltrace 3 0 Float 0.9 -3.5 0.6 FR4 10 inch4–miltrace 4 0 1 1.0 0 1.0 FR4 <5 inch4–miltrace 5 R 0 1.0 -3.5 0.7 FR4 10 inch4–miltrace 6 R R 1.0 -6 0.5 FR4 15 inch4–miltrace 7 R Float 1.1 0 1.1 FR4 <5 inch4–miltrace 8 R 1 1.1 -3.5 0.7 FR4 10 inch4–miltrace 9 Float 0 1.1 -6 0.6 FR4 15 inch4–miltrace 10 Float R 1.2 0 1.2 FR4 <5 inch4–miltrace 11 Float Float 1.2 -3.5 0.8 FR4 10 inch4–miltrace 12 Float 1 1.2 -6 0.6 FR4 15 inch4–miltrace 13 1 0 1.3 0 1.3 FR4 <5 inch4–miltrace 14 1 R 1.3 -3.5 0.9 FR4 10 inch4–miltrace 15 1 Float 1.3 -6 0.7 FR4 15 inch4–miltrace 16 1 1 1.3 -9 0.5 FR4 20 inch4–miltrace Table4.SignalDetectThresholdLevel(1) SD_TH SMBus REG bit[3:2]and [1:0] AssertLevel(typ) De-assertLevel(typ) 0 10 210 mVp-p 150 mVp-p R 01 160 mVp-p 100 mVp-p F (default) 00 180 mVp-p 110 mVp-p 1 11 190 mVp-p 130 mVp-p (1) VDD = 2.5V,25°C and 0101 patternat10.3Gbps SMBUS Master Mode The DS100KR401 devicessupportreadingdirectlyfrom an externalEEPROM deviceby implementingSMBus Mastermode. When usingtheSMBus mastermode, theDS100KR401 willreaddirectlyfromspecificlocationin theexternalEEPROM. When designinga systemforusingtheexternalEEPROM, theuserneeds tofollowthese specificguidelines.

SetENSMB = Float— enabletheSMBUS mastermode.
The externalEEPROM deviceaddressbytemust be 0xA0'hand capableof400 kHz operationat2.5V and 3.3Vsupply.
SettheAD[3:0]inputsforSMBus addressbyte.When theAD[3:0]= 0000'b,thedeviceaddressbyteisB0'h. When tyingmultipleDS100KR401 devicesto the SDA and SCL bus, use these guidelinesto configurethe devices.
Use SMBus AD[3:0]address bitsso thateach devicecan loaded it'sconfigurationfrom the EEPROM. Example belowisfor4 device.
Use a pull-upresistoron SDA and SCL; value= 2k ohms
Daisy-chainREADEN# (pin26)and ALL_DONE# (pin27)fromone devicetothenextdeviceinthesequence so thattheydo notcompete fortheEEPROM atthesame time. – 1.TieREADEN# ofthe1stdeviceinthechain(U1)toGND – 2.TieALL_DONE# ofU1 toREADEN# ofU2 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS100KR401

SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com – 3.TieALL_DONE# ofU2 toREADEN# ofU3 – 4.TieALL_DONE# ofU3 toREADEN# ofU4 – 5.Optional:TieALL_DONE# outputofU4 toa LED toshow thedeviceshave been loadedsuccessfully Below isan example ofa 2 kbits(256 x 8-bit)EEPROM inhex formatfortheDS100KR401 device.The first3 bytesof the EEPROM always containa header common and necessaryto controlinitializationof alldevices connectedtotheI2C bus.CRC enableflagtoenable/disableCRC checking.IfCRC checkingisdisabled,a fixed pattern(8’hA5) iswritten/readinsteadoftheCRC bytefromtheCRC location,tosimplifythecontrol.There isa MAP bittoflagthepresenceofan addressmap thatspecifiestheconfigurationdatastartintheEEPROM. Ifthe MAP bitisnotpresenttheconfigurationdatastartaddressisderivedfrom theDS100KR401 addressand the configurationdata size.A bitto indicatean EEPROM size> 256 bytesisnecessaryto properlyaddressthe EEPROM. Thereare37 bytesofdatasizeforeach DS100KR401 device. :2000000000001000000407002FAD4002FAD4002FAD4002FAD401805F5A8005F5A8005F5A D8 :200020008005F5A800005454 000000000000000000000000000000000000000000000000F6 :20006000000000000000000000000000000000000000000000000000000000000000000080 :20008000000000000000000000000000000000000000000000000000000000000000000060 :2000A000000000000000000000000000000000000000000000000000000000000000000040 :2000C000000000000000000000000000000000000000000000000000000000000000000020 :2000E000000000000000000000000000000000000000000000000000000000000000000000 :200040000000000000000000000000000000000000000000000000000000000000000000A0

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 Table5.EEPROM RegisterMap -SingleDevice withDefaultValue EEPROM Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BIt0Byte Description 0 CRC EN AddressMap EEPROM > 256 RES DEVICE DEVICE DEVICE DEVICE Present Bytes COUNT[3] COUNT[2] COUNT[1] COUNT[0] Value 0 0 0 0 0 0 0 0 Description 1 RES RES RES RES RES RES RES RES Value 0 0 0 0 0 0 0 0 Description 2 Max EEPROM Max EEPROM Max EEPROM Max EEPROM Max EEPROM Max EEPROM Max EEPROM Max EEPROM Burstsize[7] Burstsize[6] Burstsize[5] Burstsize[4] Burstsize[3] Burstsize[2] Burstsize[1] Burstsize[0] Value 0 0 0 0 0 0 0 0 Description 3 PWDN_ch7 PWDN_ch6 PWDN_ch5 PWDN_ch4 PWDN_ch3 PWDN_ch2 PWDN_ch1 PWDN_ch0 Value 0 0 0 0 0 0 0 0 Description 4 RES_1 RES_0 PWDN_INPUTS PWDN_OSC Ovrd_RESET RES RES RES Value 0 0 0 0 0 0 0 0 Description 5 RES RES RES RES RES RES_btb_en Ovrd_RES Ovrd_RES Value 0 0 0 0 0 1 0 0 Description 6 Ovrd_RES Ovrd_RES Ovrd_RES Ovrd_RES Ovrd_RES rx_delay_sel_2 rx_delay_sel_1 rx_delay_sel_0 Value 0 0 0 0 0 1 1 1 Description 7 RD_delay_sel_3 RD_delay_sel_2 RD_delay_sel_1 RD_delay_sel_0 ch0_Idle_auto ch0_Idle_sel ch0_RES_1 ch0_RES_0 Value 0 0 0 0 0 0 0 0 Description 8 ch0_BST_7 ch0_BST_6 ch0_BST_5 ch0_BST_4 ch0_BST_3 ch0_BST_2 ch0_BST_1 ch0_BST_0 Value 0 0 1 0 1 1 1 1 Description 9 ch0_Sel_scp ch0_Sel_mode ch0_RES_2 ch0_RES_1 ch0_RES_0 ch0_VOD_2 ch0_VOD_1 ch0_VOD_0 Value 1 0 1 0 1 1 0 1 Description 10 ch0_DEM_2 ch0_DEM_1 ch0_DEM_0 ch0_Slow ch0_idle_tha_1 ch0_idle_tha_0 ch0_idle_thd_1 ch0_idle_thd_0 Value 0 1 0 0 0 0 0 0 Description 11 ch1_Idle_auto ch1_Idle_sel ch1_RES_1 ch1_RES_0 ch1_BST_7 ch1_BST_6 ch1_BST_5 ch1_BST_4 Value 0 0 0 0 0 0 1 0 Description 12 ch1_BST_3 ch1_BST_2 ch1_BST_1 ch1_BST_0 ch1_Sel_scp ch1_Sel_mode ch1_RES_2 ch1_RES_1 Value 1 1 1 1 1 0 1 0 Description 13 ch1_RES_0 ch1_VOD_2 ch1_VOD_1 ch1_VOD_0 ch1_DEM_2 ch1_DEM_1 ch1_DEM_0 ch1_Slow Value 1 1 0 1 0 1 0 0 Description 14 ch1_idle_tha_1 ch1_idle_tha_0 ch1_idle_thd_1 ch1_idle_thd_0 ch2_Idle_auto ch2_Idle_sel ch2_RES_1 ch2_RES_0 Value 0 0 0 0 0 0 0 0 Description 15 ch2_BST_7 ch2_BST_6 ch2_BST_5 ch2_BST_4 ch2_BST_3 ch2_BST_2 ch2_BST_1 ch2_BST_0 Value 0 0 1 0 1 1 1 1 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS100KR401

SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com Table5.EEPROM RegisterMap -SingleDevice withDefaultValue (continued) EEPROM Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BIt0Byte Description 16 ch2_Sel_scp ch2_Sel_mode ch2_RES_2 ch2_RES_1 ch2_RES_0 ch2_VOD_2 ch2_VOD_1 ch2_VOD_0 Value 1 0 1 0 1 1 0 1 Description 17 ch2_DEM_2 ch2_DEM_1 ch2_DEM_0 ch2_Slow ch2_idle_tha_1 ch2_idle_tha_0 ch2_idle_thd_1 ch2_idle_thd_0 Value 0 1 0 0 0 0 0 0 Description 18 ch3_Idle_auto ch3_Idle_sel ch3_RES_1 ch3_RES_0 ch3_BST_7 ch3_BST_6 ch3_BST_5 ch3_BST_4 Value 0 0 0 0 0 0 1 0 Description 19 ch3_BST_3 ch3_BST_2 ch3_BST_1 ch3_BST_0 ch3_Sel_scp ch3_Sel_mode ch3_RES_2 ch3_RES_1 Value 1 1 1 1 1 0 1 0 Description 20 ch3_RES_0 ch3_VOD_2 ch3_VOD_1 ch3_VOD_0 ch3_DEM_2 ch3_DEM_1 ch3_DEM_0 ch3_Slow Value 1 1 0 1 0 1 0 0 Description 21 ch3_idle_tha_1 ch3_idle_tha_0 ch3_idle_thd_1 ch3_idle_thd_0 ovrd_fast_idle en_high_idle_th_nen_high_idle_th_sen_fast_idle_n Value 0 0 0 0 0 0 0 1 Description 22 en_fast_idle_s eqsd_mgain_n eqsd_mgain_s ch4_Idle_auto ch4_Idle_sel ch4_RXDET_1 ch4_RXDET_0 ch4_BST_7 Value 1 0 0 0 0 0 0 0 Description 23 ch4_BST_6 ch4_BST_5 ch4_BST_4 ch4_BST_3 ch4_BST_2 ch4_BST_1 ch4_BST_0 ch4_Sel_scp Value 0 1 0 1 1 1 1 1 Description 24 ch4_Sel_mode ch4_RES_2 ch4_RES_1 ch4_RES_0 ch4_VOD_2 ch4_VOD_1 ch4_VOD_0 ch4_DEM_2 Value 0 1 0 1 1 0 1 0 Description 25 ch4_DEM_1 ch4_DEM_0 ch4_Slow ch4_idle_tha_1 ch4_idle_tha_0 ch4_idle_thd_1 ch4_idle_thd_0 ch5_Idle_auto Value 1 0 0 0 0 0 0 0 Description 26 ch5_Idle_sel ch5_RES_1 ch5_RES_0 ch5_BST_7 ch5_BST_6 ch5_BST_5 ch5_BST_4 ch5_BST_3 Value 0 0 0 0 0 1 0 1 Description 27 ch5_BST_2 ch5_BST_1 ch5_BST_0 ch5_Sel_scp ch5_Sel_mode ch5_RES_2 ch5_RES_1 ch5_RES_0 Value 1 1 1 1 0 1 0 1 Description 28 ch5_VOD_2 ch5_VOD_1 ch5_VOD_0 ch5_DEM_2 ch5_DEM_1 ch5_DEM_0 ch5_Slow ch5_idle_tha_1 Value 1 0 1 0 1 0 0 0 Description 29 ch5_idle_tha_0 ch5_idle_thd_1 ch5_idle_thd_0 ch6_Idle_auto ch6_Idle_sel ch6_RES_1 ch6_RES_0 ch6_BST_7 Value 0 0 0 0 0 0 0 0 Description 30 ch6_BST_6 ch6_BST_5 ch6_BST_4 ch6_BST_3 ch6_BST_2 ch6_BST_1 ch6_BST_0 ch6_Sel_scp Value 0 1 0 1 1 1 1 1 Description 31 ch6_Sel_mode ch6_RES_2 ch6_RES_1 ch6_RES_0 ch6_VOD_2 ch6_VOD_1 ch6_VOD_0 ch6_DEM_2 Value 0 1 0 1 1 0 1 0

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 Table5.EEPROM RegisterMap -SingleDevice withDefaultValue (continued) EEPROM Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BIt0Byte Description 32 ch6_DEM_1 ch6_DEM_0 ch6_Slow ch6_idle_tha_1 ch6_idle_tha_0 ch6_idle_thd_1 ch6_idle_thd_0 ch7_Idle_auto Value 1 0 0 0 0 0 0 0 Description 33 ch7_Idle_sel ch7_RES_1 ch7_RES_0 ch7_BST_7 ch7_BST_6 ch7_BST_5 ch7_BST_4 ch7_BST_3 Value 0 0 0 0 0 1 0 1 Description 34 ch7_BST_2 ch7_BST_1 ch7_BST_0 ch7_Sel_scp ch7_Sel_mode ch7_RES_2 ch7_RES_1 ch7_RES_0 Value 1 1 1 1 0 1 0 1 Description 35 ch7_VOD_2 ch7_VOD_1 ch7_VOD_0 ch7_DEM_2 ch7_DEM_1 ch7_DEM_0 ch7_Slow ch7_idle_tha_1 Value 1 0 1 0 1 0 0 0 Description 36 ch7_idle_tha_0 ch7_idle_thd_1 ch7_idle_thd_0 iph_dac_ns_1 iph_dac_ns_0 ipp_dac_ns_1 ipp_dac_ns_0 ipp_dac_1 Value 0 0 0 0 0 0 0 0 Description 37 ipp_dac_0 RD23_67 RD01_45 RD_PD_ovrd RD_Sel_test RD_RESET_ovrd PWDB_input_DC DEM_VOD_ovrd Value 0 0 0 0 0 0 0 0 Description 38 DEM_ovrd_N2 DEM_ovrd_N1 DEM_ovrd_N0 VOD_ovrd_N2 VOD_ovrd_N1 VOD_ovrd_N0 SPARE0 SPARE1 Value 0 1 0 1 0 1 0 0 Description 39 DEM__ovrd_S2 DEM__ovrd_S1 DEM_ovrd_S0 VOD_ovrd_S2 VOD_ovrd_S1 VOD_ovrd_S0 SPARE0 SPARE1 Value 0 1 0 1 0 1 0 0 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS100KR401

SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com Table6. Example ofEEPROM for4 Devices Using 2 Address Maps (1) EEPROM Address Address (Hex) EEPROM Data Comments 0 00 0x43 CRC_EN = 0,AddressMap = 1,>256 bytes= 0,DeviceCount[3:0]= 3 1 01 0x00 2 02 0x08 EEPROM BurstSize 3 03 0x00 CRC notused 4 04 0x0B Device0 AddressLocation 5 05 0x00 CRC notused 6 06 0x0B Device1 AddressLocation 7 07 0x00 CRC notused 8 08 0x30 Device2 AddressLocation 9 09 0x00 CRC notused 10 0A 0x30 Device3 AddressLocation 11 0B 0x00 BeginDevice0,1 -AddressOffset3 12 0C 0x00 13 0D 0x04 14 0E 0x07 15 0F 0x00 16 10 0x00 EQ CHB0 = 00 17 11 0xAB VOD CHB0 = 1.0V 18 12 0x00 DEM CHB0 = 0 (0dB) 19 13 0x00 EQ CHB1 = 00 20 14 0x0A VOD CHB1 = 1.0V 21 15 0xB0 DEM CHB1 = 0 (0dB) 22 16 0x00 23 17 0x00 EQ CHB2 = 00 24 18 0xAB VOD CHB2 = 1.0V 25 19 0x00 DEM CHB2 = 0 (0dB) 26 1A 0x00 EQ CHB3 = 00 27 1B 0x0A VOD CHB3 = 1.0V 28 1C 0xB0 DEM CHB3 = 0 (0dB) 29 1D 0x01 30 1E 0x80 31 1F 0x01 EQ CHA0 = 00 32 20 0x56 VOD CHA0 = 1.0V 33 21 0x00 DEM CHA0 = 0 (0dB) 34 22 0x00 EQ CHA1 = 00 35 23 0x15 VOD CHA1 = 1.0V 36 24 0x60 DEM CHA1 = 0 (0dB) 37 25 0x00 38 26 0x01 EQ CHA2 = 00 39 27 0x56 VOD CHA2 = 1.0V 40 28 0x00 DEM CHA2 = 0 (0dB) 41 29 0x00 EQ CHA3 = 00 42 2A 0x15 VOD CHA3 = 1.0V 43 2B 0x60 DEM CHA3 = 0 (0dB) 44 2C 0x00 45 2D 0x00 (1) CRC_EN = 0,AddressMap = 1,>256 byte= 0,DeviceCount[3:0]= 3.Thisexample has all8–channelssettoEQ = 00 (minboost), VOD = 1.0V,DEM = 0 (0dB)and multipledevicecan pointtothesame addressmap.

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 Table6. Example ofEEPROM for4 Devices Using 2 Address Maps (1)(continued) EEPROM Address Address (Hex) EEPROM Data Comments 46 2E 0x54 47 2F 0x54 End Device0,1 -AddressOffset39 48 30 0x00 BeginDevice2,3 -AddressOffset3 49 31 0x00 50 32 0x04 51 33 0x07 52 34 0x00 53 35 0x00 EQ CHB0 = 00 54 36 0xAB VOD CHB0 = 1.0V 55 37 0x00 DEM CHB0 = 0 (0dB) 56 38 0x00 EQ CHB1 = 00 57 39 0x0A VOD CHB1 = 1.0V 58 3A 0xB0 DEM CHB1 = 0 (0dB) 59 3B 0x00 60 3C 0x00 EQ CHB2 = 00 61 3D 0xAB VOD CHB2 = 1.0V 62 3E 0x00 DEM CHB2 = 0 (0dB) 63 3F 0x00 EQ CHB3 = 00 64 40 0x0A VOD CHB3 = 1.0V 65 41 0xB0 DEM CHB3 = 0 (0dB) 66 42 0x01 67 43 0x80 68 44 0x01 EQ CHA0 = 00 69 45 0x56 VOD CHA0 = 1.0V 70 46 0x00 DEM CHA0 = 0 (0dB) 71 47 0x00 EQ CHA1 = 00 72 48 0x15 VOD CHA1 = 1.0V 73 49 0x60 DEM CHA1 = 0 (0dB) 74 4A 0x00 75 4B 0x01 EQ CHA2 = 00 76 4C 0x56 VOD CHA2 = 1.0V 77 4D 0x00 DEM CHA2 = 0 (0dB) 78 4E 0x00 EQ CHA3 = 00 79 4F 0x15 VOD CHA3 = 1.0V 80 50 0x60 DEM CHA3 = 0 (0dB) 81 51 0x00 82 52 0x00 83 53 0x54 84 54 0x54 End Device2,3 -AddressOffset39 SYSTEM MANAGEMENT BUS (SMBus) and CONFIGURATION REGISTERS The System Management Bus interfaceiscompatibletoSMBus 2.0physicallayerspecification.ENSMB = 1kΩ toVDD toenableSMBus slavemode and allowaccesstotheconfigurationregisters. The DS100KR401 has theAD[3:0]inputsinSMBus mode. These pinsare theusersetSMBUS slaveaddress inputs.The AD[3:0]pinshave internalpull-down.When leftfloatingorpulledlowtheAD[3:0]= 0000'b,thedevice defaultaddressbyteisB0'h.Based on theSMBus 2.0specification,theDS100KR401 has a 7-bitslaveaddress. The LSB issetto 0'b(fora WRITE). The devicesupportsup to 16 addressbyte,which can be setwiththe AD[3:0]inputs.Below arethe16 addresses. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS100KR401

SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com Table7.Device SlaveAddress Bytes AD[3:0]Settings Address Bytes (HEX) 0000 B0 0001 B2 0010 B4 0011 B6 0100 B8 0101 BA 0110 BC 0111 BE 1000 C0 1001 C2 1010 C4 1011 C6 1100 C8 1101 CA 1110 CC 1111 CE The SDA, SCL pinsare 3.3V tolerant,butare not5V tolerant.Externalpull-upresistorisrequiredon theSDA. The resistorvaluecan be from 1 kΩ to5 kΩ dependingon thevoltage,loadingand speed.The SCL may also requirean externalpull-upresistorand itdepends on theHostthatdrivesthebus. TRANSFER OF DATA VIA THE SMBus Duringnormaloperationthedataon SDA must be stableduringthetimewhen SCL isHigh. TherearethreeuniquestatesfortheSMBus: START: A High-to-Lowtransitionon SDA whileSCL isHighindicatesa message START condition. STOP: A Low-to-Hightransitionon SDA whileSCL isHighindicatesa message STOP condition. IDLE: IfSCL and SDA arebothHigh fora timeexceedingtBUF fromthelastdetectedSTOP conditionorifthey areHighfora totalexceedingthemaximum specificationfortHIGH thenthebus willtransfertotheIDLE state. SMBus TRANSACTIONS The devicesupportsWRITE and READ transactions.See RegisterDescriptiontableforregisteraddress,type (Read/Write,Read Only),defaultvalueand functioninformation.

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 WRITING A REGISTER To writea register,thefollowingprotocolisused (seeSMBus 2.0specification). 1. The Hostdrivesa START condition,the7-bitSMBus address,and a “0”indicatinga WRITE. 2. The Device(Slave)drivestheACK bit(“0”). 3. The Hostdrivesthe8-bitRegisterAddress. 4. The Devicedrivesan ACK bit(“0”). 5. The Hostdrivethe8-bitdatabyte. 6. The Devicedrivesan ACK bit(“0”). 7. The Hostdrivesa STOP condition. The WRITE transactioniscompleted,the bus goes IDLE and communicationwithotherSMBus devicesmay now occur. READING A REGISTER To reada register,thefollowingprotocolisused (seeSMBus 2.0specification). 1. The Hostdrivesa START condition,the7-bitSMBus address,and a “0”indicatinga WRITE. 2. The Device(Slave)drivestheACK bit(“0”). 3. The Hostdrivesthe8-bitRegisterAddress. 4. The Devicedrivesan ACK bit(“0”). 5. The Hostdrivesa START condition. 6. The Hostdrivesthe7-bitSMBus Address,and a “1”indicatinga READ. 7. The Devicedrivesan ACK bit“0”. 8. The Devicedrivesthe8-bitdatavalue(registercontents). 9. The Hostdrivesa NACK bit“1”indicatingend oftheREAD transfer. 10. The Hostdrivesa STOP condition. The READ transactioniscompleted,thebus goes IDLE and communicationwithotherSMBus devicesmay now occur. Pleasesee SMBus RegisterMap Tableformore information. Table8. SMBUS SlaveMode RegisterMap Address RegisterName Bit(s) Field Type Default Description 0x00 Observation, 7 Reserved R/W 0x00 Setbitto0. Reset 6:3 AddressBit R ObservationofAD[3:0]bit AD[3:0] [6]:AD3 [5]:AD2 [4]:AD1 [3]:AD0

2 EEPROM Read R 1:Devicecompletedthereadfromexternal

Done EEPROM.

1 BlockReset R/W 1:Blockbit0 fromresetttingtheregisters;self

clearing.

0 Reset R/W SMBus Reset

1:Resetregisterstodefaultvalue;selfclearing. 0x01 PWDN Channels 7:0 PWDN CHx R/W 0x00 Power Down perChannel [7]:CH7 – CHA_3 [6]:CH6 – CHA_2 [5]:CH5 – CHA_1 [4]:CH4 – CHA_0 [3]:CH3 – CHB_3 [2]:CH2 – CHB_2 [1]:CH1 – CHB_1 [0]:CH0 – CHB_0 00'h= allchannelsenabled FF'h= allchannelsdisabled Note:overrideRESET pin. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DS100KR401

SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com Table8. SMBUS SlaveMode RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x02 OverrideRESET, 7:6 Reserved R/W 0x00 Setbitsto0. LPBK Control 5:4 LPBK Control 00:Use LPBK pincontrol 01:INA toOUTB loopback 10:INB toOUTA loopback 11:Disableloopbackand ignoreLPBK pin. 3:1 Reserved Setbitsto0.

0 OverrideRESET 1:BlockRESET pincontrol

0:AllowRESET pincontrol 0x05 SlaveMode CRC Bits 7:0 CRC bits R/W 0x00 CRC bits[7:0] 0x06 SlaveCRC Control 7:5 Reserved R/W 0x10 Setbitsto0. 4 Reserved Setbitto1.

3 SlaveCRC 1:DisablestheslaveCRC mode

0:EnablestheslaveCRC mode Note:Inordertochange VOD, DEM and EQ ofthe channelsinslavemode, setbitto1 todisablethe CRC. 2:0 Reserved Setbitsto0. 0x08 Override 7 Reserved R/W 0x00 Setbitto0. PinControl 6 OverrideSD_TH 1:BlockSD_TH pincontrol 0:AllowSD_TH pincontrol 5:2 Reserved Setbitsto0.

1 OverrideDEM 1:BlockDEM pincontrol

0:AllowDEM pincontrol 0 Reserved Setbitto0. 0x0E CH0 -CHB0 7:0 Reserved R/W 0x00 Setbitsto0. Reserved 0x0F CH0 -CHB0 7:0 EQ Control R/W 0x2F IB0EQ Control-totalof256 levels. EQ See Table2. 0x10 CH0 -CHB0 7 ShortCircuit R/W 0xAD 1:Enabletheshortcircuitprotection VOD Protection 0:Disabletheshortcircuitprotection 6 Reserved Setbitto0. 5:3 Reserved Setbitstodefaultvalue-101. 2:0 VOD Control OB0 VOD Control 000:0.7V 001:0.8V 010:0.9V 011:1.0V 100:1.1V 101:1.2V (default) 110:1.3V 111:1.4V 0x11 CH0 -CHB0 7 STATUS R 0x02 ObservationbitforCH0 -CHB0. DEM 6:5 STATUS R ObservationbitforCH0 -CHB0. 4:3 Reserved R/W Setbitsto0. 2:0 DEM Control R/W OB0 DEM Control 000:0 dB 001:–1.5dB 010:–3.5dB (default) 011:–5 dB 100:–6 dB 101:–8 dB 110:–9 dB 111:–12 dB

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 Table8. SMBUS SlaveMode RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x12 CH0 -CHB0 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:2 IDLE thd De-assertthreshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note:overridetheSD_TH pin. 1:0 IDLE tha Assertthreshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note:overridetheSD_TH pin. 0x15 CH1 -CHB1 7:0 Reserved R/W 0x00 Setbitsto0. Reserved 0x16 CH1 -CHB1 7:0 EQ Control R/W 0x2F IB1EQ Control-totalof256 levels.See Table2. EQ 0x17 CH1 -CHB1 7 ShortCircuit R/W 0xAD 1:Enabletheshortcircuitprotection VOD Protection 0:Disabletheshortcircuitprotection 6 Reserved Setbitto0. 5:3 Reserved Setbitstodefaultvalue-101. 2:0 VOD Control OB1 VOD Control 000:0.7V 001:0.8V 010:0.9V 011:1.0V 100:1.1V 101:1.2V (default) 110:1.3V 111:1.4V 0x18 CH1 -CHB1 7 STATUS R 0x02 ObservationbitforCH1 -CHB1. DEM 6:5 STATUS R ObservationbitforCH1 -CHB1. 4:3 Reserved R/W Setbitsto0. 2:0 DEM Control R/W OB1 DEM Control 000:0 dB 001:–1.5dB 010:–3.5dB (default) 011:–5 dB 100:–6 dB 101:–8 dB 110:–9 dB 111:–12 dB 0x19 CH1 -CHB1 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:2 IDLE thd De-assertthreshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note:overridetheSD_TH pin. 1:0 IDLE tha Assertthreshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note:overridetheSD_TH pin. 0x1C CH2 -CHB2 7:0 Reserved R/W 0x00 Setbitsto0. Reserved 0x1D CH2 -CHB2 7:0 EQ Control R/W 0x2F IB2EQ Control-totalof256 levels.See Table2. EQ Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:DS100KR401

SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com Table8. SMBUS SlaveMode RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x1E CH2 -CHB2 7 ShortCircuit R/W 0xAD 1:Enabletheshortcircuitprotection VOD Protection 0:Disabletheshortcircuitprotection 6 Reserved Setbitto0. 5:3 Reserved Setbitstodefaultvalue-101. 2:0 VOD Control OB2 VOD Control 000:0.7V 001:0.8V 010:0.9V 011:1.0V 100:1.1V 101:1.2V (default) 110:1.3V 111:1.4V 0x1F CH2 -CHB2 7 STATUS R 0x02 ObservationbitforCH2 -CHB2. DEM 6:5 STATUS R ObservationbitforCH2 -CHB2. 4:3 Reserved R/W Setbitsto0. 2:0 DEM Control R/W OB2 DEM Control 000:0 dB 001:–1.5dB 010:–3.5dB (default) 011:–5 dB 100:–6 dB 101:–8 dB 110:–9 dB 111:–12 dB 0x20 CH2 -CHB2 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:2 IDLE thd De-assertthreshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note:overridetheSD_TH pin. 1:0 IDLE tha Assertthreshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note:overridetheSD_TH pin. 0x23 CH3 -CHB3 7:0 Reserved R/W 0x00 Setbitsto0. Reserved 0x24 CH3 -CHB3 7:0 EQ Control R/W 0x2F IB3EQ Control-totalof256 levels.See Table2. EQ 0x25 CH3 -CHB3 7 ShortCircuit R/W 0xAD 1:Enabletheshortcircuitprotection VOD Protection 0:Disabletheshortcircuitprotection 6 Reserved Setbitto0. 5:3 Reserved Setbitstodefaultvalue-101. 2:0 VOD Control OB0 VOD Control 000:0.7V 001:0.8V 010:0.9V 011:1.0V 100:1.1V 101:1.2V (default) 110:1.3V 111:1.4V

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 Table8. SMBUS SlaveMode RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x26 CH3 -CHB3 7 STATUS R 0x02 ObservationbitforCH3 -CHB3. DEM 6:5 STATUS R ObservationbitforCH3 -CHB3. 4:3 Reserved R/W Setbitsto0. 2:0 DEM Control R/W OB3 DEM Control 000:0 dB 001:–1.5dB 010:–3.5dB (default) 011:–5 dB 100:–6 dB 101:–8 dB 110:–9 dB 111:–12 dB 0x27 CH3 -CHB3 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:2 IDLE thd De-assertthreshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note:overridetheSD_TH pin. 1:0 IDLE tha Assertthreshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note:overridetheSD_TH pin. 0x2B CH4 -CHA0 7:0 Reserved R/W 0x00 Setbitsto0. Reserved 0x2C CH4 -CHA0 7:0 EQ Control R/W 0x2F IA0EQ Control-totalof256 levels. EQ See Table2. 0x2D CH4 -CHA0 7 ShortCircuit R/W 0xAD 1:Enabletheshortcircuitprotection VOD Protection 0:Disabletheshortcircuitprotection 6 Reserved Setbitto0. 5:3 Reserved Setbitstodefaultvalue-101. 2:0 VOD Control OA0 VOD Control 000:0.7V 001:0.8V 010:0.9V 011:1.0V 100:1.1V 101:1.2V (default) 110:1.3V 111:1.4V 0x2E CH4 -CHA0 7 STATUS R 0x02 ObservationbitforCH4 -CHA0. DEM 6:5 STATUS R ObservationbitforCH4 -CHA0. 4:3 Reserved R/W Setbitsto0. 2:0 DEM Control R/W OA0 DEM Control 000:0 dB 001:–1.5dB 010:–3.5dB (default) 011:–5 dB 100:–6 dB 101:–8 dB 110:–9 dB 111:–12 dB Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:DS100KR401

SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com Table8. SMBUS SlaveMode RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x2F CH4 -CHA0 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:2 IDLE thd De-assertthreshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note:overridetheSD_TH pin. 1:0 IDLE tha Assertthreshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note:overridetheSD_TH pin. 0x32 CH5 -CHA1 7:0 Reserved R/W 0x00 Setbitsto0. Reserved 0x33 CH5 -CHA1 7:0 EQ Control R/W 0x2F IA1EQ Control-totalof256 levels.See Table2. EQ 0x34 CH5 -CHA1 7 ShortCircuit R/W 0xAD 1:Enabletheshortcircuitprotection VOD Protection 0:Disabletheshortcircuitprotection 6 Reserved Setbitto0. 5:3 Reserved Setbitstodefaultvalue-101. 2:0 VOD Control OA1 VOD Control 000:0.7V 001:0.8V 010:0.9V 011:1.0V 100:1.1V 101:1.2V (default) 110:1.3V 111:1.4V 0x35 CH5 -CHA1 7 STATUS R 0x02 ObservationbitforCH5 -CHA1. DEM 6:5 STATUS R ObservationbitforCH5 -CHA1. 4:3 Reserved R/W Setbitsto0. 2:0 DEM Control R/W OA1 DEM Control 000:0 dB 001:–1.5dB 010:–3.5dB (default) 011:–5 dB 100:–6 dB 101:–8 dB 110:–9 dB 111:–12 dB 0x36 CH5 -CHA1 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:2 IDLE thd De-assertthreshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note:overridetheSD_TH pin. 1:0 IDLE tha Assertthreshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note:overridetheSD_TH pin. 0x39 CH6 -CHA2 7:0 Reserved R/W 0x00 Setbitsto0. Reserved 0x3A CH6 -CHA2 7:0 EQ Control R/W 0x2F IA2EQ Control-totalof256 levels.See Table2. EQ

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 Table8. SMBUS SlaveMode RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x3B CH6 -CHA2 7 ShortCircuit R/W 0xAD 1:Enabletheshortcircuitprotection VOD Protection 0:Disabletheshortcircuitprotection 6 Reserved Setbitto0. 5:3 Reserved Setbitstodefaultvalue-101. 2:0 VOD Control OA2 VOD Control 000:0.7V 001:0.8V 010:0.9V 011:1.0V 100:1.1V 101:1.2V (default) 110:1.3V 111:1.4V 0x3C CH6 -CHA2 7 STATUS R 0x02 ObservationbitforCH6 -CHA2. DEM 6:5 STATUS R ObservationbitforCH6 -CHA2. 4:3 Reserved R/W Setbitsto0. 2:0 DEM Control R/W OA2 DEM Control 000:0 dB 001:–1.5dB 010:–3.5dB (default) 011:–5 dB 100:–6 dB 101:–8 dB 110:–9 dB 111:–12 dB 0x3D CH6 -CHA2 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:2 IDLE thd De-assertthreshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note:overridetheSD_TH pin. 1:0 IDLE tha Assertthreshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note:overridetheSD_TH pin. 0x40 CH7 -CHA3 7:0 Reserved R/W 0x00 Setbitsto0. Reserved 0x41 CH7 -CHA3 7:0 EQ Control R/W 0x2F IA3EQ Control-totalof256 levels.See Table2. EQ 0x42 CH7 -CHA3 7 ShortCircuit R/W 0xAD 1:Enabletheshortcircuitprotection VOD Protection 0:Disabletheshortcircuitprotection 6 Reserved Setbitto0. 5:3 Reserved Setbitstodefaultvalue-101. 2:0 VOD Control OA3 VOD Control 000:0.7V 001:0.8V 010:0.9V 011:1.0V 100:1.1V 101:1.2V (default) 110:1.3V 111:1.4V Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:DS100KR401

SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com Table8. SMBUS SlaveMode RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x43 CH7 -CHA3 7 STATUS R 0x02 ObservationbitforCH7 -CHA3. DEM 6:5 STATUS R ObservationbitforCH7 -CHA3. 4:3 Reserved R/W Setbitsto0. 2:0 DEM Control R/W OA3 DEM Control 000:0 dB 001:–1.5dB 010:–3.5dB (default) 011:–5 dB 100:–6 dB 101:–8 dB 110:–9 dB 111:–12 dB 0x44 CH7 -CHA3 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:2 IDLE thd De-assertthreshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note:overridetheSD_TH pin. 1:0 IDLE tha Assertthreshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note:overridetheSD_TH pin. 0x51 DeviceID 7:5 VERSION R 0x44 010'b 4:0 ID 00100'b

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 APPLICATIONS INFORMATION GENERAL RECOMMENDATIONS The DS100KR401 isa highperformancecircuitcapableof deliveringexcellentperformance.Carefulattention must be paidtothedetailsassociatedwithhigh-speeddesignas wellas providinga cleanpower supply.Refer to the informationbelow and Revision4 of the LVDS Owner's Manual formore detailedinformationon high speed designtipstoaddresssignalintegritydesignissues. PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS The CML inputsand outputshave been optimizedto work withinterconnectsusinga controlleddifferential impedance of 85 - 100Ω. Itis preferableto routedifferentiallinesexclusivelyon one layerof the board, particularlyfortheinputtraces.The use ofviasshouldbe avoidedifpossible.Ifviasmust be used,theyshould be used sparinglyand must be placed symmetricallyforeach side of a given differentialpair.Whenever differentialviasare used thelayoutmust alsoprovidefora low inductancepathforthereturncurrentsas well. Route thedifferentialsignalsaway from othersignalsand noisesourceson theprintedcircuitboard.See AN- 1187 (SNOA401 )foradditionalinformationon WQFN packages. Figure6. TypicalRouting Options The graphicshown above depictsdifferenttransmissionlinetopologieswhich can be used in various combinationstoachievetheoptimalsystem performance.Impedance discontinuitiesatthedifferentialviacan be minimizedor eliminatedby increasingthe swellaround each holeand providingfora low inductancereturn currentpath.When theviastructureisassociatedwiththickbackplanePCB, furtheroptimizationsuch as back drillingisoftenused toreducethedeterimentialhighfrequencyeffectsofstubson thesignalpath. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:DS100KR401

SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com POWER SUPPLY BYPASSING Two approachesarerecommended toensurethattheDS100KR401 isprovidedwithan adequatepower supply. First,thesupply(VDD) and ground(GND) pinsshouldbe connectedtopower planesroutedon adjacentlayers oftheprintedcircuitboard.The layerthicknessofthedielectricshouldbe minimizedso thattheVDD and GND planes createa low inductancesupply with distributedcapacitance.Second, carefulattentionto supply bypassingthroughthe properuse of bypass capacitorsis required.A 0.1 μF bypass capacitorshould be connectedtoeach VDD pinsuch thatthecapacitorisplacedas closeas possibletotheDS100KR401. Smaller body sizecapacitorscan helpfacilitatepropercomponent placement.Inthecase of3.3V mode operationwith theinternalLDO regulator,recommend usingcapacitorswithcapacitanceintherangeof1.0μF to10 μF should be incorporatedinthepower supplybypassingdesignfortheVIN pin.These capacitorsshouldbe ultra-lowESR ceramic.

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-40 -15 10 35 60 85 VOD (mVp-p) TEMPERATURE (° C) VDD = 2.5V 1007 1010 1013 1016 1019 1021 2.375 2.5 2.625 VOD (mVp-p) VDD (V) T = 25° C 420.0 440.0 460.0 480.0 500.0 520.0 540.0 560.0 580.0 600.0 620.0 640.0 VOD (Vp-p) PD (mW) VDD = 2.625V VDD = 2.5V VDD = 2.375V T = 25° C DS100KR401 www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 TYPICAL CHARACTERISTICS TypicalPerformance Curves Characteristics Figure7. Power Dissipation(PD)vs.Output DifferentialVoltage(VOD) Figure8. Output DifferentialVoltage(VOD = 1.0Vp-p)vs.Supply Voltage(VDD) Figure9. Output DifferentialVoltage(VOD = 1.0Vp-p)vs.Temperature Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:DS100KR401

VID = 1.0 Vp-p, DE = -9 dB

10.3125 Gb/s,

BW = 50 GHzDS100KR401TL1 Lossy Channel IN OUT TL2 Lossy Channel Pattern Generator VID = 1.0 Vp-p, DE = 0 dB BW = 50 GHzDS100KR401IN OUTTL Lossy Channel DS100KR401 SNLS395B –JANUARY 2012–REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) TypicalPerformance Eye Diagrams Characteristics Figure10. TestSetup Connections Diagram Figure11. TL = 20 inch4–milFR4 trace, DS100KR401 settings:EQ[1:0]= R, R = 15'h,DEM[1:0] = float,float Figure12. TL = 30 inch4–milFR4 trace, DS100KR401 settings:EQ[1:0]= float,R = 1F'h,DEM[1:0] = float,float Figure13. TestSetup Connections Diagram

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www.ti.com SNLS395B –JANUARY 2012–REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) Figure14. TL1 = 20 inch4–milFR4 trace,TL2 = 15 inch4–milFR4 trace, DS100KR401 settings:EQ[1:0]= R, R = 15'h,DEM[1:0] = float,float Figure15. TL1 = 30 inch4–milFR4 trace,TL2 = 15 inch4–milFR4 trace, DS100KR401 settings:EQ[1:0]= float,R = 1F'h,DEM[1:0] = float,float Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:DS100KR401

www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples DS100KR401SQ/NOPB ACTIVE WQFN NJY 54 2000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 DS100KR401SQ DS100KR401SQE/NOPB ACTIVE WQFN NJY 54 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 DS100KR401SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS100KR401SQ/NOPB WQFN NJY 54 2000 367.0 367.0 38.0 DS100KR401SQE/NOPB WQFN NJY 54 250 213.0 191.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 54X 0.3 0.2 3.51±0.1 50X 0.5 54X 0.5 0.3

0.8 MAX

8.5 7.5±0.1 2X 4 A 10.1 9.9 B 5.6 5.4 0.3 0.2 0.5 0.3 (0.1) 4214993/A 07/2013 WQFNNJY0054A WQFN PIN 1 INDEX AREA SEATING PLANE 18 28 19 27 54 46

0.1 C A B

0.05 C (OPTIONAL) PIN 1 ID DETAIL SEE TERMINAL NOTES: 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 2.000 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT (3.51)

0.07 MIN

0.07 MAX

54X (0.6) 54X (0.25) (9.8) (5.3) ( ) TYP VIA 0.2 50X (0.5) (1.16) (1) TYP (7.5) (1.17) TYP 4214993/A 07/2013 WQFNNJY0054A WQFN SYMM SEE DETAILS 19 27 4654 SYMM LAND PATTERN EXAMPLE SCALE:8X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING METAL SOLDER MASK DEFINED METAL SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN (1.17) TYP (5.3) 54X (0.6) 54X (0.25) 12X (1.51) (9.8) (0.855) TYP 12X (0.97) 50X (0.5) 4214993/A 07/2013 WQFNNJY0054A WQFN NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM TYP METAL SOLDERPASTE EXAMPLE BASED ON 0.125mm THICK STENCIL EXPOSED PAD 67% PRINTED SOLDER COVERAGE BY AREA SCALE:10X 19 27 4654 SYMM

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