DS100BR410 TI1 | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 21
Technical content
Features
■ Quad channel repeater for up to 10.3125 Gbps ■ Low power consumption, with option to power down unused channels ■ Adjustable receive equalization ■ Adjustable transmit de-emphasis ■ Adjustable transmit VOD (up to 1200 mVp-p) ■ IDLE detection — squelch function auto mutes the output for SATA/SAS OOB signal ■ <0.22 UI of residual DJ at 10.3125 Gbps with 12 meters cable ■ Programmable via pin selection or SMBus interface ■ Single supply operation at 2.5 V ±5% ■ -40°C to +85°C Operation ■ ≥7 kV HBM ESD Rating ■ High speed signal flow–thru pinout package: 48-pin LLP (7 mm x 7 mm, 0.5 mm pitch)
Applications
■ High-speed active copper cable modules ■ FR-4 Backplanes ■ 10GE, 8GFC, 10GFC, 10G SONET, SAS, SATA, and InfiniBand Typical Application Diagram 30122480 © 2012 Texas Instruments Incorporated 301224 SNLS326A www.ti.com DS100BR410 Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and De-Emphasis Driver
Ordering Information
DS100BR410SQE 48-pin LLP (7mm X 7mm X 0.8mm, 0.5mm pitch) 250 in Tape & Reel SQA48A NOPB DS100BR410SQ 48-pin LLP (7mm X 7mm X 0.8mm, 0.5mm pitch) 1000 in Tape & Reel SQA48A NOPB DS100BR410SQX 48-pin LLP (7mm X 7mm X 0.8mm, 0.5mm pitch) 2500 in Tape & Reel SQA48A NOPB www.ti.com 2 DS100BR410
Pin Name Pin # I/O, Type Description HIGH SPEED DIFFERENTIAL I/O IN_0+ IN_0– I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating resistor connects IN_0+ to IN_0-. IN_1+ IN_1– I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating resistor connects IN_1+ to IN_1-. IN_2+ IN_2– I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating resistor connects IN_2+ to IN_2-. IN_3+ IN_3– I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating resistor connects IN_3+ to IN_3-. OUT_0+ OUT_0– O, CML Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω terminating resistor connects OUT_0+ to OUT_0-. OUT_1+ OUT_1– O, CML Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω terminating resistor connects OUT_1+ to OUT_1-. OUT_2+ OUT_2– O, CML Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω terminating resistor connects OUT_2+ to OUT_2-. OUT_3+ OUT_3– O, CML Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω terminating resistor connects OUT_3+ to OUT_3-. 2.5V LVCMOS CONTROL PINS BST_2 BST_1 BST_0 I, LVCMOS BST_2, BST_1, and BST_0 select the equalizer boost level for all channels. BST_2 and BST_1 are internally pulled high. BST_0 is internally pulled low. See Table 1 EN0 EN1 EN2 EN3 I, LVCMOS Enable channel n input. When held High, normal operation is selected. When held Low, standby mode is selected. EN is internally pulled High. PIN_MODE 21 I, LVCMOS Pin mode control input. When held High, device is in Pin control mode. When held Low, device is in SMBus Control Mode PIN_MODE is internally pulled High. SD0 SD1 SD2 SD3 O, LVCMOS Signal detect n output. Output is High when signal is detected. Output is Low when signal is NOT detected. OOB_DIS 47 I, LVCMOS OOB disable control input. When held High, OOB is disabled. When held Low, OOB is enabled. Out Of Band (OOB) for SATA/SAS applications is active. OOB_DIS is internally pulled Low. Analog Input Pins (4–level Inputs) VOD_SEL 19 I, analog Differential Output Voltage Select Input Tie to VDD, VOD = 1.2 Vp-p Leave Open, VOD = 1.0 Vp-p Resistor (20 kΩ) to GND, VOD = 800 mVp-p Tie to GND, VOD = 600 mVp-p DE_SEL 20 I, analog De-Emphasis Select Input Tie to VDD = -9 dB Leave Open = -6 dB Resistor (20 kΩ) to GND = -3 dB Tie to GND = 0 dB 3 www.ti.com DS100BR410
Pin Name Pin # I/O, Type Description SERIAL MANAGEMENT BUS (SMBus) INTERFACE SDA 18 I/O, LVCMOS Data Input / Open Drain Output External pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant. SDC 17 I, LVCMOS Clock Input Pin is 3.3 V LVCMOS tolerant. CS 16 I, LVCMOS Chip Select When high, access to the SMBus registers are enabled. When low, access to the SMBus registers are disabled. Please refer to “SMBus configuration Registers” section for detail information. Pin is 3.3 V LVCMOS tolerant. POWER VDD 3, 6, 7, 10, 13, 15, 46 Power VDD = 2.5 V ± 5% GND 22, 24, 27, 30, 31, 34 Power Ground reference. DAP PAD Power Ground reference. The exposed pad at the center of the package must be connected to ground plane of the board with at least 4 via to lower the ground impedance and improve the thermal performance of the package. RES 48 NC Reserved – Do not connect Note: I = Input O = Output, LVCMOS pins are 2.5 V levels only, only SMBus pins SDA, SDC and CS are 3.3V tolerant. www.ti.com 4 DS100BR410
Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) -0.5V to +2.75V
2.5 I/O Voltage
(LVCMOS and Analog Input) -0.5V to +2.75V
3.3 LVCMOS I/O Voltage
(SDA, SDC, CS) -0.5V to +4.0V CML Input Voltage (IN_n+/-) -0.5V to +2.75V CML Output Voltage (OUT_n+/-) -0.5V to +2.75V Junction Temperature +150°C Storage Temperature -65°C to +150°C ESD Rating HBM, STD - JESD22-A114F ≥7 kV MM, STD - JESD22-A115-A ≥200 V CDM, STD - JESD22-C101-D ≥1250 V Thermal Resistance θJA, No Airflow, 4 layer JEDEC, 9 thermal vias 27.6 °C/W For soldering specifications: see product folder at www.national.com www.national.com/ms/MS/MS-SOLDERING.pdf Recommended Operating Conditions Min Typ Max Units Supply Voltage VDD to GND 2.375 2.5 2.625 V Ambient Temperature -40 25 +85 °C
Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified. (Note 2) Symbol Parameter Conditions Min Typ Max Units POWER PD Power Supply Consumption Device Output Enabled (EN[3:0] = High), VOD_SEL = open (1.0 Vp-p) 220 275 mW Device Output Disable (EN[3:0] = Low) 25 40 mW PSNT Supply Noise Tolerance (Note 4) 50 Hz to 100 Hz 100 mVP-P
100 Hz to 10 MHz 40 mVP-P
10 MHz to 5.0 GHz 10 mVP-P
2.5 LVCMOS DC SPECIFICATIONS
VIH High Level Input Voltage 1.75 VDD V VIL Low Level Input Voltage -0.3 0.7 V VOH High Level Output Voltage IOH = -3mA 2.0 V VOL Low Level Output Voltage IOL = 3mA 0.4 V IIN Input Leakage Current VIN = VDD +10 μA VIN = GND -10 μA IIN-P Input Leakage Current with Internal Pull-Down/Up Resistors VIN = VDD, with internal pull-down resistors +65 μA VIN = GND, with internal pull-up resistors -50 μA SIGNAL DETECT SDH Signal Detect ON Threshold Level Default input signal level to assert SD pin, 10.3125 Gbps 130 mVp-p SDL Signal Detect OFF Threshold Level Default input signal level to de- assert SD, 10.3125 Gbps 60 mVp-p 5 www.ti.com DS100BR410
Symbol Parameter Conditions Min Typ Max Units CML RECEIVER INPUTS (IN_n+, IN_n-) VTX Source Transmit Launch Signal Level (IN diff) AC-Coupled Requirement, Differential measurement at point A. Figure 1 600 1600 mVP-P RLI Differential Input Return Loss - SDD11
100 MHz – 6 GHz, with fixture’s
CML DRIVER OUTPUTS (OUT_n+, OUT_n-) VOD Output Differential Voltage Level (Note 6), Figure 2 Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled, VOD_SEL = open (1.0 Vp-p), DE_SEL = GND 750 970 1150 mVP-P Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled, VOD_SEL = VDD (1.2 Vp-p), DE_SEL = GND 1140 mVP-P VOD_DE De-Emphasis Levels (Note 6, Note 7) DE_SEL = 20kΩ to GND, VOD_SEL = VDD (1.2 Vp-p) -3 dB DE_SEL = open, VOD_SEL = VDD (1.2 Vp-p) -6 dB DE_SEL = VDD, VOD_SEL = VDD (1.2 Vp-p) -9 dB tR, tF Transition Time 20% to 80% of differential output voltage, measured within 1” from output pins. Figure 2 30 38 45 ps RLO Differential Output Return Loss - SDD22 effect de-embedded. IN+ = static high. -15 dB tPLHD Differential Low to High Propagation Delay Propagation delay measurement at 50% crossing between input to output, 100 Mbps. Figure 3 240 ps tPHLD Differential High to Low Propagation Delay 240 ps tCCSK Inter Pair Channel to Channel Skew Difference in 50% crossing between channels 7 ps tPPSK Part to Part Output Skew Difference in 50% crossing between outputs 20 ps RJ Random Jitter VTX = 1.0 Vp-p, BST_[2:0] = 000, (Note 6, Note 8) 0.3 psrms www.ti.com 6 DS100BR410
Symbol Parameter Conditions Min Typ Max Units EQUALIZATION DJ1 Residual Deterministic Jitter at 10.3125 Gbps VTX = 1.0 VP-P, 12 meter 30 AWG cable, EQ = 03F'h (BST[2:0] = 111), PRBS-7 (27-1) pattern. (Note 5) 0.10 0.22 UIP-P DJ2 Residual Deterministic Jitter at 6.0 Gbps VTX = 1.0 VP-P, 12 meter 30 AWG cable, EQ = 07F'h, PRBS-7 (27-1) pattern. (Note 5) 0.07 0.12 UIP-P SIGNAL DETECT and ENABLE TIMING tZISD Input OFF to ON detect — SD Output High Response Time Response time measurement at VIN to SD output, VIN = 800 mVP-P,
100 Mbps, 40” of 6 mil microstrip
FR4. Figure 4 35 ns tIZSD Input ON to OFF detect — SD Output Low Response Time 400 ns tOZOED EN High to Output ON Response Time Response time measurement at EN input to VO, VIN = 800 mVP-P, FR4. Figure 5 150 ns tZOED EN Low to Output OFF Response Time 5 ns Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 2: Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 3: Allowed supply noise (mVP-P sine wave) under typical conditions. Note 4: Specification is guaranteed by characterization at optimal boost setting and is not tested in production. Note 5: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1). Random jitter is removed through the use of averaging or similar means. Note 6: Measured with clock-like {11111 00000} pattern. Note 7: The de-emphasis level of −3 dB, −6 dB, −9 dB are for VOD = 1.2 Vp-p. At lower VOD level, the de-emphasis levels are reduced. Note 8: Random jitter contributed by the equalizer is defined as sqrt (JOUT2 – JIN2). JOUT is the random jitter at equalizer outputs in ps-rms, see point C of Figure 1; JIN is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 1. 7 www.ti.com DS100BR410
Electrical Characteristics — Serial Management Bus Interface Over recommended operating supply and temperature ranges unless other specified. (Note 2) Symbol Parameter Conditions Min Typ Max Units SERIAL BUS INTERFACE DC SPECIFICATIONS VIL Data, Clock Input Low Voltage 0.8 V VIH Data, Clock Input High Voltage 2.1 VDD V IPULLUP Current Through Pull-Up Resistor or Current Source High Power Specification 4 mA VDD Nominal Bus Voltage 2.375 3.6 V ILEAK-Bus Input Leakage Per Bus Segment (Note 11) -200 +200 µA ILEAK-Pin Input Leakage Per Device Pin -15 µA CI Capacitance for SDA and SDC (Note 11, Note 12) 10 pF RTERM External Termination Resistance pull to VDD = 2.5V ± 5% OR 3.3V ± 10% VDD3.3, (Note 11, Note 12) 2000 Ω VDD2.5, (Note 11, Note 12) 1000 Ω SERIAL BUS INTERFACE TIMING SPECIFICATIONS – (See Figure 6) FSMB Bus Operating Frequency 10 100 kHz TBUF Bus Free Time Between Stop and Start Condition 4.7 µs THD:STA Hold time after (Repeated) Start Condition. After this period, the first clock is generated. At IPULLUP, Max 4.0 µs TSU:STA Repeated Start Condition Setup Time 4.7 µs TSU:STO Stop Condition Setup Time 4.0 µs THD:DAT Data Hold Time 300 ns TSU:DAT Data Setup Time 250 ns TLOW Clock Low Period 4.7 µs THIGH Clock High Period 4.0 50 µs tF Clock/Data Fall Time 300 ns tR Clock/Data Rise Time 1000 ns tPOR Time in which a device must be operational after power-on reset 500 ms Note 9: Recommended value. Parameter not tested in production. Note 10: Recommended maximum capacitance load per bus segment is 400pF. Note 11: Maximum termination voltage should be identical to the device supply voltage. AC specifications for details. www.ti.com 8 DS100BR410
analog input DE_SEL pin or via SMBus (see Table 4). TABLE 3. DE_SEL Pin Configuration the SMBus port allowing access to the configuration registers. thus the 8-bit value is 1010 1100'b or AC'h. ing the time when SDC is High. indicates a message START condition. indicates a message STOP condition. the bus will transfer to the IDLE state.
- The Host (Master) selects the device by driving its
SMBus Chip Select (CS) signal High.
- The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
- The Device (Slave) drives the ACK bit (“0”).
- The Host drives the 8-bit Register Address.
- The Device drives an ACK bit (“0”).
- The Host drive the 8-bit data byte.
- The Device drives an ACK bit (“0”).
- The Host drives a STOP condition.
- The Host de-selects the device by driving its SMBus CS
communication with other SMBus devices may now occur.
- The Host (Master) selects the device by driving its
SMBus Chip Select (CS) signal High.
- The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
- The Device (Slave) drives the ACK bit (“0”).
- The Host drives the 8-bit Register Address.
- The Device drives an ACK bit (“0”).
- The Host drives a START condition.
- The Host drives the 7-bit SMBus Address, and a “1”
- The Device drives an ACK bit “0”.
- The Device drives the 8-bit data value (register contents).
- The Host drives a NACK bit “1”indicating end of the
- The Host drives a STOP condition.
- The Host de-selects the device by driving its SMBus CS
communication with other SMBus devices may now occur. to Table 4 for additional information.
TABLE 4. DS100BR410 Register Map
00 Device ID 7:4 Device ID R 0010 Device ID Value
3 SD_CH3 R 1: Signal detected on CH3
2 SD_CH2 R 1: Signal detected on CH2
1 SD_CH1 R 1: Signal detected on CH1
0 SD_CH0 R 1: Signal detected on CH0
01 Status Register
7 Reserved R
6 OOB_DIS R OOB_DIS
5 Reserved R
4 EN R EN
0 Boost_bit[8] R Boost_bit[8]
02 Status Register
03 Status Register
04 Reserved 7:0 Reserved R 00
05 Signal Detect
06 Signal Detect
(hex) REG Name Bit(s) Field Type Default (binary) Description
07 Port/Channel
7:6 Reserved R/W 00 5:4 Port/Channel Select for Status R/W 00 Select port/channel [1:0] to report status in REG_01 to REG_03 00 = port0 (CH0) 01 = port1 (CH1) 10 = port2 (CH2) 11 = port3 (CH3) 3:1 Reserved R/W 000
0 SMBUS Channel EN and
R/W 0 Channel EN and EQ Boost through pins or smbus REG_13 to REG_1A 0 = Channel EN[3:0] and EQ BST[2:0] boost set by external pins 1 = Allow channel EN and EQ boost to be set by SMBus Register bits: REG_13 to REG_1A
08 Driver VOD
7 Reserved R/W 0
6:4 Reserved R/W 111 3:2 VOD Control R/W 10 00 = 0.6 Vp-p 01 = 0.8 Vp-p 10 = 1.0 Vp-p 11 = 1.2 Vp-p 1:0 Reserved R/W 00 09 – 10 Reserved 7:0 Reserved R/W 00000000
11 De-Emphasis
7:6 DEM_CH3 R/W 00 00 = 0 dB 01 = -3 dB 10 = -6 dB 11 = -9 dB 5:4 DEM_CH2 R/W 00 3:2 DEM_CH1 R/W 00 1:0 DEM_CH0 R/W 00
12 OOB Signal
7:3 Reserved R/W 00000 2:1 Reserved R/W 11
0 OOB Signal Detect Control R/W 0 0 = OOB signal detect enabled
1 = OOB signal detect disabled
13 Channel 3
7:5 Reserved R/W 000
4 Channel Enable R/W 1 0 = Disabled
1 = Enabled 3:1 Reserved R/W 000
0 Boost[8] R/W 0 See Table 5
14 EQ Control
7:0 Boost[7:0] R/W 00000000 See Table 5
15 Channel 2
7:5 Reserved R/W 000 1 = Enabled 3:1 Reserved R/W 000
16 EQ Control
7:0 Boost[7:0] R/W 00000000 See Table 5
17 Channel 1
7:5 Reserved R/W 000 1 = Enabled 3:1 Reserved R/W 000
18 EQ Control
7:0 Boost[7:0] R/W 00000000 See Table 5 www.ti.com 14 DS100BR410
19 Channel 0
TABLE 5. Boost / EQ SMBus Register: 16 levels - recommended settings
The DS100BR410 is a high performance circuit capable of delivering excellent performance up to 10.3125 Gbps. Careful attention must be paid to the details associated with high- speed design as well as providing a clean power supply. Refer to the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity design is- sues. UNUSED CHANNEL It is recommended to disable the unused channel (EN[3:0] = LOW). The power consumption of the device is reduced when the channel is disabled. PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS The high speed CML inputs and outputs must have a con- trolled differential impedance of 100Ω. It is preferable to route differential lines exclusively on one layer of the board, partic- ularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Route the differential signals away from other signals and noise sources on the printed circuit board. See AN-1187 for additional information on LLP packages. Impedance discontinuities at the differential via can be mini- mized or eliminated by increasing the swell around each via hole. To further improve the signal quality, a ground via placed close to the signal via for a low inductance return current path is recommended. When the via structure is associated with stripline trace and a thick board, further optimization such as back drilling is often used to reduce the high frequency effects of via stubs on the signal path. To minimize cross-talk cou- pling, it is recommended to have >3X gap spacing between the differential pairs. For example, if the trace width is 5 mils with 5 mils spacing – 100 Ω differential impedance (closely coupled). The gap spacing between the differential pairs should be >15 mils. POWER SUPPLY BYPASSING Two approaches are recommended to ensure that the DS100BR410 is provided with an adequate power supply. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Sec- ond, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.1uF or 0.01 μF by- pass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to the DS100BR410. Smaller body size capacitors can help facili- tate proper component placement. Additionally, three capac- itors with capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic. www.ti.com 16 DS100BR410
Physical Dimensions inches (millimeters) unless otherwise noted 48-pin LLP Package (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch) 19 www.ti.com DS100BR410
DS100BR410 Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and De-Emphasis Driver www.ti.com
Texas InstrumentsIncorporatedand itssubsidiaries(TI)reservetherighttomake corrections,modifications,enhancements,improvements, and otherchanges toitsproductsand servicesatany timeand todiscontinueany productorservicewithoutnotice.Customersshould obtainthelatestrelevantinformationbeforeplacingordersand shouldverifythatsuch informationiscurrentand complete.Allproductsare soldsubjecttoTI’s termsand conditionsofsalesuppliedatthetimeoforderacknowledgment. TIwarrantsperformanceofitshardwareproductstothespecificationsapplicableatthetimeofsaleinaccordancewithTI’s standard warranty.Testingand otherqualitycontroltechniquesareused totheextentTIdeems necessarytosupportthiswarranty.Exceptwhere mandated by governmentrequirements,testingofallparametersofeach productisnotnecessarilyperformed. TIassumes no liabilityforapplicationsassistanceorcustomerproductdesign.Customersareresponsiblefortheirproductsand applicationsusingTIcomponents.To minimizetherisksassociatedwithcustomerproductsand applications,customersshouldprovide adequatedesignand operatingsafeguards. TIdoes notwarrantorrepresentthatany license,eitherexpressorimplied,isgrantedunderany TIpatentright,copyright,mask work right, orotherTIintellectualpropertyrightrelatingtoany combination,machine,orprocessinwhichTIproductsorservicesareused.Information publishedby TIregardingthird-partyproductsorservicesdoes notconstitutea licensefromTItouse such productsorservicesora warrantyorendorsementthereof.Use ofsuch informationmay requirea licensefroma thirdpartyunderthepatentsorotherintellectual propertyofthethirdparty,ora licensefromTIunderthepatentsorotherintellectualpropertyofTI. ReproductionofTIinformationinTIdatabooks ordatasheetsispermissibleonlyifreproductioniswithoutalterationand isaccompanied by allassociatedwarranties,conditions,limitations,and notices.Reproductionofthisinformationwithalterationisan unfairand deceptive businesspractice.TIisnotresponsibleorliableforsuch altereddocumentation.Informationofthirdpartiesmay be subjecttoadditional restrictions. ResaleofTIproductsorserviceswithstatementsdifferentfromorbeyond theparametersstatedby TIforthatproductorservicevoidsall expressand any impliedwarrantiesfortheassociatedTIproductorserviceand isan unfairand deceptivebusinesspractice.TIisnot responsibleorliableforany such statements. TIproductsarenotauthorizedforuse insafety-criticalapplications(suchas lifesupport)where a failureoftheTIproductwouldreasonably be expectedtocause severepersonalinjuryordeath,unlessofficersofthepartieshave executedan agreementspecificallygoverning such use.Buyersrepresentthattheyhave allnecessaryexpertiseinthesafetyand regulatoryramificationsoftheirapplications,and acknowledgeand agreethattheyaresolelyresponsibleforalllegal,regulatoryand safety-relatedrequirementsconcerningtheirproducts and any use ofTIproductsinsuch safety-criticalapplications,notwithstandingany applications-relatedinformationorsupportthatmay be providedby TI.Further,Buyersmust fullyindemnifyTIand itsrepresentativesagainstany damages arisingoutoftheuse ofTIproductsin such safety-criticalapplications. TIproductsareneitherdesignednorintendedforuse inmilitary/aerospaceapplicationsorenvironmentsunlesstheTIproductsare specificallydesignatedby TIas military-gradeor"enhanced plastic." Onlyproductsdesignatedby TIas military-grademeet military specifications.Buyersacknowledgeand agreethatany such use ofTIproductswhichTIhas notdesignatedas military-gradeissolelyat theBuyer's risk,and thattheyaresolelyresponsibleforcompliancewithalllegaland regulatoryrequirementsinconnectionwithsuch use. TIproductsareneitherdesignednorintendedforuse inautomotiveapplicationsorenvironmentsunlessthespecificTIproductsare designatedby TIas compliantwithISO/TS 16949 requirements.Buyersacknowledgeand agreethat,iftheyuse any non-designated productsinautomotiveapplications,TIwillnotbe responsibleforany failuretomeet such requirements. FollowingareURLs where you can obtaininformationon otherTexas Instrumentsproductsand applicationsolutions: Products Applications Audio www.ti.com/audio Automotiveand Transportationwww.ti.com/automotive Amplifiers amplifier.ti.com Communicationsand Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP ® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energyand Lighting www.ti.com/energy Clocksand Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space,Avionicsand Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Videoand Imaging www.ti.com/video RFID www.ti-rfid.com OMAP MobileProcessors www.ti.com/omap WirelessConnectivity www.ti.com/wirelessconnectivity TIE2E Community Home Page e2e.ti.com MailingAddress:Texas Instruments,PostOfficeBox 655303,Dallas,Texas 75265 Copyright© 2012,Texas InstrumentsIncorporated