DS100BR111SQ/NOPB

Texas Instruments

Ultra Low Power 10.3 Gbps 1-Lane Repeater with Input Equalization and Output De-Emphasis

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EQ[1:0] OUT+ OUT- 50/c3a50/c3a VOD SMBus LOSChannel Status and Control SD_TH TX_DIS MODE Line Card DS100BR111 1x10G ASIC FPGA 1x10G 1 x SFP+ Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community DS100BR111 SNLS338F –JANUARY 2011–REVISED NOVEMBER 2014 DS100BR111UltraLowPower10.3Gbps1-LaneRepeater withInputEqualizationandOutputDe-Emphasis

1 Features 3 Description

The DS100BR111 is an extremely low power, high 1• Two Channel Repeaters for up to 10.3 Gbps performance repeater designed to support serial links– DS100BR210 : 2x Unidirectional Channels with data rates up to 10.3 Gbps. The DS100BR111 – DS100BR111 : 1x Bidirectional Lane pinout is configured as one bidirectional lane (one transmit, one receive channel). The DS100BR111• 10G-KR Bi-directional Interface Compatibility inputs feature a powerful 4-stage continuous time– Allows for Back-channel Communication and linear equalizer (CTLE) to provide a boost of up toTraining +36 dB at 5 GHz and open an input eye that is

Low 65 mW/channel (Typical) Power completely closed due to inter-symbol interference Consumption, with Option to Power Down Unused (ISI) induced by the interconnect mediums such as board traces or twin-axial copper cables. TheChannels transmitter features a programmable output de-• Advanced Signal Conditioning Features emphasis driver with up to -12 dB and can drive– Receive Equalization up to +36 dB output voltage levels from 700 mVp-p to 1300 mVp-p. – Transmit De-emphasis up to -12 dB When configured as a 10G-KR repeater, the – Transmit VOD Control: 700 to 1300 mVp-p DS100BR111 allows the KR host and the end point to optimize the full link by adjusting transmit and receive– Low Residual DJ at 10.3 Gbps equalizer coefficients using back-channel• Programmable Via Pin Selection, EEPROM, or communication techniques specified by the 802.3apSMBus Interface Ethernet standard.• Single Supply Voltage: 2.5 V or 3.3 V The programmable settings can be applied via pin• Flow-thru Pinout in 4 mm × 4 mm 24-pin Leadless control, SMBus protocol, or an external EEPROM. InWQFN Package the EEPROM mode, the configuration information is
5 kV HBM ESD Rating automatically loaded on power up, thereby eliminating the need for an external microprocessor or software• -40 to 85°C Operating Temperature Range driver.

2 Applications Device Information(1)

High-speed Active Copper Cable Modules and PART NUMBER PACKAGE BODY SIZE (NOM) FR-4 Backplane in Communication Systems DS100BR111 WQFN (24) 4.00 mm x 4.00 mm
10GE, 10G-KR, FC, SAS, SATA 3/6 Gbps (with (1) For all available packages, see the orderable addendum atOOB Detection), InfiniBand, CPRI, RXAUI and the end of the datasheet. many others

4 Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SNLS338F –JANUARY 2011–REVISED NOVEMBER 2014 www.ti.com Table of Contents

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (February 2013) to Revision F Page

Added, updated, or renamed the following sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and

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VDD_SEL VIN INB+ INB- LOS VOD_SEL / READEN MODE / DONE SD_TH OUTA+ OUTA- OUTB- SMBUS AND CONTROL VDD EQB1/AD2 ENSMB SCL/DEMB EQB0/AD3 SDA/DEMA VDD TX_DIS AD1/EQA1 AD0/EQA0 DS100BR111 www.ti.com SNLS338F –JANUARY 2011–REVISED NOVEMBER 2014

6 Pin Configuration and Functions

(1) The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through multiple (minimum of 4) vias to ensure optimal electrical and thermal performance. Pin Functions(1) PIN I/O, TYPE DESCRIPTION NAME NUMBER DIFFERENTIAL HIGH SPEED I/O's Inverting and non-inverting CML differential inputs to the equalizer. On-chip 50 ΩINA+, INA- , 24, 23 I, CML termination resistors connect both INx+ and INx- to VDD. Compatible with AC coupledINB+, INB- 11, 12 CML inputs. OUTA+, OUTA-, 7, 8 Inverting and non-inverting 50 Ω driver outputs with de-emphasis. Compatible with ACO, CMLOUTB+, OUTB- 20, 19 coupled CML inputs. CONTROL PINS System Management Bus (SMBus) Enable Pin I, 4-LEVEL, High = Register Access SMBus Slave ModeENSMB 3 LVCMOS Float = Read External EEPROM (SMBus Master Mode) Tie 1 kΩ to GND = Pin Mode (1) LVCMOS inputs without the “Float”conditions must be driven to a logic low or high at all times or operation is not ensured. Unless the "Float" level is desired, 4-Level input pins require a minimum 1 kΩ resistor to GND, VDD (in 2.5 V mode), or VIN (in 3.3 V mode). Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DS100BR111

SNLS338F –JANUARY 2011–REVISED NOVEMBER 2014 www.ti.com Pin Functions(1) (continued) PIN I/O, TYPE DESCRIPTION NAME NUMBER ENSMB = Float or 1 (SMBus MODES) I, 2-LEVEL, Clock output when loading EEPROM configuration, reverting to SMBus clock input LVCMOS, when EEPROM load is complete (ALL_DONE = 0).SCL 5 O, Open External 2 kΩ to 5 kΩ pull-up resistor to VDD (2.5 V mode) or VIN (3.3 V mode) Drain recommended as per SMBus interface standards(2) I, 2-LEVEL, In both SMBus Modes, this pin is the SMBus data I/O. Data input or open drain output. LVCMOS, External 2 kΩ to 5 kΩ pull-up resistor to VDD (2.5 V mode) or VIN (3.3 V mode)SDA 4 O, Open recommended as per SMBus interface standards(2) Drain ENSMB Master or Slave mode I, 4-LEVEL, SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBusAD0-AD3 10, 9, 2, 1 LVCMOS slave address inputs. There are 16 addresses supported by these pins. Pins must be tied Low or High when used to define the device SMBus address. (3) ENSMB = Float: When using SMBus Master Mode, a logic low on this pin starts the load from the external EEPROM.I, 2-LEVEL,READEN 17 ENSMB = 1: When using SMBus Slave Mode, the VOD_SEL/READEN pin must beLVCMOS tied Low for the AD[3:0] to be active. If this pin is tied High or left floating, an address of 0xB0 will be used for the DS100BR111. When using an External EEPROM (ENSMB = Float), Valid Register Load Status O, 2-LEVEL, OutputDONE 18 LVCMOS High = External EEPROM load failed or incomplete Low = External EEPROM load passed ENSMB = 0 (PIN MODE) EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. EQA[1:0] controls the A channel, and EQB[1:0] controls the B channel. The pins are only active EQA0, EQA1 10, 9 I, 4-LEVEL, when ENSMB = 0. EQB0, EQB1 1, 2 LVCMOS When ENSMB = 1, the SMBus registers provide independent control of each channel, and the EQB0/B1 pins are converted to SMBus AD2/AD3 inputs. See Table 3 for additional information. DEMA and DEMB control the level of de-emphasis for the output driver when in 10G mode. DEMA controls the A channel, and DEMB controls the B channel. The pins are I, 4-LEVEL, only active when ENSMB = 0.DEMA, DEMB 4, 5 LVCMOS When ENSMB = 1, the SMBus registers provide independent control of each channel, and the DEM pins are converted to SMBus SCL and SDA pins. See Table 4 for additional information. VOD Select High = 10G-KR Mode (VOD = 1.1 Vpp or 1.3 Vpp) I, 4-LEVEL, Float = (VOD = 1.0 Vpp)VOD_SEL 17 LVCMOS 20 kΩ to GND = (VOD = 1.2 Vpp) 1 kΩ to GND = (VOD = 700 mVpp) See (3)(4) for additional notes. See Table 2 for additional information. Controls Device Mode of Operation High= 10GbE Mode, Continuous Talk (Output Always On) I, 4-LEVEL, Float = 10G-KR Mode, Slow OOBMODE 18 LVCMOS 20 kΩ to GND = eSATA Mode, Fast OOB, Auto Low Power on 100 µs of inactivity. SD stays active. 1 kΩ to GND = SAS Mode, Fast OOB (3) Setting VOD_SEL = High in SMBus Mode will force the SMBus Address = 0xB0 (4) DS100BR111 OUTA is limited to 700 mVpp in pin mode.

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www.ti.com SNLS338F –JANUARY 2011–REVISED NOVEMBER 2014 Pin Functions(1) (continued) PIN I/O, TYPE DESCRIPTION NAME NUMBER CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS) I, 2-LEVEL, High = OUTA Enabled, OUTB DisabledTX_DIS 6 LVCMOS Low = OUTA and OUTB Enabled O, Open Indicates Loss of Signal (Default is LOS on INA). Can be modified via SMBusLOS 13 Drain registers. The SD_TH pin controls LOS threshold setting Assert (mVpp), Deassert (mVpp) I, 4-LEVEL, High = 190 mVpp, 130 mVppSD_TH 14 LVCMOS Float = 180 mVpp, 110 mVpp (Default) 20 kΩ to GND = 160 mVpp, 100 mVpp 1 kΩ to GND = 210 mVpp, 150 mVpp(5) Enables the 3.3 V to 2.5 V internal regulator VDD_SEL 16 I, FLOAT Low = 3.3 V Operation Float = 2.5 V Operation POWER Power supply pins When in 2.5 V mode, connect to 2.5 V supply. VDD 21, 22 Power When in 3.3 V mode, do not connect to any supply voltage. Should be used to attach external decoupling to device, 100 nF recommended. See Power Supply Recommendations for additional information. VIN = 3.3 V ± 10% (input to internal LDO regulator) VIN 15 Power When in 2.5 V mode, VIN pin must be left floating. See Power Supply Recommendations for additional information. GND DAP Power Ground pad (DAP - die attach pad). (5) Using values less than the default level can extend the time required to detect LOS and are not recommended. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DS100BR111

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7 Specifications

7.1 Absolute Maximum Ratings(1)(2)

Supply Voltage (VDD) -0.5 +2.75 V Supply Voltage (VIN) -0.5 +4.0 V LVCMOS Input/Output Voltage -0.5 +4.0 V CML Input Voltage -0.5 (VDD+0.5) V CML Input Current -30 +30 mA Junction Temperature 125 °C (1) “Absolute Maximum Ratings”indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. (2) For soldering specifications, see SNOA549.

7.2 Handling Ratings

Tstg Storage Temperature Range -40 +125 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all -5 5 kVpins(1) V(ESD) Electrostatic Discharge Machine model (MM), STD - JESD22-A115-A 100 V Charged device model (CDM), per JEDEC specification 1250 VJESD22-C101, all pins(2) (1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions(1)

Supply Voltage (2.5 V mode) 2.375 2.5 2.625 V Supply Voltage (3.3 V mode) 3.0 3.3 3.6 V Ambient Temperature -40 25 +85 °C SMBus (SDA, SCL) 3.6 V (1) The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only.

7.4 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY CURRENT TX_DIS = Low, EQ = ON 50 63VOD_SEL = Float (1000 mVpp) Auto Low Power Mode IDD Supply Current TX_DIS = Low, MODE = 20 kΩ mA12 15VID CHA and CHB = 0.0 V VOD_SEL = Float (1000 mVpp) TX_DIS = High 25 35 LVCMOS DC SPECIFICATIONS High Level Input Voltage,VIH25 2.5 V Supply Mode 2.0 VDD V2-Level LVCMOS High Level Input Voltage,VIH33 3.3 V Supply Mode 2.0 VIN V2-Level LVCMOS Low Level Input Voltage,VIL GND 0.7 V2-Level LVCMOS

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www.ti.com SNLS338F –JANUARY 2011–REVISED NOVEMBER 2014 Electrical Characteristics (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High Level Output Voltage IOH = -4.0 mA (1) 2.0 V VOL Low Level Output Voltage IOL = 4.0 mA 0.4 V Vinput = 0 V or VDD -15 +15VDD_SEL = Float IIN Input Leakage Current µA Vinput = 0 V or VIN -15 +15VDD_SEL = Low Vinput = 0 V or VDD - 0.05 V Input Leakage Current VDD_SEL = FloatIIN-P -160 +80 µA4-Level Input (2) Vinput = 0 V or VIN - 0.05 V VDD_SEL = Low CML RECEIVER INPUTS Source Transmit Launch Default power-up conditionsVTX 190 800 1600 mVp-pDifferential Signal Level ENSMB = 0 or 1 SDD11 @ 4.1 GHz -12 RLRX-IN RX return loss SDD11 @ 11.1 GHz -8 dB SCD11 @ 11.1 GHz -10 HIGH SPEED TRANSMITTER OUTPUTS OUT+ and OUT- AC coupled and terminated by 50 Ω to GNDVOD1 Output Voltage Differential Swing 500 650 800VOD_SEL = Low (700 mVpp setting) DE = Low OUT+ and OUT- AC coupled and terminated by 50 Ω to GNDVOD2 Output Voltage Differential Swing 800 1000 1100VOD_SEL = Float (1000 mVpp setting) mVp-p DE = Low OUT+ and OUT- AC coupled and terminated by 50 Ω to GND VOD3 Output Voltage Differential Swing VOD_SEL = 20 kΩ to GND (1200 950 1150 1350 mVpp) DE = Low OUT+ and OUT- AC coupled and terminated by 50 Ω to GNDVOD_DE1 De-Emphasis Levels -3 dBVOD_SEL = Float (1000 mVpp) DE = Float OUT+ and OUT- AC coupled and terminated by 50 Ω to GNDVOD_DE2 De-Emphasis Levels -6 dBVOD_SEL = Float (1000 mVpp) DE = 20 kΩ to GND (1) VOH only applies to the DONE pin; LOS, SCL, and SDA are open-drain outputs that have no internal pull-up capability. DONE is a full LVCMOS output with pull-up and pull-down capability. (2) Input is held to a maximum of 50 mV below VDD or VIN to simulate the use of a 1 kΩ resistor on the input. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DS100BR111

SNLS338F –JANUARY 2011–REVISED NOVEMBER 2014 www.ti.com Electrical Characteristics (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUT+ and OUT- AC coupled and terminated by 50 Ω to GNDVOD_DE3 De-Emphasis Levels -9 dBVOD_SEL = Float (1000 mVpp) DE = High AC Common Mode VoltageVCM-AC Output Common-Mode Voltage 4.5 mV (rms)DE = 0 dB, VOD ≤ 1000 mVpp Output DC Common-Mode DC Common Mode VoltageVCM-DC 0 1.1 1.9 VVoltage VIDLE TX IDLE Output Voltage VID = 0 mVp-p 30 mV SDD22 @ 4.1 GHz -13 SDD22 @ 11.1 GHz -9 RLTX-DIFF TX return loss dB SCC22 @ 2.5 GHz -22 SCC22 @ 11.1 GHz -10 Transmitter Termination DC, IFORCE = ± 100 µA (3) Delta_ZM 2.5%Mismatch TR/F Transmitter Rise and Fall Time Measurement points at 20% - 80% (4) 38 ps Measured at 50% crossingTPD Propagation Delay 230 psEQ = 0x00 TCCSK Channel to Channel Skew T = 25°C, VDD = 2.5 V 7 ps TPPSK Part to Part Skew T = 25°C, VDD = 2.5 V 20 ps TTX-IDLE-SET-TO- Max time to transition to idle after VIN = 1 Vpp, 10 Gbps 6.5 ns IDLE differential signal EQ = 0x00, DE = 0 dB TTX-IDLE-TO- Max time to transition to valid VIN = 1 Vpp, 10 Gbps 3.2 ns DIFF-DATA differential signal after idle EQ = 0x00, DE = 0 dB Active OOB timing distortion, TENV_DISTORT input active time vs. output active 3.3 ns time OUTPUT JITTER SPECIFICATIONS(5) RJ Random Jitter No Media 0.3 ps (rms) Source Amplitude = 700 mVpp, PRBS15 pattern, 10.3125 GbpsDJ1 Deterministic Jitter 0.09 UI VOD = Default, EQ = minimum, DE = 0 dB EQUALIZATION

10.3125 Gbps

8 meter 30AWG Cable on InputDJE1 Residual Deterministic Jitter 0.27 UISource = 700 mVpp, PRBS15 pattern EQ = 0x0F 30" 4-mil FR4 on InputsDJE2 Residual Deterministic Jitter 0.17 UISource = 700 mVpp, PRBS15 pattern EQ = 0x16 DE-EMPHASIS 10”4 mil stripline FR4 on Outputs DJD1 Residual Deterministic Jitter Source = 700 mVpp, PRBS15 pattern 0.13 UI EQ = Min, VOD = 1200 mVpp, DE = -3.5 dB (3) Force ±100 µA on output, measure ΔV on the Output and calculate impedance. Mismatch is the percentage difference of OUTn+ and OUTn- impedance driving the same logic state. (4) Default VOD used for testing. DE = -1.5 dB level used to compensate for fixture attenuation. (5) Typical jitter reported is determined by jitter decomposition software on the DSA8200 Oscilloscope.

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7.5 Electrical Characteristics — Serial Management Bus Interface

Over recommended operating supply and temperature ranges unless other specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SERIAL BUS INTERFACE DC SPECIFICATIONS(1) VIL Data, Clock Input Low Voltage 0.8 V VIH Data, Clock Input High Voltage 2.1 3.6 V IPULLUP Current Through Pull-Up Resistor High Power Specification 4 mAor Current Source VDD Nominal Bus Voltage 2.375 3.6 V ILEAK-Bus Input Leakage Per Bus Segment See (2) -200 +200 µA CI Capacitance for SDA and SCL See (2) (3) (4) 10 pF RTERM External Termination Resistance Pullup VDD = 3.3 V, See (2) (3) (5) 2000 Ω pull to VDD = 2.5V ± 5% OR 3.3V ± Pullup VDD = 2.5 V, See (2) (3) (5) 1000 Ω10% SERIAL BUS INTERFACE TIMING SPECIFICATIONS ENSMB = VDD (Slave Mode) 400 kHz FSMB Bus Operating Frequency ENSMB = Float (Master Mode) (1) 280 400 520 kHz Bus Free Time Between Stop andTBUF 1.3 µsStart Condition THD:STA Hold time after (Repeated) Start At IPULLUP, Max Condition. After this period, the 0.6 µs first clock is generated. TSU:STA Repeated Start Condition Setup 0.6 µsTime TSU:STO Stop Condition Setup Time 0.6 µs THD:DAT Data Hold Time 0 ns TSU:DAT Data Setup Time 100 ns TLOW Clock Low Period 1.3 µs THIGH Clock High Period See (6) 0.6 50 µs tF Clock/Data Fall Time See (6) 300 ns tR Clock/Data Rise Time See (6) 300 ns Time in which a device must betPOR See (4) (6) 500 msoperational after power-on reset (1) EEPROM interface requires 1 MHz capable EEPROM device. (2) Recommended value. (3) Recommended maximum capacitance load per bus segment is 400 pF. (4) Ensured by design and characterization. Parameter not tested in production. (5) Maximum termination voltage should be identical to the device supply voltage. SMBus common AC specifications for details.

7.6 Timing Requirements — LOS and ENABLE / DISABLE Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input IDLE to ActiveTLOS_OFF See (1) 0.035 µsRX_LOS response time Input Active to IDLETLOS_ON See (1) 0.4 µsRX_LOS response time TX Disable assert TimeTOFF See (1) 0.005 µsTX_DIS = High to Output OFF TX Disable negateTimeTON See (1) 0.150 µsTX_DIS = Low to Output ON Auto Low Power ExitTLP_EXIT See (1) 150 nsALP to Normal Operation Auto Low Power EnterTLP_ENTER See (1) 100 µsNormal Operation to Auto Low Power (1) Parameter not tested in production. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DS100BR111

Figure 1. Output Rise and Fall Transition Times Figure 2. Propagation Delay Timing Diagram Figure 3. Transmit Idle-Data and Data-Idle Response Time Figure 4. SMBus Timing Parameters

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7.7 Typical Characteristics

The following data was collected at 25°C. Figure 5. Supply Current vs. Output Voltage Setting Figure 6. Supply Current vs. Supply Voltage Figure 7. Output Voltage vs. Output Voltage Setting

EQA[1:0] ENSMB DEMA Digital Core and SMBus RegistersSCL SDA TX_DIS VIN VDD_SEL AD[3:0] Internal voltage regulator READEN DONE VOD_SEL INB+ INB- EQ OUTB+ OUTB- Term Pre- driverDriver EQB[1:0] ENSMB DEMB VOD_SEL B Channel Signal Detect Signal Detect Note: This diagram is representative of device signal flow only. DS100BR111 SNLS338F –JANUARY 2011–REVISED NOVEMBER 2014 www.ti.com

8 Detailed Description

8.1 Overview

The DS100BR111 is a high performance bidirectional 1-lane repeater optimized for 10G-KR and SAS/SATA operation, where its programmable equalization and de-emphasis compensate for lossy FR-4 printed circuit board backplanes or balanced cables. The DS100BR111 operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1), and SMBus Master Mode (ENSMB = Float) to load register information from external EEPROM. Each channel has a signal detector circuit that monitors the input signal amplitude. When the input signal level is below the detector's de-assert level, the output is disabled. When input signal level exceeds the detector's assert level, the output is enabled. The signal detector circuit is used to support the OOB signaling used in SAS and SATA.

8.2 Functional Block Diagram

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8.3 Feature Description

levels for each of the four input states are achieved as shown in Table 1. Table 1. 4–Level Control Pin Settings Table

Internal Threshold between 0 and R = 0.2 * VIN or VDD
Internal Threshold between R and F = 0.5 * VIN or VDD
Internal Threshold between F and 1 = 0.8 * VIN or VDD In order to minimize the startup current associated with the integrated 2.5-V regulator, the 1-kΩ pull-up / pull- down resistors are recommended. If several four level inputs require the same setting, it is possible to combine two or more 1-kΩ resistors into a single lower value resistor. As an example, combining two inputs with a single 500-Ω resistor is a valid way to save board space.

8.4 Device Functional Modes

8.4.1 Pin Control Mode

EEPROM is available to access the device via SMBus SDA and SCL lines.

8.4.2 SMBus Slave Mode

and SD_TH) remain active unless their respective registers are written to and the appropriate override bit is set.

Table 2. Signal Detect Threshold Level(1)

2 R 01 160 100

3 F (Default) 00 180 110

(1) Typical assert and de-assert levels were measured with VDD = 2.5 V, 25°C, and 010101 pattern at 8 Gbps.

8.4.3 SMBus Master Mode

waits indefinitely in an unknown state where access to the SMBus lines is not possible.

8.4.4 Signal Conditioning Settings

256 EQ levels and control both VOD and de-emphasis settings independently, SMBus register access must be

Table 3. Equalizer Settings

5 R 0 0000 0111 = 0x07 14 FR4 20 inch trace

6 R R 0001 0101 = 0x15 15 FR4 25 inch trace

7 R F 0000 1011 = 0x0B 17 FR4 25 inch trace

8 R 1 0000 1111 = 0x0F 19 7m 30 AWG Cable

9 F 0 0101 0101 = 0x55 20 FR4 30 inch trace

settings should be determined via simulation and prototype verification.

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Table 3. Equalizer Settings (continued)

11 F F 0010 1111 = 0x2F 25 10m 30 AWG Cable

12 F 1 0011 1111 = 0x3F 27

Table 4. De-Emphasis and Output Voltage Settings(1)

5 F 0 000 011 1000 0

7 F R 011 011 1000 -6

8 F 1 101 011 1000 -9

9 R 0 000 101 1200 -0

11 R R 011 101 1200 -6

12 R 1 101 101 1200 -9

OUTPUT A can be adjusted with SMBus register 0x23 [4:2] as shown in Table 9. communication using pin control.

8.5 Programming

8.5.1 System Management Bus (SMBus) and Configuration Registers

Table 5. Device Slave Address Bytes

0000 B0 58

0001 B2 59

0010 B4 5A

0011 B6 5B

0100 B8 5C

0101 BA 5D

0110 BC 5E

0111 BE 5F

1000 C0 60

1001 C2 61

1010 C4 62

1011 C6 63

1100 C8 64

1101 CA 65

1110 CC 66

1111 CE 67

SDA and SCL line. The resistor value can be from 2 kΩ to 5 kΩ depending on the voltage, loading, and speed.

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8.5.2 Transfer Of Data Via the SMBus

During normal operation, the data on SDA must be stable during the time when SCL is High. There are three unique states for the SMBus:

START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they are High for a total exceeding the maximum specification for tHIGH, then the bus will transfer to the IDLE state.

8.5.3 SMBus Transactions

The device supports WRITE and READ transactions. See Table 9 for register address, type (Read/Write, Read Only), default value, and function information.

8.5.4 Writing a Register

To write a register, the following protocol is used (see SMBus 2.0 specification): 1. The Host drives a START condition, the 7-bit SMBus address, and a “0”indicating a WRITE. 2. The Device (Slave) drives the ACK bit (“0”). 3. The Host drives the 8-bit Register Address. 4. The Device drives an ACK bit (“0”). 5. The Host drive the 8-bit data byte. 6. The Device drives an ACK bit (“0”). 7. The Host drives a STOP condition. Once the WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: DS100BR111

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8.5.5 Reading a Register

To read a register, the following protocol is used (see SMBus 2.0 specification): 1. The Host drives a START condition, the 7-bit SMBus address, and a “0”indicating a WRITE. 2. The Device (Slave) drives the ACK bit (“0”). 3. The Host drives the 8-bit Register Address. 4. The Device drives an ACK bit (“0”). 5. The Host drives a START condition. 6. The Host drives the 7-bit SMBus Address, and a “1”indicating a READ. 7. The Device drives an ACK bit “0”. 8. The Device drives the 8-bit data value (register contents). 9. The Host drives a NACK bit “1”indicating end of the READ transfer. 10. The Host drives a STOP condition. Once the READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. Please see Table 9 for more information.

8.5.6 EEPROM Programming

The DS100BR111 supports reading directly from an external EEPROM device by implementing SMBus Master mode. When used in SMBus Master mode, the DS100BR111 will read directly from a specific location in the external EEPROM. When designing a system that uses external EEPROM, the following guidelines should be followed:

Set the DS100BR111 in SMBus Master Mode. – ENSMB (Pin 3) = Float
The external EEPROM device must support 1 MHz operation.
The external EEPROM device address byte must be 0xA0.
Set the AD[3:0] inputs for SMBus address byte. When AD[3:0] = 0000'b, the device address byte is 0xB0.
The device address can be set with the use of the AD[3:0] input up to 16 different addresses. Use the example below to set each of the SMBus addresses. – AD[3:0] = 0001'b, the device address byte is 0xB2 – AD[3:0] = 0010'b, the device address byte is 0xB4 – AD[3:0] = 0011'b, the device address byte is 0xB6 – AD[3:0] = 0100'b, the device address byte is 0xB8
The master implementation in the DS100BR111 supports multiple devices reading from one EEPROM. When tying multiple devices to the SDA and SCL pins, use these guidelines: – Use adjacent SMBus addresses for the 4 devices – Use a pull-up resistor on SDA; value = 4.7 kΩ – Use a pull-up resistor on SCL: value = 4.7 kΩ – Daisy-chain READEN (Pin 17) and DONE (Pin 18) from one device to the next device in the sequence. 1. Tie READEN of the 1st device in the chain (U1) to GND 2. Tie DONE of U1 to READEN of U2 3. Tie DONE of U2 to READEN of U3 4. Tie DONE of U3 to READEN of U4 5. Optional: Tie DONE of U4 to a LED to show each of the devices have been loaded successfully

18 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Product Folder Links: DS100BR111

8.5.6.1 Master EEPROM Programming

Figure 8. Typical EEPROM Data Set The maximum EEPROM size supported is 8 kbits (1024 x 8 bits).

DONE
READEN When the DS100BR111 is powered up in SMBus Master mode, it reads its configuration from the external EEPROM when the READEN pin goes low. When the DS100BR111 is finished reading its configuration from the external EEPROM, it drives the DONE pin low. In applications where there is more than one DS100BR111 on the same SMBus, bus contention can result if more than one DS100BR111 tries to take control of the SMBus at the same time. The READEN and DONE pins prevent this bus contention. The system should be designed so that the READEN pin from one DS100BR111 in the system is driven low on power-up. This DS100BR111 will take command of the SMBus on power-up and will read its initial configuration from the external EEPROM. When the first DS100BR111 is finished reading its configuration, it will drive the DONE pin low. This pin should be Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: DS100BR111

Note: Set AD[3:0] of each DS100BR111 to unique SMBus Address. Figure 9. Typical Multi-device EEPROM Connection Diagram

8.5.6.2 EEPROM Address Mapping

map overview for a multi-device EEPROM address map is shown in Table 7.

20 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Table 6. Single Device with Default Value

Table 6. Single Device with Default Value (continued)

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24 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Table 7. Multi-Device EEPROM Address Map Overview(1)

0 CRC EN Address Map EEPROM > 256 Reserved COUNT[3] COUNT[2] COUNT[1] COUNT[0]

2 EE Burst[7] EE Burst[6] EE Burst[5] EE Burst[4] EE Burst[3] EE Burst[2] EE Burst[1] EE Burst[0]

(d) Note: Multiple DS100BR111 devices may point at the same address space if they have identical programming values.

26 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Table 7. Multi-Device EEPROM Address Map Overview(1) (continued)

Table 8. Multi DS100BR111 EEPROM Data

28 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Table 8. Multi DS100BR111 EEPROM Data (continued)

8.6 Register Maps

Table 9. SMBus Slave Mode Register Map

7 Reserved R/W Set bit to 0

2 LOS Select 1 = Use LOS from CH B

3 PWDN Inputs Yes 1 = PWDN

1 Reserved Set bit to 0

0 Reserved Yes Set bit to 0

30 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Table 9. SMBus Slave Mode Register Map (continued)

4 Reserved Yes Set bit to 1

0 Reserved Set bit to 0

7 Reserved Set bit to 0

5 Reserved Yes Set bit to 0

4 Override IDLE Yes and 0x15

1 Override DEM Yes Override De-emphasis (ignore rate)

7 Reserved Reserved

7 Reserved Yes Set bit to 0

32 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

7 Reserved Yes Reserved

1 = Enable Fast IDLE control in Reg 0x28[3:2]6 Override Fast Idle Yes 0 = Disable Fast IDLE control in Reg 0x28[3:2].

0 Reserved Yes Reserved

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Signal Integrity in 10G-KR Applications

other words, operating in "KR Mode" implies that signals will pass through the repeater with a linearized output. different system applications. Table 10. Suggested 10G-KR Initial Device Settings in Pin Mode(1) (1) For 10G-KR mode with slow idle-to-active response, the MODE pin should be left floating. Table 11. Suggested 10G-KR Initial Device Settings in SMBus Modes recommended device settings. Table 12. SMBus 10G-KR Example Sequence 0x06 0x18 Set SMBus Slave Mode Register Enable. 0x08 0x04 Enable Output Mode Control for individual channel outputs. 0x0F 0x00 Set CHA EQ to 0x00. Set CHA Output Mode to Linear (10G-KR mode).0x10 0xAD If link-training is not required, set Reg 0x10 to 0xED. 0x11 0x00 Set CHA DEM to 000'b.

Table 12. SMBus 10G-KR Example Sequence (continued) Set CHB Output Mode to Linear (10G-KR mode).0x17 0xAD If link-training is not required, set Reg 0x18 to 0xED. 0x18 0x00 Set CHB DEM to 000'b. 0x23 0x10 Set CHA VOD to 100'b. Leave Idle Control at default levels.0x28 0x00 For SAS/SATA applications, set Reg 0x28 to 0x4C. 0x2D 0xB1 Set CHB VOD to 100'b.

9.1.2 OOB (Out-of-Band) Functionality in SAS/SATA Applications

for this faster idle-to-active response.

9.2 Typical Application

Figure 10. Test Setup Connections Diagram Figure 11. Test Setup Connections Diagram Figure 12. Test Setup Connections Diagram

9.2.1 Design Requirements

critical areas for consideration during design.

Use 100 Ω impedance traces. Length matching on the P and N traces should be done on the single-ended segments of the differential pair.
Use uniform trace width and trace spacing for differential pairs.
Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
The maximum body size for AC-coupling capacitors is 0402.
Back-drill connector vias and signal vias to minimize stub length.
Use Reference plane vias to ensure a low inductance path for the return current.

9.2.2 Detailed Design Procedure

The DS100BR111 is designed to be placed at an offset location with respect to the overall channel attenuation. Table 13. Suggested Generic 10GbE Initial Device Settings in Pin Mode(1) (1) For 10GbE applications, the MODE pin should be tied high. Table 14. Suggested Generic 10GbE Initial Device Settings in SMBus Modes Examples of the repeater performance are illustrated in the performance curves in the next section.

9.2.3 Application Performance Plots

cable media. For all measurements, Mode Pin = Float.

9.2.3.1 Equalization Results (Pre-Channel Only)

Figure 13. TL = 5 Inch 4–Mil FR4 Trace, Figure 14. TL = 5 Inch 4–Mil FR4 Trace, Figure 15. TL = 10 Inch 4–Mil FR4 Trace, Figure 16. TL= 10 Inch 4–Mil FR4 Trace, Figure 17. TL = 15 Inch 4–Mil FR4 Trace, Figure 18. TL = 15 Inch 4–Mil FR4 Trace,

Figure 25. TL = 3-Meter 30-AWG 100 Ω Twin-Axial Cable, Figure 26. TL = 3-Meter 30-AWG 100 Ω Twin-Axial Cable, Figure 27. TL = 7-Meter 30-AWG 100 Ω Twin-Axial Cable, Figure 28. TL = 7-Meter 30-AWG 100 Ω Twin-Axial Cable, Figure 29. TL = 10-Meter 30-AWG 100 Ω Twin-Axial Cable, Figure 30. TL = 10-Meter 30-AWG 100 Ω Twin-Axial Cable,

9.2.3.2 Equalization and De-Emphasis Results

Figure 31. TL1 = 15 Inch 4–Mil FR4 Trace, Figure 32. TL1 = 15 Inch 4–Mil FR4 Trace,

9.2.3.3 Equalization and De-Emphasis Results

Figure 33. TL1 = 15 Inch 4–Mil FR4 Trace, Figure 34. TL1 = 15 Inch 4–Mil FR4 Trace, Figure 35. TL1 = 30 Inch 4–Mil FR4 Trace, Figure 36. TL1 = 30 Inch 4–Mil FR4 Trace, Figure 37. TL1 = 40 Inch 4–Mil FR4 Trace, Figure 38. TL1 = 40 Inch 4–Mil FR4 Trace,

10 Power Supply Recommendations

connections for each supply selection.

3.3 V Mode of Operation – Tie VDD_SEL = GND. – Feed 3.3 V supply into VIN pin. Local 10 µF and 1 µF decoupling at VIN is recommended. – See information on VDD bypass in Power Supply Bypass. – SDA and SCL pins should connect pull-up resistor to VIN. – Any 4-Level input which requires a connection to "Logic 1" should use a 1 kΩ resistor to VIN.
2.5 V Mode of Operation – VDD_SEL = Float – VIN = Float – Feed 2.5 V supply into VDD pins. Local 10 µF and 1 µF decoupling at VIN is recommended. – See information on VDD bypass in Power Supply Bypass. – SDA and SCL pins connect pull-up resistor to VDD for 2.5 V or 3.3 V microcontroller SMBus IO. – Any 4-Level input which requires a connection to "Logic 1" should use a 1 kΩ resistor to VDD. NOTE The DAP (bottom solder pad) is the GND connection.

Figure 39. 3.3 V or 2.5 V Supply Connection Diagram

SNLS338F –JANUARY 2011–REVISED NOVEMBER 2014 www.ti.com

10.1 Power Supply Bypass

Two approaches are recommended to ensure that the DS100BR111 is provided with an adequate power supply bypass. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the printed circuit board. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.1 μF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to the device. Small body size capacitors (such as 0402) reduce the capacitors' parasitic inductance and also help in placement close to the VDD pin. If possible, the layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance.

11 Layout

11.1 Layout Guidelines

The differential inputs and outputs are designed with 100 Ω differential terminations. Therefore, they should be connected to interconnects with controlled differential impedance of approximately 85-110 Ω. It is preferable to route differential lines primarily on one layer of the board, particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias are used, the layout must also provide for a low inductance path for the return currents as well. Route the differential signals away from other signals and noise sources on the printed circuit board. To minimize the effects of crosstalk, a 5:1 ratio or greater should be maintained between inter-pair spacing and trace width. See AN-1187 “Leadless Leadframe Package (LLP) The DS100BR111 pinout promotes easy high speed routing and layout. To optimize DS100BR111 performance, refer to the following guidelines: 1. Place local VIN and VDD capacitors as close as possible to the device supply pins. Often the best location is directly under the DS100BR111 pins to reduce the inductance path to the capacitor. In addition, bypass capacitors may share a via with the DAP GND to minimize ground loop inductance. 2. Differential pairs going into or out of the DS100BR111 should have adequate pair-to-pair spacing to minimize crosstalk. 3. Use return current via connections to link reference planes locally. This ensures a low inductance return current path when the differential signal changes layers. 4. Optimize the via structure to minimize trace impedance mismatch. 5. Place GND vias around the DAP perimeter to ensure optimal electrical and thermal performance. A 2x2 or 3x3 array of GND vias for the DAP is recommended. 6. Use small body size AC coupling capacitors when possible — 0402 or smaller size is preferred. The AC coupling capacitors should be placed closer to the Rx on the channel.

Product Folder Links: DS100BR111

11.2 Layout Example

shows the DS100BR111 channels in a typical 1-lane bidirectional layout. Figure 40. DS100BR111 Example Layout

SNLS338F –JANUARY 2011–REVISED NOVEMBER 2014 www.ti.com

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

Absolute Maximum Ratings for Soldering (SNOA549).
Leadless Leadframe Package (LLP) Application Report, AN-1187 (SNOA401)
Semiconductor and IC Package Thermal Metrics (SPRA953).

12.2 Trademarks

All trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: DS100BR111

www.ti.com 18-Apr-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS100BR111SQ/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 BR111 DS100BR111SQE/NOPB ACTIVE WQFN RTW 24 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 BR111 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 18-Apr-2014 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 18-Apr-2014 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS100BR111SQ/NOPB WQFN RTW 24 1000 213.0 191.0 55.0 DS100BR111SQE/NOPB WQFN RTW 24 250 213.0 191.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 18-Apr-2014 Pack Materials-Page 2

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Product Information

DS100BR111SQ/NOPB specifications and overview.

Summary

Ultra Low Power 10.3 Gbps 1-Lane Repeater with Input Equalization and Output De-Emphasis

Description

Ultra Low Power 10.3 Gbps 1-Lane Repeater with Input Equalization and Output De-Emphasis

Source title DS100BR111SQ/NOPB Datasheet(PDF) - Texas Instruments

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