DS08MB200 TI | Alldatasheet

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LI_0 SOA_0 SOB_0 SIA_0 SIB_0 MUX_S0 Channel 0 LO_0 ENL_0 ENA_0 ENB_0 Mux Buffer Switch Fabric A Switch Fabric B FPGA or ASIC Backplane or Cable LVDS LVDS DS08MB200 www.ti.com SNLS197D –MAY 2006–REVISED MARCH 2013 DS08MB200Dual800Mbps2:1/1:2LVDSMux/Buffer Check forSamples: DS08MB200 1FEATURES DESCRIPTION The DS08MB200 isa dual-port1 to2 repeater/buffer 2• Up to800 Mbps Data Rate per Channel and 2 to 1 multiplexer.High-speeddata paths and• LVDS/BLVDS/CML/LVPECL Compatible Inputs, flow-throughpinoutminimizeinternaldevicejitterandLVDS Compatible Outputs simplifyboard layout.The differentialinputsand

  • Low Output Skew and Jitter outputsinterfacetoLVDS or Bus LVDS signalssuch as those on TI's10-,16-,and 18- bitBus LVDS• On-Chip 100Ω InputTermination SerDes,ortoCML orLVPECL signals.• 15 kV ESD Protectionon LVDS Inputs/Outputs The 3.3V supply,CMOS process,and robustI/O• Hot Plug Protection ensurehighperformanceatlow power overtheentire• Single3.3VSupply industrial-40to+85°C temperaturerange.
  • Industrial-40to+85°C Temperature Range
  • 48-pinWQFN Package TypicalApplication Block Diagram Figure1. DS08MB200 Block Diagram Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2006–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS197D –MAY 2006–REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS Pin WQFN Pin I/O,Type DescriptionName Number SWITCH SIDE DIFFERENTIAL INPUTS SIA_0+ 30 I,LVDS SwitchA-sideChannel0 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or SIA_0− 29 LVPECL compatible. SIA_1+ 19 I,LVDS SwitchA-sideChannel1 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or SIA_1− 20 LVPECL compatible. SIB_0+ 28 I,LVDS SwitchB-sideChannel0 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or SIB_0− 27 LVPECL compatible. SIB_1+ 21 I,LVDS SwitchB-sideChannel1 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or SIB_1− 22 LVPECL compatible. LINE SIDE DIFFERENTIAL INPUTS LI_0+ 40 I,LVDS Line-sideChannel0 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or LI_0− 39 LVPECL compatible. LI_1+ 9 I,LVDS Line-sideChannel1 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or LI_1− 10 LVPECL compatible. SWITCH SIDE DIFFERENTIAL OUTPUTS SOA_0+ 34 O, LVDS SwitchA-sideChannel0 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). SOA_0 − 33 SOA_1+ 15 O, LVDS SwitchA-sideChannel1 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). SOA_1 − 16 SOB_0+ 32 O, LVDS SwitchB-sideChannel0 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). SOB_0 − 31 SOB_1+ 17 O, LVDS SwitchB-sideChannel1 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). SOB_1 − 18 LINE SIDE DIFFERENTIAL OUTPUTS LO_0+ 42 O, LVDS Line-sideChannel0 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). LO_0 − 41 LO_1+ 7 O, LVDS Line-sideChannel1 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). LO_1 − 8 DIGITAL CONTROL INTERFACE MUX_S0 38 I,LVTTL Mux SelectControlInputs(perchannel)toselectwhichSwitch-sideinput,A orB,ispassed through MUX_S1 11 totheLine-side. ENA_0 36 I,LVTTL OutputEnableControlforSwitchA-sideand B-sideoutputs.Each outputdriveron theA-sideand B- ENA_1 13 sidehas a separateenablepin. ENB_0 35 ENB_1 14 ENL_0 45 I,LVTTL OutputEnableControlforThe Line-sideoutputs.Each outputdriveron theLine-sidehas a separate ENL_1 4 enablepin. POWER VDD 6,12,37, I,Power VDD = 3.3V±0.3V. 43,48 GND 2,3,46, I,Power Ground referenceforLVDS and CMOS circuitry. 47(3) FortheWQFN package,theDAP isused as theprimaryGND connectiontothedevice.The DAP is theexposed metalcontactatthebottomoftheWQFN-48 package.Itshouldbe connectedtothe groundplanewithatleast4 viasforoptimalAC and thermalperformance. N/C 1,5,23,24, No Connect 25,26,44 (1) ForinterfacingLVDS outputstoCML orLVPECL compatibleinputs,refertotheAPPLICATIONS sectionofthisdatasheet. (2) The LVDS outputsdo notsupporta multidrop(BLVDS) environment.The LVDS outputcharacteristicsoftheDS08MB200 devicehave been optimizedforpoint-to-pointbackplaneand cableapplications. (3) Note thattheDAP on thebacksideoftheWQFN package istheprimaryGND connectionforthedevicewhen usingtheWQFN package.

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ENL_0 N/C VDD LO_0+ LO_0- LI_0+ LI_0- MUX_S0 VDD ENA_1 ENB_1 SOA_1+ SOA_1- SOB_1+ SOB_1- SIA_1+ SIA_1- SIB_1+ SIB_1- N/C N/C VDD MUX_S1 LI_1- LI_1+ LO_1- LO-1+ VDD N/C ENL_1 GND GND N/C 12 11 10 9 8 7 6 5 4 3 2 1N/C N/C SIB_0- SIB_0+ SIA_0- SIA_0+ SOB_0- SOB_0+ SOA_0- SOA_0+ ENB_0 ENA_0 25 26 27 28 29 30 31 32 33 34 35 36 DAP (GND) VDD GND GND ENL_0 N/C VDD LO_0+ LO_0- LI_0+ LI_0- MUX_S0 VDD ENA_1 ENB_1 SOA_1+ SOA_1- SOB_1+ SOB_1- SIA_1+ SIA_1- SIB_1+ SIB_1- N/C N/C VDD MUX_S1 LI_1- LI_1+ LO_1- LO-1+ VDD N/C ENL_1 GND GND N/C N/C N/C SIB_0- SIB_0+ SIA_0- SIA_0+ SOB_0- SOB_0+ SOA_0- SOA_0+ ENB_0 ENA_0 Channel 0 Channel 1 DS08MB200 www.ti.com SNLS197D –MAY 2006–REVISED MARCH 2013 Connection Diagrams Top View Top View Figure2.WQFN Package Figure3.DirectionalSignalPaths See Package Number RHS0048A (Refertopinnames forsignalpolarity) DAP = GND TRI-STATE and Powerdown Modes The DS08MB200 has outputenablecontrolon each ofthesixonboardLVDS outputdrivers.Thiscontrolallows each outputindividuallytobe placedina low power TRI-STATE mode whilethedeviceremainsactive,and is usefultoreducepower consumptionon unused channels.InTRI-STATE mode, some outputsmay remainactive whilesome areinTRI-STATE. When allsixoftheoutputenables(alldriverson bothchannels)aredeasserted(LOW), thenthedeviceentersa Powerdown mode thatconsumes only0.5mA (typical)of supplycurrent.In thismode, the entiredeviceis essentiallypowered off,includingallreceiverinputs,outputdriversand internalbandgap referencegenerators. When returningto activemode from Powerdown mode, thereisa delayuntilvaliddata ispresentedat the outputsbecause oftheramp topower up theinternalbandgap referencegenerators. Any singleoutputenablethatremainsactivewillholdthedeviceinactivemode even iftheotherfiveoutputsare inTRI-STATE. When inPowerdown mode, any outputenablethatbecomes activewillwake up the deviceback intoactive mode, even iftheotherfiveoutputsareinTRI-STATE. InputFailsafeBiasing Externalpullup and pulldown resistorsmay be used toprovideenough ofan offsettoenablean inputfailsafe under open-circuitconditions.ThisconfigurationtiesthepositiveLVDS inputpintoVDD thrua pullup resistor and the negativeLVDS inputpinistiedto GND by a pulldown resistor.The pullup and pulldown resistors shouldbe inthe5kΩ to15kΩ range tominimizeloadingand waveform distortiontothedriver.Pleasereferto applicationnoteSNLA051B AN-1194,“FailsafeBiasingofLVDS Interfaces”formore information. Output Characteristics The outputcharacteristicsof the DS08MB200 have been optimizedforpoint-to-pointbackplaneand cable applications,and arenotintendedformultipointormultidropsignaling. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS08MB200

SNLS197D –MAY 2006–REVISED MARCH 2013 www.ti.com MULTIPLEXER TRUTH TABLE (1)(2) Data Inputs ControlInputs Output SIA_0 SIB_0 MUX_S0 ENL_0 LO_0 X valid 0 1 SIB_0 valid X 1 1 SIA_0 X X X 0 (3) Z (1) Same functionalityforchannel1 (2) X = Don 'tCare Z = HighImpedance (TRI-STATE) (3) When allenableinputsfrombothchannelsareLow, thedeviceentersa powerdown mode. RefertotheTRI-STATE and Powerdown Modes section. REPEATER/BUFFER TRUTH TABLE (1)(2) Data Input ControlInputs Outputs LI_0 ENA_0 ENB_0 SOA_0 SOB_0 X 0 0 Z (3) Z (3) valid 0 1 Z LI_0 valid 1 0 LI_0 Z valid 1 1 LI_0 LI_0 (1) Same functionalityforchannel1 (2) X = Don 'tCare Z = HighImpedance (TRI-STATE) (3) When allenableinputsfrombothchannelsareLow, thedeviceentersa powerdown mode. RefertotheTRI-STATE and Powerdown Modes section. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1) SupplyVoltage(VDD ) −0.3Vto+4.0V CMOS InputVoltage -0.3Vto(VDD +0.3V) LVDS ReceiverInputVoltage(2) -0.3Vto(VDD +0.3V) LVDS DriverOutputVoltage -0.3Vto(VDD +0.3V) LVDS OutputShortCircuitCurrent +40 mA JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature(Solder,4sec) 260°C Max Pkg Power Capacity@ 25°C 5.2W ThermalResistance(θJA) 24°C/W Package Deratingabove +25°C 41.7mW/°C ESD LastPassingVoltage HBM, 1.5kΩ,100pF 8kV LVDS pinstoGND only 15kV EIAJ,0Ω,200pF 250V CDM 1000V (1) Absolutemaximum ratingsarethosevaluesbeyond whichdamage tothedevicemay occur.Texas Instrumentsdoes notrecommend operationofproductsoutsideofrecommended operationconditions. (2) VID max < 2.4V RECOMMENDED OPERATING CONDITIONS SupplyVoltage(VCC ) 3.0Vto3.6V InputVoltage(VI)(1) 0V toVCC OutputVoltage(VO ) 0V toVCC OperatingTemperature(TA) Industrial −40°C to+85°C (1) VID max < 2.4V

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www.ti.com SNLS197D –MAY 2006–REVISED MARCH 2013

ELECTRICAL CHARACTERISTICS

Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ (1) Max Units LVTTL DC SPECIFICATIONS (MUX_Sn, ENA_n, ENB_n, ENL_n) VIH HighLevelInputVoltage 2.0 VDD V VIL Low LevelInputVoltage GND 0.8 V IIH HighLevelInputCurrent VIN = VDD = VDDMAX −10 +10 µA IIL Low LevelInputCurrent VIN = VSS ,VDD = VDDMAX −10 +10 µA C IN1 InputCapacitance Any DigitalInputPintoVSS 3.5 pF C OUT1 OutputCapacitance Any DigitalOutputPintoVSS 5.5 pF VCL InputClamp Voltage ICL = −18 mA −1.5 −0.8 V LVDS INPUT DC SPECIFICATIONS (SIA±,SIB±,LI±) VTH DifferentialInputHighThreshold(2) VCM = 0.8Vor1.2Vor3.55V, 0 100 mVVDD = 3.6V VTL DifferentialInputLow Threshold(2) VCM = 0.8Vor1.2Vor3.55V, −100 0 mVVDD = 3.6V VID DifferentialInputVoltage VCM = 0.8Vto3.55V,VDD = 3.6V 100 2400 mV VCMR Common Mode VoltageRange VID = 150 mV, VDD = 3.6V 0.05 3.55 V C IN2 InputCapacitance IN+ orIN− toVSS 3.5 pF IIN InputCurrent VIN = 3.6V,VDD = VDDMAX −15 +15 µA VIN = 0V,VDD = VDDMAX −15 +15 µA LVDS OUTPUT DC SPECIFICATIONS (SOA_n ±,SOB_n ±,LO_n ±) VOD DifferentialOutputVoltage(2) R L istheinternal100Ω between OUT+ 250 360 500 mV and OUT −ΔVOD Change inVOD between -35 35 mVComplementaryStates VOS OffsetVoltage(3) 1.05 1.22 1.475 V ΔVOS Change inVOS between -35 35 mVComplementaryStates IOS OutputShortCircuitCurrent OUT+ orOUT − ShorttoGND −21 -40 mA C OUT2 OutputCapacitance OUT+ orOUT − toGND when TRI- 5.5 pFSTATE SUPPLY CURRENT (Static) ICC SupplyCurrent Allinputsand outputsenabledand active,terminatedwithdifferentialloadof 225 275 mA 100Ω between OUT+ and OUT-. ICCZ SupplyCurrent-Powerdown Mode ENA_0 = ENB_0 = ENL_0= ENA_1 = 0.6 4.0 mAENB_1 = ENL_1 = L SWITCHING CHARACTERISTICS — LVDS OUTPUTS tLHT DifferentialLow toHighTransition Use an alternating1 and 0 patternat200 170 250 psTime Mb/s,measure between 20% and 80% of VOD .(4) tHLT DifferentialHightoLow Transition 170 250 psTime tPLHD DifferentialLow toHighPropagation Use an alternating1 and 0 patternat200 1.0 2.5 nsDelay Mb/s,measure at50% VOD between inputtooutput.tPHLD DifferentialHightoLow Propagation 1.0 2.5 nsDelay tSKD1 PulseSkew |tPLHD –tPHLD |(4) 25 75 ps tSKCC OutputChanneltoChannelSkew Differenceinpropagationdelay(tPLHD or 50 115 pstPHLD )among alloutputchannels.(4) (1) Typicalparametersaremeasured atVDD = 3.3V,TA = 25°C. They areforreferencepurposes,and arenotproduction-tested. (2) DifferentialoutputvoltageVOD isdefinedas ABS(OUT+ –OUT −).DifferentialinputvoltageVID isdefinedas ABS(IN+–IN−). (3) OutputoffsetvoltageVOS isdefinedas theaverageoftheLVDS single-endedoutputvoltagesatlogichighand logiclowstates. (4) Not productiontested.Ensuredby statisticalanalysison a sample basisatthetimeofcharacterization. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS08MB200

SNLS197D –MAY 2006–REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ (1) Max Units tJIT Jitter(5) RJ -Alternating1 and 0 at400 MHz (6) 1.3 1.5 psrms DJ -K28.5Pattern,800 Mbps (7) 15 34 psp-p TJ -PRBS 27-1Pattern,800 Mbps (8) 16 34 psp-p tON LVDS OutputEnableTime Time fromENA_n, ENB_n, orENL_n to 0.5 1.5 µsOUT ± change fromTRI-STATE toactive. tON2 LVDS OutputEnabletimefrom Time fromENA_n, ENB_n, orENL_n to 10 20 µspowerdown mode OUT ± change fromPowerdown toactive tOFF LVDS OutputDisableTime Time fromENA_n, ENB_n, orENL_n to OUT ± change fromactivetoTRI-STATE 12 ns orpowerdown. (5) Jitterisnotproductiontested,butensuredthroughcharacterizationon a sample basis. (6) Random Jitter,orRJ,ismeasured RMS witha histogramincluding1500 histogramwindow hits.The inputvoltage= VID = 500mV, 50% dutycycleat400 MHz, tr = tf= 50ps (20% to80%). (7) DeterministicJitter,orD J,ismeasured toa histogrammean witha sample sizeof350 hits.Stimulusand fixturejitterhas been subtracted.The inputvoltage= VID = 500mV, K28.5patternat800 Mbps, tr = tf= 50ps (20% to80%).The K28.5patternisrepeatingbit streamsof(00111110101100000101). (8) TotalJitter,orTJ,ismeasured peak topeak witha histogramincluding3500 window hits.Stimulusand fixturejitterhas been subtracted. The inputvoltage= VID = 500mV, 27-1 PRBS patternat800 Mbps, tr = tf= 50ps (20% to80%).

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POWER SUPPLY CURRENT (mA) 350 BIT DATA RATE (Mbps) 0 800 100 150 200 200 400 600 250 300 DS08MB200 www.ti.com SNLS197D –MAY 2006–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Currentvs.BitData Rate TotalJittervs.Temperature TotalJittermeasured at0V differentialwhilerunninga PRBS 27-1 Dynamic power supplycurrentwas measured withallchannelsactive patternwithone channelactive,allotherchannelsaredisabled.VDD =and togglingatthebitdatarate.Data patternhas no effecton the fixturejitterhas been subtracted. Figure4. Figure5. TotalJittervs.BitData Rate TotalJittermeasured at0V differentialwhilerunninga PRBS 27-1 patternwithone channel active,allotherchannels aredisabled. VDD = 3.3V,TA = +25°C, VID = 0.5V.Stimulusand fixturejitterhas been subtracted. Figure6. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS08MB200

150: 150: 50: 50: 15MB200 0.1 PF 0.1 PF LVPECL 150: 150: 50: 50: 15MB200 DS08MB200 SNLS197D –MAY 2006–REVISED MARCH 2013 www.ti.com

APPLICATIONS

An LVPECL driverconsistsofa differentialpairwithcoupledemittersconnectedtoGND viaa currentsource. This drivesa pairof emitter-followersthatrequirea 50 ohm to VCC -2.0load.A modern LVPECL driverwill typicallyincludetheterminationscheme withinthedevicefortheemitterfollower.Ifthedriverdoes notinclude theload,thenan externalscheme must be used.The 1.3V supplyisusuallynotreadilyavailableon a PCB, therefore,a loadscheme withouta uniquepower supplyrequirementmay be used. Figure7. DC Coupled LVPECL toLVDS Interface Figure7 isa separatedπ terminationscheme fora 3.3V LVPECL driver.R1 and R2 providesproperDC loadfor thedriveremitterfollowers,and may be includedas partofthedriverdevice.The DS08MB200 includesa 100 ohm inputterminationforthe transmissionline.The common mode voltagewillbe at the normal LVPECL levels– around 2 V. Thisscheme works wellwithLVDS receiversthathave rail-to-railcommon mode voltage, VCM ,range.Most Texas InstrumentsLVDS receivershave wide VCM range.The exceptionsarenotedindevices’ respectivedatasheets.Those LVDS devicesthatdo have a wide VCM range do not vary in performance significantlywhen receivinga signalwitha common mode otherthanstandardLVDS VCM of1.2V. Figure8. AC Coupled LVPECL toLVDS Interface An AC coupledinterfaceispreferredwhen transmitterand receivergroundreferencesdiffermore than1 V. This isa likelyscenariowhen transmitterand receiverdevicesare on separatePCBs. Figure8 illustratesan AC coupledinterfacebetween a LVPECL driverand LVDS receiver.R1 and R2, ifnotpresentinthedriverdevice, provideDC loadfortheemitterfollowersand may range between 140-220 ohms formost LVPECL devicesfor thisparticularconfiguration.The DS08MB200 includesan internal100 ohm resistortoterminatethetransmission lineforminimalreflections.The signalafterac couplingcapacitorswillswing around a levelset by internal biasingresistors(i.e.fail-safe)which iseitherVDD /2or 0 V dependingon theactualfailsafeimplementation.If internalbiasingisnotimplemented,thesignalcommon mode voltagewillslowlywander toGND level.

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130: 130: 50: 50: LVPECL VDD 83: 83: 0.1PF 0.1PF 15MB200 50: 50: 50: 50: LVPECL VT DS08MB200 www.ti.com SNLS197D –MAY 2006–REVISED MARCH 2013 InterfacingLVDS toLVPECL An LVDS driverconsistsofa currentsource(nominal3.5mA) which drivesa CMOS differentialpair.Itneeds a differentialresistiveloadintherangeof70 to130 ohms togenerateLVDS levels.Ina system,theloadshould be selectedto match transmissionlinecharacteristicdifferentialimpedance so thatthe lineis properly terminated.The terminationresistorshould be placed as close to the receiverinputsas possible.When interfacingan LVDS driverwitha non-LVDS receiver,one onlyneeds tobiastheLVDS signalso thatitiswithin thecommon mode range ofthereceiver.Thismay be done by usingseparatebiasingvoltagewhich demands anotherpower supply.Some receivershave requiredbiasingvoltageavailableon-chip(VT,VTT orVBB ). Figure9. DC Coupled LVDS toLVPECL Interface Figure9 illustratesinterfacebetween an LVDS driverand a LVPECL witha VT pinavailable.R1 and R2, ifnot presentinthereceiver,provideproperresistiveloadforthedriverand terminationforthetransmissionline,and VT setsdesiredbiasforthereceiver. Figure10. AC Coupled LVDS toLVPECL Interface Figure10 illustratesAC coupledinterfacebetween an LVDS driverand LVPECL receiverwithouta VT pin available.The resistorsR1, R2, R3, and R4, ifnotpresentinthereceiver,providea loadforthedriver,terminate thetransmissionline,and biasthesignalforthereceiver. The biasnetworksshown above forLVPECL driversand receiversmay ormay notbe presentwithinthedriver device.The LVPECL driverand receiverspecificationmust be reviewedcloselytoensurecompatibilitybetween thedriverand receiverterminationsand common mode operatingranges. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS08MB200

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS08MB200TSQ/NOPB Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 08MB200 DS08MB200TSQ/NOPB.A Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 08MB200 DS08MB200TSQX/NOPB Active Production WQFN (RHS) | 48 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 08MB200 DS08MB200TSQX/NOPB.A Active Production WQFN (RHS) | 48 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 08MB200 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS08MB200TSQ/NOPB WQFN RHS 48 250 208.0 191.0 35.0 DS08MB200TSQX/NOPB WQFN RHS 48 2500 356.0 356.0 36.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C SEE TERMINAL DETAIL 48X 0.30 0.18 5.1 0.1 48X 0.5 0.3 0.8 0.7 (A) TYP 0.05 0.00 44X 0.5 5.5 2X 5.5 A 7.15 6.85 B 7.15 6.85 0.30 0.18 0.5 0.3 (0.2) WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 DIM A OPT 1 OPT 2 (0.1) (0.2) PIN 1 INDEX AREA 0.08 C SEATING PLANE 12 25 13 24 48 37 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD

49 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 1.800 DETAIL OPTIONAL TERMINAL TYPICAL

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0.07 MIN

0.07 MAX

48X (0.25) 48X (0.6) ( 0.2) TYP VIA 44X (0.5) (6.8) (6.8) (1.25) TYP ( 5.1) (R0.05) TYP (1.25) TYP (1.05) TYP (1.05) TYP WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 SYMM 13 24 3748 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL EDGE SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 48X (0.6) 48X (0.25) 44X (0.5) (6.8) (6.8) 16X ( 1.05) (0.625) TYP (R0.05) TYP (1.25) TYP (1.25) TYP (0.625) TYP WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:15X SYMM 13 24 3748

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