DS08MB200 NSC | Alldatasheet
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Features
n Up to 800 Mbps data rate per channel n LVDS/BLVDS/CML/LVPECL compatible inputs, LVDS compatible outputs n Low output skew and jitter n On-chip 100Ω input termination n 15 kV ESD protection on LVDS Inputs/Outputs n Hot plug Protection n Single 3.3V supply n Industrial -40 to +85˚C temperature range n 48-pin LLP Package Typical Application 20157420 Block Diagram 20157401 FIGURE 1. DS08MB200 Block Diagram
Number I/O, Type Description SWITCH SIDE DIFFERENTIAL INPUTS SIA_0+ SIA_0− I, LVDS Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. SIA_1+ SIA_1− I, LVDS Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. SIB_0+ SIB_0− I, LVDS Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. SIB_1+ SIB_1− I, LVDS Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. LINE SIDE DIFFERENTIAL INPUTS LI_0+ LI_0− I, LVDS Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. LI_1+ LI_1− I, LVDS Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. SWITCH SIDE DIFFERENTIAL OUTPUTS SOA_0+ SOA_0− O, LVDS Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (Notes 1, 3). SOA_1+ SOA_1− O, LVDS Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (Notes 1, 3). SOB_0+ SOB_0− O, LVDS Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (Notes 1, 3). SOB_1+ SOB_1− O, LVDS Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (Notes 1, 3). LINE SIDE DIFFERENTIAL OUTPUTS LO_0+ LO_0− O, LVDS Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (Notes 1, 3). LO_1+ LO_1− O, LVDS Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (Notes 1, 3). DIGITAL CONTROL INTERFACE MUX_S0 MUX_S1 I, LVTTL Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed through to the Line-side. ENA_0 ENA_1 ENB_0 ENB_1 I, LVTTL Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side and B-side has a separate enable pin. ENL_0 ENL_1 I, LVTTL Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a separate enable pin. POWER V DD 6, 12, 37, 43, 48 I, Power V DD = 3.3V ±0.3V. GND 2, 3, 46, 47 (Note I, Power Ground reference for LVDS and CMOS circuitry. For the LLP package, the DAP is used as the primary GND connection to the device. The DAP is the exposed metal contact at the bottom of the LLP-48 package. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance. N/C 1, 5, 23, 24, 25, 26, 44 No Connect Note 1: For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet. Note 2: Note that the DAP on the backside of the LLP package is the primary GND connection for the device when using the LLP package. Note 3: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS08MB200 device have been optimized for point-to-point backplane and cable applications. DS08MB200 www.national.com 2
DAP = GND 20157403 Directional Signal Paths Top View (Refer to pin names for signal polarity) TRI-STATE and Powerdown Modes The DS08MB200 has output enable control on each of the six onboard LVDS output drivers. This control allows each output individually to be placed in a low power TRI-STATE mode while the device remains active, and is useful to reduce power consumption on unused channels. In TRI- STATE mode, some outputs may remain active while some are in TRI-STATE. When all six of the output enables (all drivers on both chan- nels) are deasserted (LOW), then the device enters a Pow- erdown mode that consumes only 0.5mA (typical) of supply current. In this mode, the entire device is essentially pow- ered off, including all receiver inputs, output drivers and internal bandgap reference generators. When returning to active mode from Powerdown mode, there is a delay until valid data is presented at the outputs because of the ramp to power up the internal bandgap reference generators. Any single output enable that remains active will hold the device in active mode even if the other five outputs are in TRI-STATE. When in Powerdown mode, any output enable that becomes active will wake up the device back into active mode, even if the other five outputs are in TRI-STATE. Input Failsafe Biasing External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform dis- tortion to the driver. Please refer to application note AN- 1194, “Failsafe Biasing of LVDS Interfaces” for more infor- mation. Output Characteristics The output characteristics of the DS08MB200 have been optimized for point-to-point backplane and cable applica- tions, and are not intended for multipoint or multidrop signal- ing. Multiplexer Truth Table(Note 4) Data Inputs Control Inputs Output SIA_0 SIB_0 MUX_S0 ENL_0 LO_0 X valid 0 1 SIB_0 valid X 1 1 SIA_0 X X X 0 (Note 5) Z X = Don’t Care Z = High Impedance (TRI-STATE) Repeater/Buffer Truth Table(Note 4) Data Input Control Inputs Outputs LI_0 ENA_0 ENB_0 SOA_0 SOB_0 X 0 0 Z (Note 5) Z (Note 5) valid 0 1 Z LI_0 valid 1 0 LI_0 Z valid 1 1 LI_0 LI_0 X = Don’t Care Z = High Impedance (TRI-STATE) Note 4: Same functionality for channel 1 Note 5: When all enable inputs from both channels are Low, the device enters a powerdown mode. Refer to the applications section titled TRI-STATE and Powerdown modes. DS08MB200 www.national.com3
Absolute Maximum Ratings(Note 6) Supply Voltage (VDD) −0.3V to +4.0V CMOS Input Voltage -0.3V to (V DD+0.3V) LVDS Receiver Input Voltage (Note 7) -0.3V to (V DD+0.3V) LVDS Driver Output Voltage -0.3V to (V DD+0.3V) LVDS Output Short Circuit Current +40 mA Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Solder, 4sec) 260˚C Max Pkg Power Capacity @ 25˚C 5.2W Thermal Resistance (θJA) 24˚C/W Package Derating above +25˚C 41.7mW/˚C ESD Last Passing Voltage HBM, 1.5kΩ, 100pF 8kV LVDS pins to GND only 15kV EIAJ, 0Ω, 200pF 250V CDM 1000V Recommended Operating Conditions Supply Voltage (VCC) 3.0V to 3.6V Input Voltage (VI) (Note 7) 0V to V CC Output Voltage (VO) 0 Vt oV CC Operating Temperature (TA) Industrial −40˚C to +85˚C Note 6: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recom- mend operation of products outside of recommended operation conditions. Note 7: V ID max < 2.4V
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note 8) Max Units LVTTL DC SPECIFICATIONS(MUX_Sn, ENA_n, ENB_n, ENL_n) VIH High Level Input Voltage 2.0 V DD V VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current V IN =V DD =V DDMAX −10 +10 µA IIL Low Level Input Current V IN =V SS,V DD =V DDMAX −10 +10 µA CIN1 Input Capacitance Any Digital Input Pin to V SS 3.5 pF COUT1 Output Capacitance Any Digital Output Pin to V SS 5.5 pF VCL Input Clamp Voltage I CL = −18 mA −1.5 −0.8 V LVDS INPUT DC SPECIFICATIONS(SIA±, SIB±,L I±) VTH Differential Input High Threshold (Note 9) VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V 0 100 mV VTL Differential Input Low Threshold (Note 9) VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V −100 0 mV VID Differential Input Voltage V CM = 0.8V to 3.55V, V DD = 3.6V 100 2400 mV VCMR Common Mode Voltage Range V ID = 150 mV, V DD = 3.6V 0.05 3.55 V CIN2 Input Capacitance IN+ or IN− to V SS 3.5 pF IIN Input Current V IN = 3.6V, VDD =V DDMAX −15 +15 µA VIN = 0V, VDD =V DDMAX −15 +15 µA LVDS OUTPUT DC SPECIFICATIONS(SOA_n±, SOB_n±, LO_n±) VOD Differential Output Voltage, (Note 9) RL is the internal 100 Ω between OUT+ and OUT− 250 360 500 mV ∆VOD Change in VOD between Complementary States -35 35 mV VOS Offset Voltage (Note 10) 1.05 1.22 1.475 V ∆VOS Change in VOS between Complementary States -35 35 mV IOS Output Short Circuit Current OUT+ or OUT− Short to GND −21 -40 mA COUT2 Output Capacitance OUT+ or OUT− to GND when TRI-STATE 5.5 pF DS08MB200 www.national.com 4
Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note 8) Max Units SUPPLY CURRENT (Static) ICC Supply Current All inputs and outputs enabled and active, terminated with differential load of 100Ω between OUT+ and OUT-. 225 275 mA I CCZ Supply Current - Powerdown Mode ENA_0 = ENB_0 = ENL_0= ENA_1 = ENB_1 = ENL_1 = L 0.6 4.0 mA SWITCHING CHARACTERISTICS — LVDS OUTPUTS tLHT Differential Low to High Transition Time Use an alternating 1 and 0 pattern at
200 Mb/s, measure between 20% and
80% of V OD. (Note 15) 170 250 ps tHLT Differential High to Low Transition Time 170 250 ps tPLHD Differential Low to High Propagation Delay Use an alternating 1 and 0 pattern at
200 Mb/s, measure at 50% V OD
between input to output. 1.0 2.5 ns tPHLD Differential High to Low Propagation Delay 1.0 2.5 ns tSKD1 Pulse Skew |t PLHD–tPHLD| (Note 15) 25 75 ps tSKCC Output Channel to Channel Skew Difference in propagation delay (t PLHD or tPHLD) among all output channels. (Note 15) 50 115 ps tJIT Jitter (Note 11) RJ - Alternating 1 and 0 at 400 MHz (Note 12) 1.3 1.5 psrms DJ - K28.5 Pattern, 800 Mbps (Note 13) 15 34 psp-p TJ - PRBS 2 7-1 Pattern, 800 Mbps (Note 14) 16 34 psp-p tON LVDS Output Enable Time Time from ENA_n, ENB_n, or ENL_n to OUT± change from TRI-STATE to active. 0.5 1.5 µs tON2 LVDS Output Enable time from powerdown mode Time from ENA_n, ENB_n, or ENL_n to OUT± change from Powerdown to active 10 20 µs tOFF LVDS Output Disable Time Time from ENA_n, ENB_n, or ENL_n to OUT± change from active to TRI-STATE or powerdown. 12 ns Note 8: Typical parameters are measured at V DD = 3.3V, TA = 25˚C. They are for reference purposes, and are not production-tested. Note 9: Differential output voltage V OD is defined as ABS(OUT+–OUT−). Differential input voltage V ID is defined as ABS(IN+–IN−). Note 10: Output offset voltage V OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Note 11: Jitter is not production tested, but guaranteed through characterization on a sample basis. Note 12: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at 400 MHz, tr =t f = 50ps (20% to 80%). Note 13: Deterministic Jitter, or D J, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter has been subtracted. The input voltage = VID = 500mV, K28.5 pattern at 800 Mbps, t r =t f = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (00 11111010 1100000101). Note 14: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input voltage =V ID = 500mV, 27-1 PRBS pattern at 800 Mbps, t r =t f = 50ps (20% to 80%). Note 15: Not production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization. DS08MB200 www.national.com5
Typical Performance Characteristics Power Supply Current vs. Bit Data Rate Total Jitter vs. Temperature 20157412 Dynamic power supply current was measured with all channels active and toggling at the bit data rate. Data pattern has no effect on the power consumption. V DD = 3.3V, TA = +25˚C, VID = 0.5V, VCM = 1.2V. 20157410 Total Jitter measured at 0V differential while running a PRBS 2 7-1 pattern with one channel active, all other channels are disabled. V DD = 3.3V, VID = 0.5V, VCM = 1.2V, 800 Mbps data rate. Stimulus and fixture jitter has been subtracted. Total Jitter vs. Bit Data Rate 20157411 Total Jitter measured at 0V differential while running a PRBS 2 7-1 pattern with one channel active, all other channels are disabled. V DD = 3.3V, TA = +25˚C, VID = 0.5V. Stimulus and fixture jitter has been subtracted. DS08MB200 www.national.com 6
Physical Dimensions inches (millimeters) unless otherwise noted 48-Pin LLP DS08MB200TSQX (2500 piece Tape and Reel) National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/quality/green. Lead free products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com DS08MB200 Dual 800 Mbps 1:2/2:1 LVDS Mux/Buffer