DS07-13704-5E

E713704 FUJITSU | Alldatasheet

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DS07-13704-5EFUJITSU SEMICONDUCTOR DATA SHEET 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90590/590G Series MB90591/591G/F591A/F591G/594/594G/F594A/F594G MB90V590A/V590G n DESCRIPTION The MB90590/590G series with two FULL-CAN*1 interfaces and FLASH ROM is especially designed for automo- tive and industrial applications. Its main features are two on board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. The instruction set of F 2MC-16LX CPU core inherits an A T architecture of the F2MC* 2 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90590/590G series has peripheral resources of 8/10-bit A/D converters, UART (SCI), extended I/O serial interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)), stepping motor controller, and sound generator. *1 : Controller Area Network (CAN) - License of Robert Bosch GmbH *2 : F 2MC stands for FUJITSU Flexible Microcontroller. n PACKAGE 100-pin Plastic QFP (FPT -100P-M06)

• C l o c k Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock, V CC of 5.0 V)
• Instruction set to optimize controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C language) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed : 4-byte instruction queue
• Enhanced interrupt function : 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI 2OS) : Up to 10 channels
• Embedded ROM size and types Mask ROM : 256 Kbytes/384 Kbytes Flash ROM : 256 Kbytes/384 Kbytes Embedded RAM size : 6 Kbytes/8 Kbytes
• F l a s h R O M Supports automatic programming, Embedded Algorithm TM * Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Erase can be performed on each block Block protection with external programming voltage
• Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Clock mode Hardware stand-by mode
• P r o c e s s 0.5mm CMOS technology
• I/O port General-purpose I/O ports : 78 ports
• T i m e r Watchdog timer : 1 channel 8/16-bit PPG timer : 8/16-bit · 6 channels 16-bit re-load timer : 2 channels

• 16-bit I/O timer 16-bit free-run timer : 1 channel Input capture : 6 channels Output compare : 6 channels
• Extended I/O serial interface : 1 channel
• UART (3 channels) With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.
• Stepping motor controller (4 channels)
• External interrupt circuit (8 channels) A module for starting an extended intelligent I/O service (EI 2OS) and generating an external interrupt which is triggered by an external input.
• Delayed interrupt generation module Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input.
• FULL-CAN interfaces : 2 Conforming to Version 2.0 Part A and Part B Flexible message buffering (mailbox and FIFO buffering can be mixed)
• Sound generator
• 18-bit Time-base counter
• Clock timer : 1 channel
• External bus interface : Maximum address space 16 Mbytes * : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

(Continued) Features MB90591/591G/594/594G MB90F591A/F591G/ F594A/F594G MB90V590A/V590G Classification Mask ROM product Flash ROM product Evaluation product ROM size 384/256 Kbytes 384/256 Kbytes Boot block Hard-wired reset vector None RAM size 8/6 Kbytes 8/6 Kbytes 8 Kbytes Emulator-specific power supply *1 ¾ None CPU functions The number of instructions : 340 Instruction bit length : 8 bits, 16 bits Instruction length : 1 byte to 7 bytes Data bit length : 1 bit, 8 bits, 16 bits Minimum execution time : 62.5 ns (at machine clock frequency of 16 MHz) Interrupt processing time : 1.5 ms (at machine clock frequency of 16 MHz, minimum value) UART (3 channels) Clock synchronized transmission (500 Kbps / 1 Mbps / 2 Mbps) Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500 /500000 bps at machine clock frequency of 16 MHz) Transmission can be performed by bi-directional serial transmission or by master/ slave connection. 8/10-bit A/D converter Conversion precision : 8/10-bit can be selectively used. Number of inputs : 8 One-shot conversion mode (converts selected channel once only) Scan conversion mode (converts two or more successive channels and can program up to 8 channels) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) 8/16-bit PPG timers (6 channels) Number of channels : 6 (8/16-bit · 6 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval : fsys, fsys/2 1, fsys/22, fsys/23, fsys/24, 128ms (at oscillation of 4 MHz, fsys = system clock frequency of 16 MHz, fosc = oscillation clock frequency) 16-bit Reload timer Number of channels : 2 Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function 16-bit I/O timer 16-bit Output compares Number of channels : 6 (8/16-bit · 6 channels) Pin input factor : A match signal of compare register Input captures Number of channels : 6 Rewriting a register value upon a pin input (rising, falling, or both edges)

(Continued) *1 : It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used. Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. *2 : Varies with conditions such as the operating frequency. (See section “n Electrical Characteristics.”) Features MB90591/591G/594/594G MB90F591A/F591G/ F594A/F594G MB90V590A/V590G CAN Interface Number of channels : 2 Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID’s Supports multiple messages Flexible configuration of acceptance filtering : Full bit compare / Full bit mask / Two partial bit masks Supports up to 1Mbps CAN bit timing setting : MB90xxx : TSEG2 ‡ RSJW +2TQ MB90xxxG : TSEG2 ‡ RSJW Stepping motor controller (4 channels) Four high current outputs for each channel Synchronized two 8-bit PWM’s for each channel External interrupt circuitNumber of inputs : 8 Started by a rising edge, a falling edge, an “H” level input, or an “L” level input. Sound generator 8-bit PWM signal is mixed with tone frequency from 8-bit reload counter PWM frequency : 62.5K, 31.2K, 15.6K, 7.8KHz (at System clock = 16MHz) Tone frequency : PWM frequency / 2 / (reload value + 1) Extended I/O serial interface Clock synchronized transmission (31.25K/62.5K/125K/500K/1Mbps at machine clock frequency of 16 MHz) LSB first/MSB first Clock timer Directly operates with the system clock Read/Write accessible Second/Minute/Hour registers Watchdog timer Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Flash Memory Supports automatic programming, Embedded Algorithm TM and Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Writer from Minato Electronics Inc. Low-power consumption (stand-by) mode Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by Process CMOS Power supply voltage for operation*

5 V–10 % (MB90V590A , MB90F594A , MB90594 , MB90V590G,

MB90F594G, MB90594G)

5 V–5 % (MB90F591G, MB90591G, MB90F591A, MB90591)

C P47/SOT3 P46/SCK3 P45/SCIN3 Vcc P44/SIN2 P43/SCK2 P42/SOT2 P41/SOT1 P40/SCK1 P37/SIN1 P36/SIN0 P35/SCK0 P34/SOT0 P33 P32 Vss (Top view) (FPT-100P-M06)

(Continued) No. Pin name Circuit type Function 82 X0 A Oscillator pin 83 X1

77 RST B Reset input

52 HST C Hardware standby input

D General purpose I/O IN0 to IN5 Inputs for the Input Captures 91 to 96 P06 to P07, P10 to P13 D General purpose I/O OUT0 to OUT5 Outputs for the Output Compares. To enable the signal outputs, the corresponding bits of the Port Direc- tion registers should be set to “1”. P14 D General purpose I/O RX1 RX input for CAN Interface 1 P15 D General purpose I/O TX1 TX output for CAN Interface 1. To enable the signal output, the corresponding bit of the Port Direction register should be set to “1”. P16 D General purpose I/O SGO SGO output for the Sound Generator. To enable the signal output, the corresponding bit of the Port Direction register should be set to “1”. 100 P17 D General purpose I/O SGA SGA output for the Sound Generator. To enable the signal output, the corresponding bit of the Port Direction register should be set to “1”. 1 to 4 P20 to P23 D General purpose I/O 5 to 8 P24 to P27 D General purpose I/O INT4 to INT7 External interrupt input for INT4 to INT7 9 to 10 P30 to P31 D General purpose I/O 12 to 13 P32 to P33 D General purpose I/O P34 D General purpose I/O SOT0 SOT output for UART 0. To enable the signal output, the corresponding bit of the Port Direction register should be set to “1”. P35 D General purpose I/O SCK0 SCK input/output for UART 0. To enable the signal output, the corresponding bit of the Port Direction register should be set to “1”.

(Continued) No. Pin name Circuit type Function P36 D General purpose I/O SIN0 SIN input for UART 0 P37 D General purpose I/O SIN1 SIN input for UART 1 P40 D General purpose I/O SCK1 SCK input/output for UART 1 P41 D General purpose I/O SOT1 SOT output for UART 1 P42 D General purpose I/O SOT2 SOT output for UART 2 P43 D General purpose I/O SCK2 SCK input/output for UART 2 P44 D General purpose I/O SIN2 SIN input for UART 2 P45 D General purpose I/O SIN3 SIN input for the Serial I/O P46 D General purpose I/O SCK3 SCK input/output for the Serial I/O P47 D General purpose I/O SOT3 SOT output for the Serial I/O 28 to 33 P50 to P55 D General purpose I/O PPG0 to PPG5, ADTG Outputs for the Programmable Pulse Generators. Pin number 33 is also shared with ADTG input for the external trigger of the A/D Converter. 38 to 41 P60 to P63 E General purpose I/O AN0 to AN3 Inputs for the A/D Converter 43 to 46 P64 to P67 E General purpose I/O AN4 to AN7 Inputs for the A/D Converter P56 D General purpose I/O TIN TIN input for the 16-bit Reload Timers P57 D General purpose I/O TOT/WOT TOT output for the 16-bit Reload Timers and WOT output for the Watch Timer. Only one of three output enable flags in these periph- eral blocks can be set at a time. Otherwise the output signal has no meaning.

(Continued) No. Pin name Circuit type Function 54 to 57 P70 to P73 F General purpose I/O PWM1P0, PWM1M0, PWM2P0, PWM2M0 Output for Stepping Motor Controller channel 0. 59 to 62 P74 to P77 F General purpose I/O PWM1P1, PWM1M1, PWM2P1, PWM2M1 Output for Stepping Motor Controller channel 1. 64 to 67 P80 to P83 F General purpose I/O PWM1P2, PWM1M2, PWM2P2, PWM2M2 Output for Stepping Motor Controller channel 2. 69 to 72 P84 to P87 F General purpose I/O PWM1P3, PWM1M3, PWM2P3, PWM2M3 Output for Stepping Motor Controller channel 3. P90 D General purpose I/O TX0 TX output for CAN Interface 0 P91 D General purpose I/O RX0 RX input for CAN Interface 0 P92 D General purpose I/O INT0 External interrupt input for INT0 P93 D General purpose I/O INT1 External interrupt input for INT1 P94 D General purpose I/O INT2 External interrupt input for INT2 P95 D General purpose I/O INT3 External interrupt input for INT3 58, 68 DV CC ¾ Dedicated power supply pins for the high current output buffers (Pin No. 54 to 72) 53, 63, 73 DV SS ¾ Dedicated ground pins for the high current output buffers (Pin No. 54 to 72)

34 AV CC

Power supply for analog circuit pin When turning this power supply on or off, always be sure to first apply electric potential equal to or greater than AV CC to VCC .

37 AV SS

supply Ground level for analog circuit

(Continued) No. Pin name Circuit type Function

35 AVRH Power

Reference voltage input pin for analog circuit When turning this power supply on or off, always be sure to first apply electric potential equal to or greater than AVRH to AV CC .

36 AVRL Power

supply Reference voltage input pin for analog circuit 49, 50 MD0, MD1 C Operating mode selection input pins Connect directly to VCC or VSS .

51 MD2 G Operating mode selection input pin

Connect directly to VCC or VSS . 27 C ¾ This is the power supply stabilization capacitor pin. It should be con- nected externally to an 0.1 mF ceramic capacitor. 23, 84 V CC Power supply Power supply (5.0 V) input pin for digital circuit 11,42,81 V SS Power supply Power supply (GND) input pin for digital circuit

(Continued) Circuit Type Circuit Remarks A

• Oscillation feedback resistor : 1 MW approx. B
• Hysteresis input with pull-up resistor : 50 kW approx. C
• Hysteresis input D
• C M O S o u t p u t
• Hysteresis input HARD,SOFT STANDBY CONTROL Clock Input HYS R (pull-up) R HYSR HYS VCC P-ch N-ch R

(Continued) Circuit Type Circuit Remarks E

• C M O S o u t p u t
• Hysteresis input
• Analog input F
• CMOS high current output
• Hysteresis input G
• Hysteresis input with pull-down resistor : 50 kW approx.
• Flash version does not have pull-down resistor. Analog input HYS P-ch N-ch R Vcc P-ch N-ch HYS High current P-ch N-ch R HYSR R (pull-down)

(1) Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions :

• A voltage higher than Vcc or lower than Vss is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between Vcc and Vss.
• The AVcc power supply is applied before the Vcc voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, also be careful not to let the analog power-supply voltage (AVCC , AVRH) exceed the digital power-supply voltage. (2) Treatment of unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefor they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kW . Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. (3) Using external clock T o use external clock, drive X0 pin only and leave X1 pin unconnected. Below is a diagram of how to use external clock. Using external clock MB90590/590G Series

(4)Power supply pins (Vcc/Vss) In products with multiple VCC or VSS pins, pins with the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect V CC and VSS pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 mF between VCC and VSS pin near the device. (5) Pull-up/down resistors The MB90590/590G Series does not support internal pull-up/down resistors. Use external components where needed. (6) Crystal Oscillator Circuit Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure that lines of oscillation circuits do not cross the lines of other circuits. A printed circuit board artwork surrounding the X0 and X1 pins with a ground area for stabilizing the operation is highly recommended. (7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AV CC , AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC ). T urn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simulta- neously is acceptable). (8) Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC , AVSS = AVRH = VSS . Vcc Vss Vss Vcc Vss Vcc MB90590/590G Series Vcc Vss VccVss

(9) N.C. Pin The N.C. (internally connected) pin must be opened for use. (10) Notes on Energization T o prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 ms or more (0.2 V to 2.7 V). (11) Indeterminate outputs from ports 0 and 1 (without MB90F591G/591G, MB90F594G) During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the outputs from ports 0 and 1 become following state.

• I f R S T pin is “H”, the outputs become indeterminate.
• I f R S T pin is “L”, the outputs become high-impedance. Pay attention to the port output timing shown as follow. Oscillation setting time*2 Power-on reset*1 Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal Period of indeterminated *1 : Power-on reset time : Period of “clock frequency · 217” (Clock frequency of 16 MHz : 8.19 ms) *2 : Oscillation setting time : Period of “clock frequency · 218” (Clock frequency of 16 MHz : 16.38ms) RST pin is “H” Oscillation setting time*2 Power-on reset*1 Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal High-impedance *1 : Power-on reset time : Period of “clock frequency · 217” (Clock frequency of 16 MHz : 8.19 ms) *2 : Oscillation setting time : Period of “clock frequency · 218” (Clock frequency of 16 MHz : 16.38ms) RST pin is “L”

(12) Initialization The device contains internal registers which are initialized only by a power-on reset. T o initialize these registers, please turn on the power again. (13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”), the value of the corre- sponding bank register (DTB, ADB, USB, SSB) is set in “00 H ”. If the values of the corresponding bank registers (DTB,ADB,USB,SSB) are set to other than “00 H ”, the remainder by the execution result of the instruction is not stored in the register of the instruction operand. (14) Using REALOS The use of EI2OS is not possible with the REALOS real time operating system. (15) Caution on Operations during PLL Clock Mode If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the free- running frequency of the automatic oscillating circuit in the PLL circuitry even if the oscillator is out of place or the clock input is stopped. Performance of this operation, however, cannot be guaranteed.

Prescaler · 3 Watch 10-bit ADC 8ch Sound Generator 16-bit Clock Controller 16-bit Input Capture 6ch 16-bit Output Compare 4ch CAN 2ch External Interrupt 8/16-bit PPG 6ch F2MC-16LX CPU F2MC-16 Bus X0,X1 RST HST SOT0 to SOT2 SCK0 to SCK2 SIN0 to SIN2 AVCC AVSS AN0 to AN7 AVRH AVRL ADTG SGO SGA IN0 to IN5 OUT0 to OUT5 PPG0 to PPG5 RX0, RX1 TX0, TX1 INT0 to INT7 Serial I/O Prescaler SOT3 SCK3 SIN3 SMC 4ch PWM1M0 to PWM1M3 PWM1P0 to PWM1P3 PWM2M0 to PWM2M3 PWM2P0 to PWM2P3 DVCC DVSS

256 K/384 K

The memory space of the MB90590/590G Series is shown below Memory space map Note : The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same address, enabling reference of the table on the ROM without stating “far”. For example, if an attempt has been made to access 00C000 H , the contents of the ROM at FFC000H are accessed. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000 H to FFFFFFH looks, therefore, as if it were the image for 004000H to 00FFFFH . Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFF H . MB90V590A/V590G MB90594/F594A/ 594G/F594G MB90591/F591A/ 591G/F591G FFFFFF H FF0000H ROM (FF bank) FFFFFF H FF0000H ROM (FF bank) FFFFFF H FF0000H ROM (FF bank) FEFFFF H FE0000 H ROM (FE bank) FEFFFF H FE0000 H ROM (FE bank) FEFFFF H FE0000 H ROM (FE bank) FDFFFF H FD0000 H ROM (FD bank) FDFFFF H FD0000 H ROM (FD bank) FDFFFF H FD0000 H ROM (FD bank) FCFFFF H FC0000 H ROM (FC bank) FCFFFF H FC0000 H ROM (FC bank) FCFFFF H FC0000 H FBFFFF H FB0000 H ROM (FB bank) FBFFFF H FB0000 H ROM (FB bank) FAFFFF H FA0000 H ROM (FA bank) FAFFFF H FA0000 H ROM (FA bank) F9FFFF H F90000H ROM (F9 bank) F9FFFF H F90000H ROM (F9 bank) 00FFFF H 004000H ROM (Image of FF bank) 00FFFF H 004000H ROM (Image of FF bank) 00FFFF H 004000H ROM (Image of FF bank) 0028FFH 002100H RAM 2K 0028FFH 002100H RAM 2K 0020FFH 0020FFH 001FFF H 001900H Peripheral 001FFF H 001900H Peripheral 001FFF H 001900H Peripheral 0018FFH 000100H RAM 6K 0018FFH 000100H RAM 6K 0018FFH 000100H RAM 6K 0000BF H 000000H Peripheral 0000BF H 000000H Peripheral 0000BF H 000000H Peripheral

(Continued) Address Register Abbreviation Access Peripheral Initial value 00H Port 0 Data Register PDR0 R/W Port 0 XXXXXXXX B 01H Port 1 Data Register PDR1 R/W Port 1 XXXXXXXX B 02H Port 2 Data Register PDR2 R/W Port 2 XXXXXXXX B 03H Port 3 Data Register PDR3 R/W Port 3 XXXXXXXX B 04H Port 4 Data Register PDR4 R/W Port 4 XXXXXXXX B 05H Port 5 Data Register PDR5 R/W Port 5 XXXXXXXX B 06H Port 6 Data Register PDR6 R/W Port 6 XXXXXXXX B 07H Port 7 Data Register PDR7 R/W Port 7 XXXXXXXX B 08H Port 8 Data Register PDR8 R/W Port 8 XXXXXXXX B 09H Port 9 Data Register PDR9 R/W Port 9 _ _ XXXXXX B 0AH to 0FH Reserved 10H Port 0 Direction Register DDR0 R/W Port 0 0 0 0 0 0 0 0 0 B 11H Port 1 Direction Register DDR1 R/W Port 1 0 0 0 0 0 0 0 0 B 12H Port 2 Direction Register DDR2 R/W Port 2 0 0 0 0 0 0 0 0 B 13H Port 3 Direction Register DDR3 R/W Port 3 0 0 0 0 0 0 0 0 B 14H Port 4 Direction Register DDR4 R/W Port 4 0 0 0 0 0 0 0 0 B 15H Port 5 Direction Register DDR5 R/W Port 5 0 0 0 0 0 0 0 0 B 16H Port 6 Direction Register DDR6 R/W Port 6 0 0 0 0 0 0 0 0 B 17H Port 7 Direction Register DDR7 R/W Port 7 0 0 0 0 0 0 0 0 B 18H Port 8 Direction Register DDR8 R/W Port 8 0 0 0 0 0 0 0 0 B 19H Port 9 Direction Register DDR9 R/W Port 9 _ _ 0 0 0 0 0 0 B 1AH Reserved 1BH Analog Input Enable Register ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1 B 1C H to 1FH Reserved 20H Serial Mode Control Register 0 UMC0 R/W UART0 0 0 0 0 0 1 0 0B 21H Serial Status Register 0 USR0 R/W 0 0 0 1 0 0 0 0 B 22H Serial Input/Output Data Register 0UIDR0/ UODR0 R/W XXXXXXXX B 23H Rate and Data Register 0 URD0 R/W 0 0 0 0 0 0 0X B 24H Serial Mode Control Register 1 UMC1 R/W UART1 0 0 0 0 0 1 0 0B 25H Serial Status Register 1 USR1 R/W 0 0 0 1 0 0 0 0 B 26H Serial Input/Output Data Register 1UIDR1/ UODR1 R/W XXXXXXXX B 27H Rate and Data Register 1 URD1 R/W 0 0 0 0 0 0 0X B

(Continued) Address Register Abbreviation Access Peripheral Initial value 28H Serial Mode Control Register 2 UMC2 R/W UART2 0 0 0 0 0 1 0 0B 29H Serial Status Register 2 USR2 R/W 0 0 0 1 0 0 0 0 B 2AH Serial Input/Output Data Register 2 UIDR2/ UODR2 R/W XXXXXXXX B 2BH Rate and Data Register 2 URD2 R/W 0 0 0 0 0 0 0X B 2C H Serial Mode Control Register (low-order) SMCS R/W Serial I/O _ _ _ _0 0 0 0B 2D H Serial Mode Control Register (high-order) SMCS R/W 0 0 0 0 0 0 1 0 B 2EH Serial Data Register SDR R/W XXXXXXXX B 2FH Edge Selector Register SES R/W _ _ _ _ _ _ _0 B 30H External Interrupt Enable Register ENIR R/W External Interrupt 0 0 0 0 0 0 0 0B 31H External Interrupt Request RegisterEIRR R/W XXXXXXXX B 32H External Interrupt Level Register ELVR R/W 0 0 0 0 0 0 0 0 B 33H External Interrupt Level Register ELVR R/W 0 0 0 0 0 0 0 0 B 34H A/D Control Status Register 0 ADCS0 R/W A/D Converter 0 0 0 0 0 0 0 0B 35H A/D Control Status Register 1 ADCS1 R/W 0 0 0 0 0 0 0 0 B 36H A/D Data Register 0 ADCR0 R XXXXXXXX B 37H A/D Data Register 1 ADCR1 R/W 0 0 0 0 1 0 XX B 38H PPG0 Operation Mode Control Register PPGC0 R/W 16-bit Programmable Pulse Generator 0/1 0 _ 0 0 0 _ _ 1B 39H PPG1 Operation Mode Control Register PPGC1 R/W 0 _ 0 0 0 0 0 1 B 3AH PPG0,1 Output Pin Control RegisterPPG01 R/W 0 0 0 0 0 0 0 0 B 3BH Reserved 3C H PPG2 Operation Mode Control Register PPGC2 R/W 16-bit Programmable Pulse Generator 2/3 0 _ 0 0 0 _ _1B 3D H PPG3 Operation Mode Control Register PPGC3 R/W 0 _ 0 0 0 0 0 1 B 3EH PPG2,3 Output Pin Control RegisterPPG23 R/W 0 0 0 0 0 0 0 0 B 3FH Reserved 40H PPG4 Operation Mode Control Register PPGC4 R/W 16-bit Programmable Pulse Generator 4/5 0 _ 0 0 0 _ _ 1B 41H PPG5 Operation Mode Control Register PPGC5 R/W 0 _ 0 0 0 0 0 1 B 42H PPG4,5 Output Pin Control RegisterPPG45 R/W 0 0 0 0 0 0 0 0 B 43H Reserved 44H PPG6 Operation Mode Control Register PPGC6 R/W 16-bit Programmable Pulse Generator 6/7 0 _ 0 0 0 _ _ 1B 45H PPG7 Operation Mode Control Register PPGC7 R/W 0 _ 0 0 0 0 0 1 B 46H PPG6,7 Output Pin Control RegisterPPG67 R/W 0 0 0 0 0 0 0 0 B 47H Reserved

(Continued) Address Register Abbreviation Access Peripheral Initial value 48H PPG8 Operation Mode Control Register PPGC8 R/W 16-bit Programmable Pulse Generator 8/9 0 _ 0 0 0 _ _ 1B 49H PPG9 Operation Mode Control Register PPGC9 R/W 0 _ 0 0 0 0 0 1 B 4AH PPG8,9 Output Pin Control RegisterPPG89 R/W 0 0 0 0 0 0 0 0 B 4BH Reserved 4C H PPGA Operation Mode Control RegisterPPGCA R/W 16-bit Programmable Pulse Generator A/B 0 _ 0 0 0 _ _ 1B 4D H PPGB Operation Mode Control RegisterPPGCB R/W 0 _ 0 0 0 0 0 1 B 4EH PPGA,B Output Pin Control RegisterPPGAB R/W 0 0 0 0 0 0 0 0 B 4FH Reserved 50H Timer Control Status Register 0 (low-order) TMCSR0 R/W 16-bit Reload Timer 0 0 0 0 0 0 0 0 0B 51H Timer Control Status Register 0 (high-order) TMCSR0 R/W _ _ _ _ 0 0 0 0 B 52H Timer Control Status Register 1 (low-order) TMCSR1 R/W 16-bit Reload Timer 1 0 0 0 0 0 0 0 0B 53H Timer Control Status Register 1 (high-order) TMCSR1 R/W _ _ _ _ 0 0 0 0 B 54H Input Capture Control Status Register 0/1 ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0 B 55H Input Capture Control Status Register 2/3 ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0 B 56H Input Capture Control Status Register 4/5 ICS45 R/W Input Capture 4/5 0 0 0 0 0 0 0 0 B 57H Reserved 58H Output Compare Control Status Register 0 OCS0 R/W Output Compare 0/1 0 0 0 0 _ _ 0 0B 59H Output Compare Control Status Register 1 OCS1 R/W _ _ _0 0 0 0 0 B 5AH Output Compare Control Status Register 2 OCS2 R/W Output Compare 2/3 0 0 0 0 _ _ 0 0B 5BH Output Compare Control Status Register 3 OCS3 R/W _ _ _ 0 0 0 0 0 B 5C H Output Compare Control Status Register 4 OCS4 R/W Output Compare 4/5 0 0 0 0 _ _ 0 0B 5D H Output Compare Control Status Register 5 OCS5 R/W _ _ _ 0 0 0 0 0 B 5EH Sound Control Register (low-order)SGCR R/W Sound Generator 0 0 0 0 0 0 0 0B 5FH Sound Control Register (high-order)SGCR R/W 0 _ _ _ _ _ _ 0 B

(Continued) Address Register Abbreviation Access Peripheral Initial value 60H Watch Timer Control Register (low-order) WTCR R/W Watch Timer 0 0 0 _ _ 0 0 0B 61H Watch Timer Control Register (high-order) WTCR R/W 0 0 0 0 0 0 0 0 B 62H PWM Control Register 0 PWC0 R/W Stepping Motor Controller 0 0 0 0 0 0 _ _ 0B 63H Reserved 64H PWM Control Register 1 PWC1 R/W Stepping Motor Controller 1 0 0 0 0 0 _ _ 0B 65H Reserved 66H PWM Control Register 2 PWC2 R/W Stepping Motor Controller 2 0 0 0 0 0 _ _ 0B 67H Reserved 68H PWM Control Register 3 PWC3 R/W Stepping Motor Controller 3 0 0 0 0 0 _ _ 0B 69H to 6CH Reserved 6D H Serial I/O Prescaler Register CDCR R/W Prescaler (Serial I/O) 0 XXX 1 1 1 1 B 6EH Timer Control Status Register TCCS R/W I/O Timer 0 0 0 0 0 0 0 0 B 6FH ROM Mirror Function Select Register ROMM W ROM Mirror XXXXXXX1 B 70H to 8FH Reserved for CAN Interface 0/1. Refer to section about CAN Controller 90H to 9DH Reserved 9EH Program Address Detection Control Status Register PACSR R/W Address Match Detection Function0 0 0 0 0 0 0 0B 9FH Delayed Interrupt/Release Register DIRR R/W Delayed Interrupt _ _ _ _ _ _ _ 0 B A0H Low Power Mode Control Register LPMCR R/W Low Power Controller 0 0 0 1 1 0 0 0 B A1H Clock Selection Register CKSCR R/W Low Power Controller 1 1 1 1 1 1 0 0 B A2H to A7H Reserved A8H Watchdog Timer Control Register WDTC R/W Watchdog Timer XXXXX 1 1 1 B A9H Time Base Timer Control Register TBTC R/W Time Base Timer 1 - - 0 0 1 0 0 B AA H to ADH Reserved AE H Flash Memory Control Status Register (Flash product only. Otherwise reserved) FMCS R/W Flash Memory 0 0 0 X 0 0 0 0 B AF H Reserved

(Continued) Address Register Abbreviation Access Peripheral Initial value B0H Interrupt Control Register 00 ICR00 R/W Interrupt controller 0 0 0 0 0 1 1 1B B1H Interrupt Control Register 01 ICR01 R/W 0 0 0 0 0 1 1 1 B B2H Interrupt Control Register 02 ICR02 R/W 0 0 0 0 0 1 1 1 B B3H Interrupt Control Register 03 ICR03 R/W 0 0 0 0 0 1 1 1 B B4H Interrupt Control Register 04 ICR04 R/W 0 0 0 0 0 1 1 1 B B5H Interrupt Control Register 05 ICR05 R/W 0 0 0 0 0 1 1 1 B B6H Interrupt Control Register 06 ICR06 R/W 0 0 0 0 0 1 1 1 B B7H Interrupt Control Register 07 ICR07 R/W 0 0 0 0 0 1 1 1 B B8H Interrupt Control Register 08 ICR08 R/W 0 0 0 0 0 1 1 1 B B9H Interrupt Control Register 09 ICR09 R/W 0 0 0 0 0 1 1 1 B BA H Interrupt Control Register 10 ICR10 R/W 0 0 0 0 0 1 1 1 B BB H Interrupt Control Register 11 ICR11 R/W 0 0 0 0 0 1 1 1 B BC H Interrupt Control Register 12 ICR12 R/W 0 0 0 0 0 1 1 1 B BD H Interrupt Control Register 13 ICR13 R/W 0 0 0 0 0 1 1 1 B BE H Interrupt Control Register 14 ICR14 R/W 0 0 0 0 0 1 1 1 B BF H Interrupt Control Register 15 ICR15 R/W 0 0 0 0 0 1 1 1 B C0 H to FFH Reserved 1900H Reload L Register PRLL0 R/W 16-bit Programmable Pulse Generator 0/1 XXXXXXXX B 1901H Reload H Register PRLH0 R/W XXXXXXXX B 1902H Reload L Register PRLL1 R/W XXXXXXXX B 1903H Reload H Register PRLH1 R/W XXXXXXXX B 1904H Reload L Register PRLL2 R/W 16-bit Programmable Pulse Generator 2/3 XXXXXXXX B 1905H Reload H Register PRLH2 R/W XXXXXXXX B 1906H Reload L Register PRLL3 R/W XXXXXXXX B 1907H Reload H Register PRLH3 R/W XXXXXXXX B 1908H Reload L Register PRLL4 R/W 16-bit Programmable Pulse Generator 4/5 XXXXXXXX B 1909H Reload H Register PRLH4 R/W XXXXXXXX B 190AH Reload L Register PRLL5 R/W XXXXXXXX B 190BH Reload H Register PRLH5 R/W XXXXXXXX B 190C H Reload L Register PRLL6 R/W 16-bit Programmable Pulse Generator 6/7 XXXXXXXX B 190D H Reload H Register PRLH6 R/W XXXXXXXX B 190EH Reload L Register PRLL7 R/W XXXXXXXX B 190FH Reload H Register PRLH7 R/W XXXXXXXX B

(Continued) Address Register Abbreviation Access Peripheral Initial value 1910H Reload L Register PRLL8 R/W 16-bit Programmable Pulse Generator 8/9 XXXXXXXX B 1911H Reload H Register PRLH8 R/W XXXXXXXX B 1912H Reload L Register PRLL9 R/W XXXXXXXX B 1913H Reload H Register PRLH9 R/W XXXXXXXX B 1914H Reload L Register PRLLA R/W 16-bit Programmable Pulse Generator A/B XXXXXXXX B 1915H Reload H Register PRLHA R/W XXXXXXXX B 1916H Reload L Register PRLLB R/W XXXXXXXX B 1917H Reload H Register PRLHB R/W XXXXXXXX B 1918H to 191FH Reserved 1920H Input Capture Register 0 (low-order) IPCP0 R Input Capture 0/1 XXXXXXXX B 1921H Input Capture Register 0 (high-order) IPCP0 R XXXXXXXX B 1922H Input Capture Register 1 (low-order) IPCP1 R XXXXXXXX B 1923H Input Capture Register 1 (high-order) IPCP1 R XXXXXXXX B 1924H Input Capture Register 2 (low-order) IPCP2 R Input Capture 2/3 XXXXXXXX B 1925H Input Capture Register 2 (high-order) IPCP2 R XXXXXXXX B 1926H Input Capture Register 3 (low-order) IPCP3 R XXXXXXXX B 1927H Input Capture Register 3 (high-order) IPCP3 R XXXXXXXX B 1928H Input Capture Register 4 (low-order) IPCP4 R Input Capture 4/5 XXXXXXXX B 1929H Input Capture Register 4 (high-order) IPCP4 R XXXXXXXX B 192AH Input Capture Register 5 (low-order) IPCP5 R XXXXXXXX B 192BH Input Capture Register 5 (high-order) IPCP5 R XXXXXXXX B 192C H to 192FH Reserved

(Continued) Address Register Abbreviation Access Peripheral Initial value 1930H Output Compare Register 0 (low-order) OCCP0 R/W Output Compare XXXXXXXX B 1931H Output Compare Register 0 (high-order) OCCP0 R/W XXXXXXXX B 1932H Output Compare Register 1 (low-order) OCCP1 R/W XXXXXXXX B 1933H Output Compare Register 1 (high-order) OCCP1 R/W XXXXXXXX B 1934H Output Compare Register 2 (low-order) OCCP2 R/W Output Compare XXXXXXXX B 1935H Output Compare Register 2 (high-order) OCCP2 R/W XXXXXXXX B 1936H Output Compare Register 3 (low-order) OCCP3 R/W XXXXXXXX B 1937H Output Compare Register 3 (high-order) OCCP3 R/W XXXXXXXX B 1938H Output Compare Register 4 (low-order) OCCP4 R/W Output Compare XXXXXXXX B 1939H Output Compare Register 4 (high-order) OCCP4 R/W XXXXXXXX B 193AH Output Compare Register 5 (low-order) OCCP5 R/W XXXXXXXX B 193BH Output Compare Register 5 (high-order) OCCP5 R/W XXXXXXXX B 193C H to 193FH Reserved 1940H Timer 0/Reload Register 0 (low-order) TMR0/ TMRLR0 R/W 16-bit Reload Timer 0 XXXXXXXX B 1941H Timer 0/Reload Register 0 (high-order) TMR0/ TMRLR0 R/W XXXXXXXX B 1942H Timer 1/Reload Register 1 (low-order) TMR1/ TMRLR1 R/W 16-bit Reload Timer 1 XXXXXXXX B 1943H Timer 1/Reload Register 1 (high-order) TMR1/ TMRLR1 R/W XXXXXXXX B 1944H Timer Data Register (low-order) TCDT R/W I/O Timer 0 0 0 0 0 0 0 0 B 1945H Timer Data Register (high-order) TCDT R/W 0 0 0 0 0 0 0 0 B 1946H Frequency Data Register SGFR R/W Sound Generator XXXXXXXX B 1947H Amplitude Data Register SGAR R/W XXXXXXXX B 1948H Decrement Grade Register SGDR R/W XXXXXXXX B 1949H Tone Count Register SGTR R/W XXXXXXXX B

(Continued) Address Register Abbreviation Access Peripheral Initial value 194AH Sub-second Data Register (low-order) WTBR R/W Watch Timer XXXXXXXX B 194BH Sub-second Data Register (middle-order) WTBR R/W XXXXXXXX B 194C H Sub-second Data Register (high-order) WTBR R/W _ _ _ XXXXX B 194D H Second Data Register WTSR R/W _ _ 0 0 0 0 0 0 B 194EH Minute Data Register WTMR R/W Watch Timer _ _ 0 0 0 0 0 0 B 194FH Hour Data Register WTHR R/W _ _ _ 0 0 0 0 0 B 1950H PWM1 Compare Register 0 PWC10 R/W Stepping Motor Controller 0 XXXXXXXX B 1951H PWM2 Compare Register 0 PWC20 R/W XXXXXXXX B 1952H PWM1 Select Register 0 PWS10 R/W _ _ 0 0 0 0 0 0 B 1953H PWM2 Select Register 0 PWS20 R/W _ 0 0 0 0 0 0 0 B 1954H PWM1 Compare Register 1 PWC11 R/W Stepping Motor Controller 1 XXXXXXXX B 1955H PWM2 Compare Register 1 PWC21 R/W XXXXXXXX B 1956H PWM1 Select Register 1 PWS11 R/W _ _ 0 0 0 0 0 0 B 1957H PWM2 Select Register 1 PWS21 R/W _ 0 0 0 0 0 0 0 B 1958H PWM1 Compare Register 2 PWC12 R/W Stepping Motor Controller 2 XXXXXXXX B 1959H PWM2 Compare Register 2 PWC22 R/W XXXXXXXX B 195AH PWM1 Select Register 2 PWS12 R/W _ _ 0 0 0 0 0 0 B 195BH PWM2 Select Register 2 PWS22 R/W _ 0 0 0 0 0 0 0 B 195C H PWM1 Compare Register 3 PWC13 R/W Stepping Motor Controller 3 XXXXXXXX B 195D H PWM2 Compare Register 3 PWC23 R/W XXXXXXXX B 195EH PWM1 Select Register 3 PWS13 R/W _ _ 0 0 0 0 0 0 B 195FH PWM2 Select Register 3 PWS23 R/W _0 0 0 0 0 0 0 B 1960H to 19FFH Reserved 1A00H to 1AFFH Reserved for CAN Interface 0. Refer to section about CAN Controller 1B00H to 1BFFH Reserved for CAN Interface 1. Refer to section about CAN Controller 1C00 H to 1CFFH Reserved for CAN Interface 0. Refer to section about CAN Controller 1D00 H to 1DFFH Reserved for CAN Interface 1. Refer to section about CAN Controller 1E00H to 1EFFH Reserved

(Continued) Note : Initial value of “_” represents unused bit; “X” represents unknown value. Addresses in the rage 0000H to 00FFH , which are not listed in the table, are reserved for the primary functions of the MCU. A read access to these reserved addresses results in reading “X”, and any write access should not be performed. Address Register Abbreviation Access Peripheral Initial value 1FF0 H Program Address Detection Register 0 (low-order) PADR0 R/W Address Match Detection Function XXXXXXXX B 1FF1H Program Address Detection Register 0 (middle-order) PADR0 R/W XXXXXXXX B 1FF2H Program Address Detection Register 0 (high-order) PADR0 R/W XXXXXXXX B 1FF3H Program Address Detection Register 1 (low-order) PADR1 R/W XXXXXXXX B 1FF4H Program Address Detection Register 1 (middle-order) PADR1 R/W XXXXXXXX B 1FF5H Program Address Detection Register 1 (high-order) PADR1 R/W XXXXXXXX B 1FF6H to 1FFFH Reserved

The CAN controller has the following features : Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats

• Supports transmission of data frames by receiving remote frames
• 16 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as 1D acceptance mask - T wo acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbit/s to 2 Mbit/s (when input clock is at 16 MHz) List of Control Registers Address Register Abbreviation Access Initial Value CAN0 CAN1 000070H 000080H Message buffer valid register BVALR R/W 00000000 00000000 B 000071H 000081H 000072H 000082H Transmit request register TREQR R/W 00000000 00000000 B 000073H 000083H 000074H 000084H Transmit cancel register TCANR W 00000000 00000000 B 000075H 000085H 000076H 000086H Transmit complete register TCR R/W 00000000 00000000 B 000077H 000087H 000078H 000088H Receive complete register RCR R/W 00000000 00000000 B 000079H 000089H 00007AH 00008AH Remote request receiving register RRTRR R/W 00000000 00000000 B 00007BH 00008BH 00007C H 00008C H Receive overrun register ROVRR R/W 00000000 00000000 B 00007D H 00008D H 00007EH 00008EH Receive interrupt enable register RIER R/W 00000000 00000000 B 00007FH 00008FH

Register Abbreviation Access Initial Value CAN0 CAN1 001C00 H 001D00 H Control status register CSR R/W, R 00---000 0----0-1 B 001C01 H 001D01 H 001C02 H 001D02 H 001C03 H 001D03 H 001C04 H 001D04 H Receive/transmit error counter RTEC R 00000000 00000000 B 001C05 H 001D05 H 001C06 H 001D06 H Bit timing register BTR R/W -1111111 11111111 B 001C07 H 001D07 H 001C08 H 001D08 H IDE register IDER R/W XXXXXXXX XXXXXXXX B001C09 H 001D09 H 001C0A H 001D0A H Transmit RTR register TRTRR R/W 00000000 00000000 B 001C0B H 001D0B H 001C0C H 001D0C H Remote frame receive waiting register RFWTR R/W XXXXXXXX XXXXXXXX B001C0D H 001D0D H 001C0E H 001D0E H Transmit interrupt enable register TIER R/W 00000000 00000000 B 001C0F H 001D0F H 001C10 H 001D10 H Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXX B001C11 H 001D11 H 001C12 H 001D12 H XXXXXXXX XXXXXXXX B001C13 H 001D13 H 001C14 H 001D14 H Acceptance mask register 0 AMR0 R/W XXXXXXXX XXXXXXXX B001C15 H 001D15 H 001C16 H 001D16 H XXXXX--- XXXXXXXX B 001C17 H 001D17 H 001C18 H 001D18 H Acceptance mask register 1 AMR1 R/W XXXXXXXX XXXXXXXX B001C19 H 001D19 H 001C1A H 001D1A H XXXXX--- XXXXXXXX B 001C1B H 001D1B H

List of Message Buffers (ID Registers) (Continued) Address Register Abbreviation Access Initial Value CAN0 CAN1 001A20H 001B20H ID register 0 IDR0 R/W XXXXXXXX XXXXXXXX B 001A21H 001B21H 001A22H 001B22H XXXXX--- XXXXXXXX B 001A23H 001B23H 001A24H 001B24H ID register 1 IDR1 R/W XXXXXXXX XXXXXXXX B 001A25H 001B25H 001A26H 001B26H XXXXX--- XXXXXXXX B 001A27H 001B27H 001A28H 001B28H ID register 2 IDR2 R/W XXXXXXXX XXXXXXXX B 001A29H 001B29H 001A2A H 001B2A H XXXXX--- XXXXXXXX B 001A2B H 001B2B H 001A2C H 001B2C H ID register 3 IDR3 R/W XXXXXXXX XXXXXXXX B 001A2D H 001B2D H 001A2E H 001B2E H XXXXX--- XXXXXXXX B 001A2F H 001B2F H 001A30H 001B30H ID register 4 IDR4 R/W XXXXXXXX XXXXXXXX B 001A31H 001B31H 001A32H 001B32H XXXXX--- XXXXXXXX B 001A33H 001B33H 001A34H 001B34H ID register 5 IDR5 R/W XXXXXXXX XXXXXXXX B 001A35H 001B35H 001A36H 001B36H XXXXX--- XXXXXXXX B 001A37H 001B37H 001A38H 001B38H ID register 6 IDR6 R/W XXXXXXXX XXXXXXXX B 001A39H 001B39H 001A3A H 001B3A H XXXXX--- XXXXXXXX B 001A3B H 001B3B H 001A3C H 001B3C H ID register 7 IDR7 R/W XXXXXXXX XXXXXXXX B 001A3D H 001B3D H 001A3E H 001B3E H XXXXX--- XXXXXXXX B 001A3F H 001B3F H

(Continued) Address Register Abbreviation Access Initial Value CAN0 CAN1 001A40H 001B40H ID register 8 IDR8 R/W XXXXXXXX XXXXXXXX B 001A41H 001B41H 001A42H 001B42H XXXXX--- XXXXXXXX B 001A43F H 001B43H 001A44H 001B44H ID register 9 IDR9 R/W XXXXXXXX XXXXXXXX B 001A45H 001B45H 001A46H 001B46H XXXXX--- XXXXXXXX B 001A47H 001B47H 001A48H 001B48H ID register 10 IDR10 R/W XXXXXXXX XXXXXXXX B 001A49H 001B49H 001A4A H 001B4A H XXXXX--- XXXXXXXX B 001A4B H 001B4B H 001A4C H 001B4C H ID register 11 IDR11 R/W XXXXXXXX XXXXXXXX B 001A4D H 001B4D H 001A4E H 001B4E H XXXXX--- XXXXXXXX B 001A4F H 001B4F H 001A50H 001B50H ID register 12 IDR12 R/W XXXXXXXX XXXXXXXX B 001A51H 001B51H 001A52H 001B52H XXXXX--- XXXXXXXX B 001A53H 001B53H 001A54H 001B54H ID register 13 IDR13 R/W XXXXXXXX XXXXXXXX B 001A55H 001B55H 001A56H 001B56H XXXXX--- XXXXXXXX B 001A57H 001B57H 001A58H 001B58H ID register 14 IDR14 R/W XXXXXXXX XXXXXXXX B 001A59H 001B59H 001A5A H 001B5A H XXXXX--- XXXXXXXX B 001A5B H 001B5B H 001A5C H 001B5C H ID register 15 IDR15 R/W XXXXXXXX XXXXXXXX B 001A5D H 001B5D H 001A5E H 001B5E H XXXXX--- XXXXXXXX B 001A5F H 001B5F H

List of Message Buffers (DLC Registers and Data Registers) (Continued) Address Register Abbreviation Access Initial Value CAN0 CAN1 001A60H 001B60H DLC register 0 DLCR0 R/W ----XXXX B 001A61H 001B61H 001A62H 001B62H DLC register 1 DLCR1 R/W ----XXXX B 001A63H 001B63H 001A64H 001B64H DLC register 2 DLCR2 R/W ----XXXX B 001A65H 001B65H 001A66H 001B66H DLC register 3 DLCR3 R/W ----XXXX B 001A67H 001B67H 001A68H 001B68H DLC register 4 DLCR4 R/W ----XXXX B 001A69H 001B69H 001A6A H 001B6A H DLC register 5 DLCR5 R/W ----XXXX B 001A6B H 001B6B H 001A6C H 001B6C H DLC register 6 DLCR6 R/W ----XXXX B 001A6D H 001B6D H 001A6E H 001B6E H DLC register 7 DLCR7 R/W ----XXXX B 001A6F H 001B6F H 001A70H 001B70H DLC register 8 DLCR8 R/W ----XXXX 001A71H 001B71H 001A72H 001B72H DLC register 9 DLCR9 R/W ----XXXX B 001A73H 001B73H 001A74H 001B74H DLC register 10 DLCR10 R/W ----XXXX B 001A75H 001B75H 001A76H 001B76H DLC register 11 DLCR11 R/W ----XXXX B 001A77H 001B77H 001A78H 001B78H DLC register 12 DLCR12 R/W ----XXXX B 001A79H 001B79H 001A7A H 001B7A H DLC register 13 DLCR13 R/W ----XXXX B 001A7B H 001B7B H 001A7C H 001B7C H DLC register 14 DLCR14 R/W ----XXXX B 001A7D H 001B7D H 001A7E H 001B7E H DLC register 15 DLCR15 R/W ----XXXX B 001A7F H 001B7F H 001A80H to 001A87H 001B80H to 001B87H Data register 0 (8 bytes) DTR0 R/W XXXXXXXX B to XXXXXXXX B

(Continued) Address Register Abbreviation Access Initial Value CAN0 CAN1 001A88H to 001A8F H 001B88H to 001B8F H Data register 1 (8 bytes) DTR1 R/W XXXXXXXX B to XXXXXXXX B 001A90H to 001A97H 001B90H to 001B97H Data register 2 (8 bytes) DTR2 R/W XXXXXXXX B to XXXXXXXX B 001A98H to 001A9F H 001B98H to 001B9F H Data register 3 (8 bytes) DTR3 R/W XXXXXXXX B to XXXXXXXX B 001AA0 H to 001AA7 H 001BA0 H to 001BA7 H Data register 4 (8 bytes) DTR4 R/W XXXXXXXX B to XXXXXXXX B 001AA8 H to 001AAF H 001BA8 H to 001BAF H Data register 5 (8 bytes) DTR5 R/W XXXXXXXX B to XXXXXXXX B 001AB0 H to 001AB7 H 001BB0 H to 001BB7 H Data register 6 (8 bytes) DTR6 R/W XXXXXXXX B to XXXXXXXX B 001AB8 H to 001ABF H 001BB8 H to 001BBF H Data register 7 (8 bytes) DTR7 R/W XXXXXXXX B to XXXXXXXX B 001AC0 H to 001AC7 H 001BC0 H to 001BC7 H Data register 8 (8 bytes) DTR8 R/W XXXXXXXX B to XXXXXXXX B 001AC8 H to 001ACF H 001BC8 H to 001BCF H Data register 9 (8 bytes) DTR9 R/W XXXXXXXX B to XXXXXXXX B 001AD0 H to 001AD7 H 001BD0 H to 001BD7 H Data register 10 (8 bytes) DTR10 R/W XXXXXXXX B to XXXXXXXX B 001AD8 H to 001ADF H 001BD8 H to 001BDF H Data register 11 (8 bytes) DTR11 R/W XXXXXXXX B to XXXXXXXX B 001AE0 H to 001AE7 H 001BE0 H to 001BE7 H Data register 12 (8 bytes) DTR12 R/W XXXXXXXX B to XXXXXXXX B 001AE8 H to 001AEF H 001BE8 H to 001BEF H Data register 13 (8 bytes) DTR13 R/W XXXXXXXX B to XXXXXXXX B 001AF0 H to 001AF7 H 001BF0 H to 001BF7 H Data register 14 (8 bytes) DTR14 R/W XXXXXXXX B to XXXXXXXX B 001AF8 H to 001AFF H 001BF8 H to 001BFF H Data register 15 (8 bytes) DTR15 R/W XXXXXXXX B to XXXXXXXX B

Interrupt vector Interrupt control register Number Address Number Address Reset N/A # 08 FFFFDC H ¾¾ INT9 instruction N/A # 09 FFFFD8 H ¾¾ Exception N/A # 10 FFFFD4 H ¾¾ Time Base Timer N/A # 11 FFFFD0 H ICR00 0000B0 H External Interrupt (INT0 to INT7) *1 # 12 FFFFCC H CAN 0 RX N/A # 13 FFFFC8 H ICR01 0000B1 H CAN 0 TX/NS N/A # 14 FFFFC4 H CAN 1 RX N/A # 15 FFFFC0 H ICR02 0000B2 H CAN 1 TX/NS N/A # 16 FFFFBC H 8/16 bit PPG 0/1 N/A # 17 FFFFB8 H ICR03 0000B3 H 8/16 bit PPG 2/3 N/A # 18 FFFFB4 H 8/16 bit PPG 4/5 N/A # 19 FFFFB0 H ICR04 0000B4 H 8/16 bit PPG 6/7 N/A # 20 FFFFAC H 8/16 bit PPG 8/9 N/A # 21 FFFFA8 H ICR05 0000B5 H 8/16 bit PPG A/B N/A # 22 FFFFA4 H 16-bit Reload Timer 0 *1 # 23 FFFFA0 H ICR06 0000B6 H 16-bit Reload Timer 1 *1 # 24 FFFF9C H Input Capture 0/1 *1 # 25 FFFF98 H ICR07 0000B7 H Output compare 0/1 *1 # 26 FFFF94 H Input Capture 2/3 *1 # 27 FFFF90 H ICR08 0000B8 H Output Compare 2/3 *1 # 28 FFFF8C H Input Capture 4/5 *1 # 29 FFFF88 H ICR09 0000B9 H Output Compare 4/5 *1 # 30 FFFF84 H 8/10 bit A/D Converter *1 # 31 FFFF80 H ICR10 0000BA H I/O Timer/Watch Timer N/A # 32 FFFF7C H Serial I/O *1 # 33 FFFF78 H ICR11 0000BB H Sound Generator N/A # 34 FFFF74 H UART 0 RX *2 # 35 FFFF70 H ICR12 0000BC H UART 0 TX *1 # 36 FFFF6C H UART 1 RX *2 # 37 FFFF68 H ICR13 0000BD H UART 1 TX *1 # 38 FFFF64 H UART 2 RX *2 # 39 FFFF60 H ICR14 0000BE H UART 2 TX *1 # 40 FFFF5C H Flash Memory N/A # 41 FFFF58 H ICR15 0000BF H Delayed interrupt N/A # 42 FFFF54 H

*1 : The interrupt request flag is cleared by the I2OS interrupt clear signal. *2 : The interrupt request flag is cleared by the I2OS interrupt clear signal. A stop request is available. N/A : The interrupt request flag is not cleared by the I2OS interrupt clear signal. Notes : • For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags are cleared by the I2OS interrupt clear signal.

• At the end of I2OS, the I2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the I2OS and in the meantime another interrupt flag is set by a hardware event, the later event is lost because the flag is cleared by the I2OS clear signal caused by the first event. So it is recommended not to use the I2OS for this interrupt number.
• If I2OS is enabled, I2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same I2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the I2OS, the other interrupt should be disabled.

n ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AVSS = 0.0 V) *1 : AVCC , AVRH, AVRL and DVCC shall not exceed VCC . AVRH and AVRL shall not exceed AVCC . Also, AVRL shall not exceed AVRH. *2 : VI and VO should not exceed VCC + 0.3V . VI should not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *3 : The maximum output current is a peak value for a corresponding pin. *4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin. *5 : T otal average current is an average current value observed for a 100 ms period for all corresponding pins. (Continued) Parameter Symbol Rating Unit RemarksMin Max Power supply voltage VCC VSS - 0.3 VSS + 6.0 V AV CC VSS - 0.3 VSS + 6.0 V V CC = AVCC *1 AVRH, AVRL VSS - 0.3 VSS + 6.0 V AV CC ‡ AVRH/L, AVRH ‡ AVRL * 1 DV CC VSS - 0.3 VSS + 6.0 V V CC ‡ DVCC Input voltage V I VSS - 0.3 VSS + 6.0 V * 2 Output voltage V O VSS - 0.3 VSS + 6.0 V * 2 Max clamp current I CLAMP -2.0 + 2.0 mA * 6 Total Max clamp current å | ICLAMP |— 2 0 m A * 6 “L” level Max output current IOL1 — 15 mA Normal output * 3 “L” level avg. output current IOLAV1 — 4 mA Normal output, average value * 4 “L” level Max output current IOL2 — 40 mA High current output * 3 “L” level avg. output currentIOLAV2 — 30 mA High current output, average value * 4 “L” level Max overall output currentå IOL1 — 100 mA Total normal output “L” level Max overall output currentå IOL2 330 mA Total high current output “L” level avg. overall output currentå IOLAV1 — 50 mA Total normal output, average value * 5 “L” level avg. overall output currentå IOLAV2 250 mA Total high current output, average value*5 “H” level Max output currentIOH1 — –15 mA Normal output * 3 “H” level avg. output currentIOHAV1 — –4 mA Normal output, average value * 4 “H” level Max output currentIOH2 — –40 mA High current output * 3 “H” level avg. output currentIOHAV2 — –30 mA High current output, average value * 4 “H” level Max overall output currentå IOH1 — –100 mA Total normal output “H” level Max overall output currentå IOH2 — –330 mA Total high current output “H” level avg. overall output currentå IOHAV1 — –50 mA Total normal output, average value * 5 “H” level avg. overall output currentå IOHAV2 — –250 mA Total high current output, average value*5 Power consumption PD — 500 mW MB90F594A, MB90F591A, MB90F594G, MB90F591G — 400 mW MB90594, MB90591, MB90594G, MB90591G Operating temperature TA –40 +85 °C Storage temperature TSTG –55 +150 °C

*6 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 toP95

• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pins does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input.
• Sample recommended circuits Note : Average output current = operating current · operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
• Input/Output equivalent circuits P-ch N-ch VCC R +B input (0 V to 16 V) Limiting resistance Protective diode

1. Recommended Conditions (VSS = AVSS = 0.0 V) * : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Value Unit Remarks Min Typ Max Power supply voltage VCC AV CC 4.5 5.0 5.5 V Under normal operation MB90V590A MB90V590G MB90F594A MB90F594G MB90594 MB90594G 3.0 — 5.5 V Maintains RAM data in stop mode 4.75 5.0 5.25 V Under normal operation MB90F591G MB90591G MB90F591A MB90591 3.0 — 5.25 V Maintains RAM data in stop mode Smooth capacitor C S 0.022 0.1 1.0 mF* Operating temperature TA –40 — +85 °C C C S

• C Pin Connection Diagram

1. DC Characteristics (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V–10 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V–5 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) * : The power supply current testing conditions are when using the external clock. (Continued) Parameter Symbol Pin name Condition Value Unit Remarks Min Typ Max Input H voltage VIHS CMOS hys- teresis input — 0.8 V CC —V CC +0.3 V VIHM MD input — V CC – 0.3 — V CC +0.3 V Input L voltage VILS CMOS hys- teresis input —V SS – 0.3 — 0.5V CC V VILM MD input — V SS – 0.3 — V SS + 0.3 V VILR RST , HST —V SS – 0.3 — 0.2V CC V Output H voltage VOH1 Normal output VCC = 4.5 V, IOH1 = –4.0 mA VCC – 0.5 — — V VOH2 High current output VCC = 4.5 V, IOH2 = –30.0 mA VCC – 0.5 — — V Output L voltage VOL1 Normal output VCC = 4.5 V, IOL1 = 4.0 mA —— 0 . 4 V VOL2 High current output VCC = 4.5 V, IOL2 = 30.0 mA —— 0 . 5 V Input leak current IIL — VCC = 5.5 V, VSS < VI < VCC –5 — 5 mA Analog input leak current IIAL AN0 to AN7 VCC = 5.5 V, AV SS < VI < AVCC –1 — 1 mA Power supply current * I CC VCC VCC = 5.0 V–10%, Internal frequency :

16 MHz,

tion. —3 76 0 m A MB90594/594G —5 08 0 m A MB90F594A/F594G —5 08 0 m A MB90F591A/F591G —4 56 0 m A MB90591/591G ICCS VCC = 5.0 V–10%, Internal frequency : At Sleep mode. —1 32 0 m A MB90594/594G —1 52 3 m A MB90F594A/F594G —1 52 3 m A MB90F591A/F591G —1 52 3 m A MB90591/591G ICTS VCC = 5.0 V–10%, Internal frequency :

2 MHz,

—0 . 3 0 . 6 m A MB90594/594G — 0.35 0.6 mA MB90F594A/F594G — 0.35 0.6 mA MB90F591A/F591G — 0.35 0.6 mA MB90591/591G ICCH VCC = 5.0 V–10%, At Stop mode, TA = 25°C —52 0 mA MB90594/594G —52 0 mA MB90F594A/F594G —52 0 mA MB90F591A/F591G —52 0 mA MB90591/591G

(Continued) (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V–10 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V–5 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) Parameter Symbol Pin name Condition Value Unit Remarks Min Typ Max Input capacity C IN Other than C, AV CC , AVSS , AVRH, AVRL, V CC, VSS, DVCC , DV SS , P70 to P87 —— 5 1 5 p F P70 to P87 — — 15 30 pF Pull-up resistance R UP RST — 25 50 100 k W Pull-down resistance R DOWN MD2 — 25 50 100 k W

1. AC Characteristics (1) Clock Timing (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V–10 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V–5 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) Example of Oscillation circuit Parameter Symbol Pin name Value Unit Remarks Min Typ Max Oscillation frequency f C X0, X1 3 — 16 MHz Oscillation cycle time t CYL X0, X1 62.5 — 333 ns Input clock pulse width P WH , PWL X0 10 — — ns Duty ratio is about 30 to 70%. Input clock rise and fall time tCR , tCF X0 — — 5 ns When using external clock Machine clock frequency f CP —1 . 5 —1 6 M H z Machine clock cycle time t CP — 62.5 — 666 ns Flash read cycle time t CYCFL —— 2 t CP — ns When Flash is accessed by CPU tCYL PWH tCF PWL tCR

0.8 VCC

0.2 VCC

• Clock Timing X0 X1 R C1 C2

• Guaranteed operation range Guaranteed PLL operation range (MB90F591G, MB90591G, MB90F591A, MB90591) Guaranteed operation range (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G) Guaranteed operation range (MB90F591G, MB90591G, MB90F591A, MB90591) Guaranteed PLL operation range (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G) 5.5 5.25 4.75 4.5 3.0 Power supply voltage VCC (V) 1.5 8 16 Machine clock fCP (MHz) 3 4 8 16 Machine clock fCP (MHz) Oscillation frequency fC (MHz)
• Oscillation clock frequency and machine clock frequency
• 4 ·3 ·2 ·1
• 1/2 (PLL off)

(2) Reset and Hardware Standby Input (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V–10 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V–5 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) *1 : “tcp” represents one cycle time of the machine clock. No reset can fully initialize the Flash Memory if it is performing the automatic algorithm. *2 : Oscillation time of oscillator is time that the amplitude reached the 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR / ceramic oscillator, the oscillation time is between hundreds of ms to several ms. In the external clock, the oscillation time is 0 ms. Parameter Symbol Pin name Value Unit Remarks Min Max Reset input time t RSTL RST 16 tCP *1 — ns Under normal operation Oscillation time of oscillator*2 + 16 tCP *1 — ms In stop mode Hardware standby input time tHSTL HST 16 tCP *1 — ns Under normal operation tRSTL , tHSTL 0.2VCC 0.2VCC RST 16 tCP Internal operation clock Internal reset Oscillation time of oscillator Oscillation setting time Instruction execution 90% of amplitude In Stop Mode

(3) Power On Reset (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V–10 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V–5 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) Notes : • VCC must be kept lower than 0.2 V before power-on.

• The above values are used for creating a power-on reset.
• Some registers in the device are initialized only upon a power-on reset. T o initialize these register, turn on the power supply using the above values. Parameter Symbol Pin name Condition Value Unit Remarks Min Max Power on rise time tR VCC 0.05 30 ms Power off time t OFF VCC 50 — ms Due to repetitive operation tR 2.7 V 0.2 V VCC 0.2 V0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock. VCC VSS RAM data being held It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.

(4) UART0/1/2, Serial I/O (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V–10 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V–5 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) * : tCP is the machine cycle (Unit : ns) Notes : • AC characteristic in CLK synchronized mode.

• CL is load capacity value of pins when testing. Parameter Symbol Pin name Condition Value Unit Remarks Min Max Serial clock cycle time t SCYC SCK0 to SCK3 Internal clock opera- tion output pins are C L = 80 pF + 1 TTL. 8 tCP *— n s SCK fl Þ SOT delay time t SLOV SCK0 to SCK3, SOT0 to SOT3 –80 80 ns Valid SIN Þ SCK › tIVSH SCK0 to SCK3, SIN0 to SIN3 100 — ns SCK › Þ Valid SIN hold time tSHIX SCK0 to SCK3, SIN0 to SIN3 60 — ns Serial clock "H" pulse width tSHSL SCK0 to SCK3 External clock oper- ation output pins are C L = 80 pF + 1 TTL. 4 tCP —n s Serial clock "L" pulse width tSLSH SCK0 to SCK3 4 t CP —n s SCK fl Þ SOT delay time t SLOV SCK0 to SCK3, SOT0 to SOT3 — 150 ns Valid SIN Þ SCK › tIVSH SCK0 to SCK3, SIN0 to SIN3 60 — ns SCK › Þ Valid SIN hold time tSHIX SCK0 to SCK3, SIN0 to SIN3 60 — ns SCK 2.4 V tSCYC 0.8 V SOT 0.8 V 2.4 V 0.8 V tSLOV SIN 0.5 VCC

0.5 VCC

• Internal Shift Clock Mode

(5)Timer Input Timing (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V–10 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V–5 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) Parameter Symbol Pin name Condition Value Unit Remarks Min Max Input pulse width tTIWH TIN0 4 tCP — ns Under normal operation tTIWL IN0 to IN5 1 — ms In stop mode SCK 0.8 VCC tSLSH 0.8 V 2.4 V tSLOV SIN 0.5 VCC

• External Shift Clock Mode
• Timer Input Timing

(6)Trigger Input Timing (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V–10 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V–5 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) (7) Slew Rate High Current Outputs (MB90F591G, MB90591G, MB90F591A, MB90591, MB90594G and MB90F594G only) (MB90F594G, MB90594G : VCC = 5.0 V–10 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V–5 %, VSS = AVSS = 0.0 V, TA = -40 °C to +85 °C) Parameter Symbol Pin name Condition Value Unit Remarks Min Max Input pulse width tTRGH tTRGL INT0 to INT7, ADTG —5 t CP —n s Parameter Symbol Pin name Condition Value Unit Remarks Min Max Output Rise/Fall time tR2 tF2 Port P70 to P77, Port P80 to P87 —1 5 4 0 n s

• Trigger Input Timing
• Slew Rate Output Timing VH VL tR2 VH VL tF2 VH = VOL2 + 0.1 · (VOH2 - VOL2 ) VL = VOL2 + 0.9 · (VOH2 - VOL2 )

1. A/D Converter (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G : VCC = AVCC = 5.0 V–10 %, VSS = AVSS = 0.0 V, 3.0 V £ AVR+ - AVR-, TA = -40 °C to +85 °C) (MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = AVCC = 5.0 V–5 %, VSS = AVSS = 0.0 V, 3.0 V £ AVR+ - AVR-, TA = -40 °C to +85 °C) * : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped. Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution — — — — 10 bit Conversion error — — — — –5.0 LSB Nonlinearity error — — — — –2.5 LSB Differential linearity Zero transition voltage V OT AN0 to AN7 AVRL – 3.5 LSB AVRL + 0.5 LSB AVRL + 4.5 LSB mV Full scale transition voltage VFST AN0 to AN7 AVRH – 6.5 LSB AVRH – 1.5 LSB AVRH + 1.5 LSB mV Compare time — — 352t CP —— n s Internal frequency :

16 MHz

Sampling time — — 64t CP —— n s Internal frequency : Analog port input current I AIN AN0 to AN7 -1 — +1 mA Analog input voltage range VAIN AN0 to AN7 AVRL — AVRH V Reference voltage range — AVRH AVRL + 2.7 — AV CC V — AVRL 0 — AVRH – 2.7 V Power supply current IA AV CC —5— m A IAH AV CC —— 5 mA* Reference voltage current IR AVRH — 400 600 mA MB90594 MB90V590A MB90V590G MB90F594A MB90F594G MB90F591A MB90F591G — 140 600 mA MB90594G MB90591 MB90591G I RH AVRH — — 5 mA* Offset between input channels — AN0 to AN7 — — 4 LSB

1. A/D Converter Glossary Resolution : Analog changes that are identifiable with the A/D converter Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” « “00 0000 0001”) with the full-scale transition point (“11 1111 1110” « “11 1111 1111”) from actual con- version characteristics Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value T otal error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. (Continued) Total error 3FF 3FE 3FD 004 003 002 001 Analog inputAVRL AVRH Actual conversion value Digital output VNT (measured value)

0.5 LSB

{1 LSB · (N – 1) + 0.5 LSB} [V]AVRH – AVRL 1024

1 LSB = (Theoretical value)

VOT (Theoretical value) = AVRL + 0.5 LSB[V] VFST (Theoretical value) = AVRH – 1.5 LSB[V] Total error for digital output N [LSB]VNT – {1 LSB · (N – 1) + 0.5 LSB}

1 LSB

VNT : Voltage at a transition of digital output from (N – 1) to N

(Continued) 7. Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions, :

• Output impedance values of the external circuit of 15 kW or lower are recommended.
• When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 ms @machine clock of 16 MHz).
• E r r o r The smaller the | AVRH - AVRL |, the greater the error would become relatively. Linearity error 3FF 3FE 3FD 004 003 002 001 Analog inputAVRL AVRH Analog input AVRL AVRH Actual conversion characteristics V OT (measured value) VFST (measured value) Actual conversion value VNT {1 LSB · (N – 1)+ VOT } Theoretical characteristics Digital output Digital output Differential linearity error Theoretical characteristics V(N + 1)T (measured value) Actual conversion value VNT (measured value) Actual conversion value Linearity error of digital output N VOT : Voltage at transition of digital output from “000H ” to “001H ” VFST : Voltage at transition of digital output from “3FEH ” to “3FFH ” [LSB]VNT – {1 LSB · (N – 1) + VOT }

[V]VFST – VOT 1022 =1 LSB – 1 LSB [LSB]V(N + 1)T – VNT =Differential linearity error of digital N N + 1 N N – 1 N – 2 (measured value) Comparator Analog input 30 pF Max 3.2 kW Max

• Equipment of analog input circuit model Note : Listed values must be considered as standards.

1. Flash Memory

• Erase and Programming Performance Parameter Condition Value Unit Remarks Min Typ Max Sector erase time TA = + 25 °C VCC = 5.0 V — 1 15 s Excludes 00H programming prior erasure Chip erase time — 7 — s MB90F594A/F594G Excludes 00H programming prior erasure— 12 — s MB90F591A/F591G Word (16-bit) programming time — 16 3,600 ns Excludes system-level overhead Erase/Program cycle — 10,000 — — cycle

(Continued) IOH1 [mA] VOH1 [V] VOH1 – IOH1 (Vcc = 4.5 V, TA = +25˚C) 3.5 2.5 1.5 0.5 4.5 VOH2 [V] IOH2 [mA] VOH2 – IOH2 (Vcc = 4.5 V, TA = +25˚C) 0 -40 -30-20-10 3.5 2.5 1.5 0.5 4.5 VOL1 [V] VOL1 – IOL1 (Vcc = 4.5 V, TA = +25˚C) IOL1 [mA] 0.6 0.5 0.4 0.3 0.2 0.1 6.0 0.8 0.7 VOL2 [V] VOL2 – IOL2 (Vcc = 4.5 V, TA = +25˚C) IOL2 [mA] 0.5 0.4 0.3 0.2 0.1 0.6 0.7 0.8 Vcc [V] VIN [V] VIN – VCC (TA = +25˚C)5 0 6543 VIH VIL

• ••• “H” Level Input Voltage/“L Level Input Voltage (Hysteresis Input)

(Continued) VCC [V] ICC [mA] ICC – VCC (TA = +25˚C) fcp = 16 MHz fcp = 8 MHz fcp = 4 MHz fcp = 2 MHz ICCS [mA] VCC [V] ICCS – VCC (TA = +25˚C) 5.0 fcp = 4 MHz fcp = 2 MHz fcp = 8 MHz fcp = 16 MHz VCC [V] ICTS [/K6DA] ICTS – VCC (TA = +25˚C) 600 500 400 300 200 100 800 700 fcp = 4 MHz fcp = 2 MHz ICCT [/K6DA] VCC [V] ICCH – VCC (TA = +25˚C)

• ••• Power Supply Voltage

Part number Package Remarks MB90594PF MB90591PF MB90594GPF MB90F594GPF MB90F594APF MB90F591APF MB90F591GPF MB90591GPF 100-pin Plastic QFP (FPT-100P-M06) MB90V590ACR MB90V590GCR 256-pin Ceramic PGA (PGA-256C-A01) For evaluation

(FPT-100P-M06) Dimensions in mm (inches) C 2001 FUJITSU LIMITED F100008S-c-4-4 1 30 5180 100 14.00±0.20 (.551±.008) 17.90±0.40 (.705±.016) INDEX (.013±.002) M0.13(.005) "A" 0.17±0.06 (.007±.002) 0.10(.004) Details of "A" part 0~8° (.035±.006) 0.88±0.15 (.031±.008) 0.80±0.20 0.25(.010)3.00 +0.35 –0.20 +.014 –.008 .118 (Mounting height) 0.25±0.20 (.010±.008) (Stand off)

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